提交 a22f803c 编写于 作者: A Alex Deucher

drm/amdgpu: fix VCE ib alignment value

The VCE rings only require single dword alignment.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 c4795ca6
......@@ -299,7 +299,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
ib_size_alignment = 8;
ib_size_alignment = 1;
break;
default:
return -EINVAL;
......
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