提交 9cf8d1a3 编写于 作者: D David S. Miller

Merge branch 'for-davem' of...

Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
...@@ -564,3 +564,12 @@ Who: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> ...@@ -564,3 +564,12 @@ Who: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
---------------------------- ----------------------------
What: iwlwifi disable_hw_scan module parameters
When: 2.6.40
Why: Hareware scan is the prefer method for iwlwifi devices for
scanning operation. Remove software scan support for all the
iwlwifi devices.
Who: Wey-Yi Guy <wey-yi.w.guy@intel.com>
----------------------------
...@@ -6457,7 +6457,7 @@ WL1271 WIRELESS DRIVER ...@@ -6457,7 +6457,7 @@ WL1271 WIRELESS DRIVER
M: Luciano Coelho <luciano.coelho@nokia.com> M: Luciano Coelho <luciano.coelho@nokia.com>
L: linux-wireless@vger.kernel.org L: linux-wireless@vger.kernel.org
W: http://wireless.kernel.org W: http://wireless.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/luca/wl12xx.git
S: Maintained S: Maintained
F: drivers/net/wireless/wl12xx/wl1271* F: drivers/net/wireless/wl12xx/wl1271*
F: include/linux/wl12xx.h F: include/linux/wl12xx.h
......
...@@ -213,7 +213,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { ...@@ -213,7 +213,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
{ {
.name = "wl1271", .name = "wl1271",
.mmc = 3, .mmc = 3,
.wires = 4, .caps = MMC_CAP_4_BIT_DATA,
.gpio_wp = -EINVAL, .gpio_wp = -EINVAL,
.gpio_cd = -EINVAL, .gpio_cd = -EINVAL,
.nonremovable = true, .nonremovable = true,
......
...@@ -54,8 +54,6 @@ MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>"); ...@@ -54,8 +54,6 @@ MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Atheros AR9170 802.11n USB wireless"); MODULE_DESCRIPTION("Atheros AR9170 802.11n USB wireless");
MODULE_FIRMWARE("ar9170.fw"); MODULE_FIRMWARE("ar9170.fw");
MODULE_FIRMWARE("ar9170-1.fw");
MODULE_FIRMWARE("ar9170-2.fw");
enum ar9170_requirements { enum ar9170_requirements {
AR9170_REQ_FW1_ONLY = 1, AR9170_REQ_FW1_ONLY = 1,
......
...@@ -35,7 +35,6 @@ static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ...@@ -35,7 +35,6 @@ static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
struct ath_ani { struct ath_ani {
bool caldone; bool caldone;
int16_t noise_floor;
unsigned int longcal_timer; unsigned int longcal_timer;
unsigned int shortcal_timer; unsigned int shortcal_timer;
unsigned int resetcal_timer; unsigned int resetcal_timer;
...@@ -103,14 +102,12 @@ enum ath_cipher { ...@@ -103,14 +102,12 @@ enum ath_cipher {
* @read: Register read * @read: Register read
* @write: Register write * @write: Register write
* @enable_write_buffer: Enable multiple register writes * @enable_write_buffer: Enable multiple register writes
* @disable_write_buffer: Disable multiple register writes * @write_flush: flush buffered register writes and disable buffering
* @write_flush: Flush buffered register writes
*/ */
struct ath_ops { struct ath_ops {
unsigned int (*read)(void *, u32 reg_offset); unsigned int (*read)(void *, u32 reg_offset);
void (*write)(void *, u32 val, u32 reg_offset); void (*write)(void *, u32 val, u32 reg_offset);
void (*enable_write_buffer)(void *); void (*enable_write_buffer)(void *);
void (*disable_write_buffer)(void *);
void (*write_flush) (void *); void (*write_flush) (void *);
}; };
......
...@@ -52,6 +52,7 @@ ...@@ -52,6 +52,7 @@
#include <linux/ethtool.h> #include <linux/ethtool.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/etherdevice.h>
#include <net/ieee80211_radiotap.h> #include <net/ieee80211_radiotap.h>
...@@ -509,8 +510,71 @@ ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) ...@@ -509,8 +510,71 @@ ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
} }
} }
struct ath_vif_iter_data {
const u8 *hw_macaddr;
u8 mask[ETH_ALEN];
u8 active_mac[ETH_ALEN]; /* first active MAC */
bool need_set_hw_addr;
bool found_active;
bool any_assoc;
};
static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
{
struct ath_vif_iter_data *iter_data = data;
int i;
if (iter_data->hw_macaddr)
for (i = 0; i < ETH_ALEN; i++)
iter_data->mask[i] &=
~(iter_data->hw_macaddr[i] ^ mac[i]);
if (!iter_data->found_active) {
iter_data->found_active = true;
memcpy(iter_data->active_mac, mac, ETH_ALEN);
}
if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
iter_data->need_set_hw_addr = false;
if (!iter_data->any_assoc) {
struct ath5k_vif *avf = (void *)vif->drv_priv;
if (avf->assoc)
iter_data->any_assoc = true;
}
}
void ath5k_update_bssid_mask(struct ath5k_softc *sc, struct ieee80211_vif *vif)
{
struct ath_common *common = ath5k_hw_common(sc->ah);
struct ath_vif_iter_data iter_data;
/*
* Use the hardware MAC address as reference, the hardware uses it
* together with the BSSID mask when matching addresses.
*/
iter_data.hw_macaddr = common->macaddr;
memset(&iter_data.mask, 0xff, ETH_ALEN);
iter_data.found_active = false;
iter_data.need_set_hw_addr = true;
if (vif)
ath_vif_iter(&iter_data, vif->addr, vif);
/* Get list of all active MAC addresses */
ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
&iter_data);
memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
if (iter_data.need_set_hw_addr && iter_data.found_active)
ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
}
static void static void
ath5k_mode_setup(struct ath5k_softc *sc) ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
{ {
struct ath5k_hw *ah = sc->ah; struct ath5k_hw *ah = sc->ah;
u32 rfilt; u32 rfilt;
...@@ -520,7 +584,7 @@ ath5k_mode_setup(struct ath5k_softc *sc) ...@@ -520,7 +584,7 @@ ath5k_mode_setup(struct ath5k_softc *sc)
ath5k_hw_set_rx_filter(ah, rfilt); ath5k_hw_set_rx_filter(ah, rfilt);
if (ath5k_hw_hasbssidmask(ah)) if (ath5k_hw_hasbssidmask(ah))
ath5k_hw_set_bssid_mask(ah, sc->bssidmask); ath5k_update_bssid_mask(sc, vif);
/* configure operational mode */ /* configure operational mode */
ath5k_hw_set_opmode(ah, sc->opmode); ath5k_hw_set_opmode(ah, sc->opmode);
...@@ -698,13 +762,13 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, ...@@ -698,13 +762,13 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
flags |= AR5K_TXDESC_RTSENA; flags |= AR5K_TXDESC_RTSENA;
cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
sc->vif, pktlen, info)); info->control.vif, pktlen, info));
} }
if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
flags |= AR5K_TXDESC_CTSENA; flags |= AR5K_TXDESC_CTSENA;
cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
sc->vif, pktlen, info)); info->control.vif, pktlen, info));
} }
ret = ah->ah_setup_tx_desc(ah, ds, pktlen, ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
ieee80211_get_hdrlen_from_skb(skb), padsize, ieee80211_get_hdrlen_from_skb(skb), padsize,
...@@ -806,10 +870,13 @@ ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) ...@@ -806,10 +870,13 @@ ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
list_add_tail(&bf->list, &sc->txbuf); list_add_tail(&bf->list, &sc->txbuf);
} }
/* beacon buffer */ /* beacon buffers */
bf->desc = ds; INIT_LIST_HEAD(&sc->bcbuf);
bf->daddr = da; for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
sc->bbuf = bf; bf->desc = ds;
bf->daddr = da;
list_add_tail(&bf->list, &sc->bcbuf);
}
return 0; return 0;
err_free: err_free:
...@@ -824,11 +891,12 @@ ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) ...@@ -824,11 +891,12 @@ ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
{ {
struct ath5k_buf *bf; struct ath5k_buf *bf;
ath5k_txbuf_free_skb(sc, sc->bbuf);
list_for_each_entry(bf, &sc->txbuf, list) list_for_each_entry(bf, &sc->txbuf, list)
ath5k_txbuf_free_skb(sc, bf); ath5k_txbuf_free_skb(sc, bf);
list_for_each_entry(bf, &sc->rxbuf, list) list_for_each_entry(bf, &sc->rxbuf, list)
ath5k_rxbuf_free_skb(sc, bf); ath5k_rxbuf_free_skb(sc, bf);
list_for_each_entry(bf, &sc->bcbuf, list)
ath5k_txbuf_free_skb(sc, bf);
/* Free memory associated with all descriptors */ /* Free memory associated with all descriptors */
pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
...@@ -837,7 +905,6 @@ ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) ...@@ -837,7 +905,6 @@ ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
kfree(sc->bufptr); kfree(sc->bufptr);
sc->bufptr = NULL; sc->bufptr = NULL;
sc->bbuf = NULL;
} }
...@@ -1083,7 +1150,7 @@ ath5k_rx_start(struct ath5k_softc *sc) ...@@ -1083,7 +1150,7 @@ ath5k_rx_start(struct ath5k_softc *sc)
spin_unlock_bh(&sc->rxbuflock); spin_unlock_bh(&sc->rxbuflock);
ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
ath5k_mode_setup(sc); /* set filters, etc. */ ath5k_mode_setup(sc, NULL); /* set filters, etc. */
ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
return 0; return 0;
...@@ -1366,6 +1433,7 @@ static bool ...@@ -1366,6 +1433,7 @@ static bool
ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
{ {
sc->stats.rx_all_count++; sc->stats.rx_all_count++;
sc->stats.rx_bytes_count += rs->rs_datalen;
if (unlikely(rs->rs_status)) { if (unlikely(rs->rs_status)) {
if (rs->rs_status & AR5K_RXERR_CRC) if (rs->rs_status & AR5K_RXERR_CRC)
...@@ -1544,6 +1612,7 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, ...@@ -1544,6 +1612,7 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
int i; int i;
sc->stats.tx_all_count++; sc->stats.tx_all_count++;
sc->stats.tx_bytes_count += skb->len;
info = IEEE80211_SKB_CB(skb); info = IEEE80211_SKB_CB(skb);
ieee80211_tx_info_clear_status(info); ieee80211_tx_info_clear_status(info);
...@@ -1642,7 +1711,7 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) ...@@ -1642,7 +1711,7 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
} }
} }
spin_unlock(&txq->lock); spin_unlock(&txq->lock);
if (txq->txq_len < ATH5K_TXQ_LEN_LOW) if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
ieee80211_wake_queue(sc->hw, txq->qnum); ieee80211_wake_queue(sc->hw, txq->qnum);
} }
...@@ -1750,6 +1819,7 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) ...@@ -1750,6 +1819,7 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
{ {
int ret; int ret;
struct ath5k_softc *sc = hw->priv; struct ath5k_softc *sc = hw->priv;
struct ath5k_vif *avf = (void *)vif->drv_priv;
struct sk_buff *skb; struct sk_buff *skb;
if (WARN_ON(!vif)) { if (WARN_ON(!vif)) {
...@@ -1766,11 +1836,11 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) ...@@ -1766,11 +1836,11 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
ath5k_debug_dump_skb(sc, skb, "BC ", 1); ath5k_debug_dump_skb(sc, skb, "BC ", 1);
ath5k_txbuf_free_skb(sc, sc->bbuf); ath5k_txbuf_free_skb(sc, avf->bbuf);
sc->bbuf->skb = skb; avf->bbuf->skb = skb;
ret = ath5k_beacon_setup(sc, sc->bbuf); ret = ath5k_beacon_setup(sc, avf->bbuf);
if (ret) if (ret)
sc->bbuf->skb = NULL; avf->bbuf->skb = NULL;
out: out:
return ret; return ret;
} }
...@@ -1786,16 +1856,14 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) ...@@ -1786,16 +1856,14 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
static void static void
ath5k_beacon_send(struct ath5k_softc *sc) ath5k_beacon_send(struct ath5k_softc *sc)
{ {
struct ath5k_buf *bf = sc->bbuf;
struct ath5k_hw *ah = sc->ah; struct ath5k_hw *ah = sc->ah;
struct ieee80211_vif *vif;
struct ath5k_vif *avf;
struct ath5k_buf *bf;
struct sk_buff *skb; struct sk_buff *skb;
ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION)) {
ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
return;
}
/* /*
* Check if the previous beacon has gone out. If * Check if the previous beacon has gone out. If
* not, don't don't try to post another: skip this * not, don't don't try to post another: skip this
...@@ -1824,6 +1892,28 @@ ath5k_beacon_send(struct ath5k_softc *sc) ...@@ -1824,6 +1892,28 @@ ath5k_beacon_send(struct ath5k_softc *sc)
sc->bmisscount = 0; sc->bmisscount = 0;
} }
if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
u64 tsf = ath5k_hw_get_tsf64(ah);
u32 tsftu = TSF_TO_TU(tsf);
int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
vif = sc->bslot[(slot + 1) % ATH_BCBUF];
ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
"tsf %llx tsftu %x intval %u slot %u vif %p\n",
(unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
} else /* only one interface */
vif = sc->bslot[0];
if (!vif)
return;
avf = (void *)vif->drv_priv;
bf = avf->bbuf;
if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
sc->opmode == NL80211_IFTYPE_MONITOR)) {
ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
return;
}
/* /*
* Stop any current dma and put the new frame on the queue. * Stop any current dma and put the new frame on the queue.
* This should never fail since we check above that no frames * This should never fail since we check above that no frames
...@@ -1836,17 +1926,17 @@ ath5k_beacon_send(struct ath5k_softc *sc) ...@@ -1836,17 +1926,17 @@ ath5k_beacon_send(struct ath5k_softc *sc)
/* refresh the beacon for AP mode */ /* refresh the beacon for AP mode */
if (sc->opmode == NL80211_IFTYPE_AP) if (sc->opmode == NL80211_IFTYPE_AP)
ath5k_beacon_update(sc->hw, sc->vif); ath5k_beacon_update(sc->hw, vif);
ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
ath5k_hw_start_tx_dma(ah, sc->bhalq); ath5k_hw_start_tx_dma(ah, sc->bhalq);
ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
sc->bhalq, (unsigned long long)bf->daddr, bf->desc); sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); skb = ieee80211_get_buffered_bc(sc->hw, vif);
while (skb) { while (skb) {
ath5k_tx_queue(sc->hw, skb, sc->cabq); ath5k_tx_queue(sc->hw, skb, sc->cabq);
skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); skb = ieee80211_get_buffered_bc(sc->hw, vif);
} }
sc->bsent++; sc->bsent++;
...@@ -1876,6 +1966,12 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) ...@@ -1876,6 +1966,12 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
u64 hw_tsf; u64 hw_tsf;
intval = sc->bintval & AR5K_BEACON_PERIOD; intval = sc->bintval & AR5K_BEACON_PERIOD;
if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
intval /= ATH_BCBUF; /* staggered multi-bss beacons */
if (intval < 15)
ATH5K_WARN(sc, "intval %u is too low, min 15\n",
intval);
}
if (WARN_ON(!intval)) if (WARN_ON(!intval))
return; return;
...@@ -2323,6 +2419,10 @@ ath5k_init(struct ath5k_softc *sc) ...@@ -2323,6 +2419,10 @@ ath5k_init(struct ath5k_softc *sc)
ath_hw_keyreset(common, (u16) i); ath_hw_keyreset(common, (u16) i);
ath5k_hw_set_ack_bitrate_high(ah, true); ath5k_hw_set_ack_bitrate_high(ah, true);
for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
sc->bslot[i] = NULL;
ret = 0; ret = 0;
done: done:
mmiowb(); mmiowb();
...@@ -2382,7 +2482,6 @@ ath5k_stop_hw(struct ath5k_softc *sc) ...@@ -2382,7 +2482,6 @@ ath5k_stop_hw(struct ath5k_softc *sc)
ATH5K_DBG(sc, ATH5K_DEBUG_RESET, ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
"putting device to sleep\n"); "putting device to sleep\n");
} }
ath5k_txbuf_free_skb(sc, sc->bbuf);
mmiowb(); mmiowb();
mutex_unlock(&sc->lock); mutex_unlock(&sc->lock);
...@@ -2587,9 +2686,9 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) ...@@ -2587,9 +2686,9 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
} }
SET_IEEE80211_PERM_ADDR(hw, mac); SET_IEEE80211_PERM_ADDR(hw, mac);
memcpy(&sc->lladdr, mac, ETH_ALEN);
/* All MAC address bits matter for ACKs */ /* All MAC address bits matter for ACKs */
memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); ath5k_update_bssid_mask(sc, NULL);
ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
...@@ -2687,31 +2786,91 @@ static int ath5k_add_interface(struct ieee80211_hw *hw, ...@@ -2687,31 +2786,91 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
{ {
struct ath5k_softc *sc = hw->priv; struct ath5k_softc *sc = hw->priv;
int ret; int ret;
struct ath5k_hw *ah = sc->ah;
struct ath5k_vif *avf = (void *)vif->drv_priv;
mutex_lock(&sc->lock); mutex_lock(&sc->lock);
if (sc->vif) {
ret = 0; if ((vif->type == NL80211_IFTYPE_AP ||
vif->type == NL80211_IFTYPE_ADHOC)
&& (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
ret = -ELNRNG;
goto end; goto end;
} }
sc->vif = vif; /* Don't allow other interfaces if one ad-hoc is configured.
* TODO: Fix the problems with ad-hoc and multiple other interfaces.
* We would need to operate the HW in ad-hoc mode to allow TSF updates
* for the IBSS, but this breaks with additional AP or STA interfaces
* at the moment. */
if (sc->num_adhoc_vifs ||
(sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
ret = -ELNRNG;
goto end;
}
switch (vif->type) { switch (vif->type) {
case NL80211_IFTYPE_AP: case NL80211_IFTYPE_AP:
case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_STATION:
case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_MESH_POINT: case NL80211_IFTYPE_MESH_POINT:
sc->opmode = vif->type; avf->opmode = vif->type;
break; break;
default: default:
ret = -EOPNOTSUPP; ret = -EOPNOTSUPP;
goto end; goto end;
} }
ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode); sc->nvifs++;
ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
/* Assign the vap/adhoc to a beacon xmit slot. */
if ((avf->opmode == NL80211_IFTYPE_AP) ||
(avf->opmode == NL80211_IFTYPE_ADHOC)) {
int slot;
WARN_ON(list_empty(&sc->bcbuf));
avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
list);
list_del(&avf->bbuf->list);
avf->bslot = 0;
for (slot = 0; slot < ATH_BCBUF; slot++) {
if (!sc->bslot[slot]) {
avf->bslot = slot;
break;
}
}
BUG_ON(sc->bslot[avf->bslot] != NULL);
sc->bslot[avf->bslot] = vif;
if (avf->opmode == NL80211_IFTYPE_AP)
sc->num_ap_vifs++;
else
sc->num_adhoc_vifs++;
}
/* Set combined mode - when APs are configured, operate in AP mode.
* Otherwise use the mode of the new interface. This can currently
* only deal with combinations of APs and STAs. Only one ad-hoc
* interfaces is allowed above.
*/
if (sc->num_ap_vifs)
sc->opmode = NL80211_IFTYPE_AP;
else
sc->opmode = vif->type;
ath5k_hw_set_opmode(ah, sc->opmode);
/* Any MAC address is fine, all others are included through the
* filter.
*/
memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
ath5k_hw_set_lladdr(sc->ah, vif->addr); ath5k_hw_set_lladdr(sc->ah, vif->addr);
ath5k_mode_setup(sc);
memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
ath5k_mode_setup(sc, vif);
ret = 0; ret = 0;
end: end:
...@@ -2724,15 +2883,29 @@ ath5k_remove_interface(struct ieee80211_hw *hw, ...@@ -2724,15 +2883,29 @@ ath5k_remove_interface(struct ieee80211_hw *hw,
struct ieee80211_vif *vif) struct ieee80211_vif *vif)
{ {
struct ath5k_softc *sc = hw->priv; struct ath5k_softc *sc = hw->priv;
u8 mac[ETH_ALEN] = {}; struct ath5k_vif *avf = (void *)vif->drv_priv;
unsigned int i;
mutex_lock(&sc->lock); mutex_lock(&sc->lock);
if (sc->vif != vif) sc->nvifs--;
goto end;
if (avf->bbuf) {
ath5k_txbuf_free_skb(sc, avf->bbuf);
list_add_tail(&avf->bbuf->list, &sc->bcbuf);
for (i = 0; i < ATH_BCBUF; i++) {
if (sc->bslot[i] == vif) {
sc->bslot[i] = NULL;
break;
}
}
avf->bbuf = NULL;
}
if (avf->opmode == NL80211_IFTYPE_AP)
sc->num_ap_vifs--;
else if (avf->opmode == NL80211_IFTYPE_ADHOC)
sc->num_adhoc_vifs--;
ath5k_hw_set_lladdr(sc->ah, mac); ath5k_update_bssid_mask(sc, NULL);
sc->vif = NULL;
end:
mutex_unlock(&sc->lock); mutex_unlock(&sc->lock);
} }
...@@ -2815,6 +2988,19 @@ static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, ...@@ -2815,6 +2988,19 @@ static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
return ((u64)(mfilt[1]) << 32) | mfilt[0]; return ((u64)(mfilt[1]) << 32) | mfilt[0];
} }
static bool ath_any_vif_assoc(struct ath5k_softc *sc)
{
struct ath_vif_iter_data iter_data;
iter_data.hw_macaddr = NULL;
iter_data.any_assoc = false;
iter_data.need_set_hw_addr = false;
iter_data.found_active = true;
ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
&iter_data);
return iter_data.any_assoc;
}
#define SUPPORTED_FIF_FLAGS \ #define SUPPORTED_FIF_FLAGS \
FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
...@@ -2885,7 +3071,7 @@ static void ath5k_configure_filter(struct ieee80211_hw *hw, ...@@ -2885,7 +3071,7 @@ static void ath5k_configure_filter(struct ieee80211_hw *hw,
/* FIF_BCN_PRBRESP_PROMISC really means to enable beacons /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
* and probes for any BSSID */ * and probes for any BSSID */
if (*new_flags & FIF_BCN_PRBRESP_PROMISC) if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
rfilt |= AR5K_RX_FILTER_BEACON; rfilt |= AR5K_RX_FILTER_BEACON;
/* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
...@@ -3070,14 +3256,13 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw, ...@@ -3070,14 +3256,13 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
struct ieee80211_bss_conf *bss_conf, struct ieee80211_bss_conf *bss_conf,
u32 changes) u32 changes)
{ {
struct ath5k_vif *avf = (void *)vif->drv_priv;
struct ath5k_softc *sc = hw->priv; struct ath5k_softc *sc = hw->priv;
struct ath5k_hw *ah = sc->ah; struct ath5k_hw *ah = sc->ah;
struct ath_common *common = ath5k_hw_common(ah); struct ath_common *common = ath5k_hw_common(ah);
unsigned long flags; unsigned long flags;
mutex_lock(&sc->lock); mutex_lock(&sc->lock);
if (WARN_ON(sc->vif != vif))
goto unlock;
if (changes & BSS_CHANGED_BSSID) { if (changes & BSS_CHANGED_BSSID) {
/* Cache for later use during resets */ /* Cache for later use during resets */
...@@ -3091,7 +3276,12 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw, ...@@ -3091,7 +3276,12 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
sc->bintval = bss_conf->beacon_int; sc->bintval = bss_conf->beacon_int;
if (changes & BSS_CHANGED_ASSOC) { if (changes & BSS_CHANGED_ASSOC) {
sc->assoc = bss_conf->assoc; avf->assoc = bss_conf->assoc;
if (bss_conf->assoc)
sc->assoc = bss_conf->assoc;
else
sc->assoc = ath_any_vif_assoc(sc);
if (sc->opmode == NL80211_IFTYPE_STATION) if (sc->opmode == NL80211_IFTYPE_STATION)
set_beacon_filter(hw, sc->assoc); set_beacon_filter(hw, sc->assoc);
ath5k_hw_set_ledstate(sc->ah, sc->assoc ? ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
...@@ -3119,7 +3309,6 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw, ...@@ -3119,7 +3309,6 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
BSS_CHANGED_BEACON_INT)) BSS_CHANGED_BEACON_INT))
ath5k_beacon_config(sc); ath5k_beacon_config(sc);
unlock:
mutex_unlock(&sc->lock); mutex_unlock(&sc->lock);
} }
...@@ -3394,6 +3583,8 @@ ath5k_pci_probe(struct pci_dev *pdev, ...@@ -3394,6 +3583,8 @@ ath5k_pci_probe(struct pci_dev *pdev,
hw->max_rate_tries = 11; hw->max_rate_tries = 11;
} }
hw->vif_data_size = sizeof(struct ath5k_vif);
/* Finish private driver data initialization */ /* Finish private driver data initialization */
ret = ath5k_attach(pdev, hw); ret = ath5k_attach(pdev, hw);
if (ret) if (ret)
......
...@@ -58,8 +58,7 @@ ...@@ -58,8 +58,7 @@
#define ATH_RXBUF 40 /* number of RX buffers */ #define ATH_RXBUF 40 /* number of RX buffers */
#define ATH_TXBUF 200 /* number of TX buffers */ #define ATH_TXBUF 200 /* number of TX buffers */
#define ATH_BCBUF 1 /* number of beacon buffers */ #define ATH_BCBUF 4 /* number of beacon buffers */
#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */ #define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */ #define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
...@@ -122,6 +121,13 @@ struct ath5k_statistics { ...@@ -122,6 +121,13 @@ struct ath5k_statistics {
/* frame errors */ /* frame errors */
unsigned int rx_all_count; /* all RX frames, including errors */ unsigned int rx_all_count; /* all RX frames, including errors */
unsigned int tx_all_count; /* all TX frames, including errors */ unsigned int tx_all_count; /* all TX frames, including errors */
unsigned int rx_bytes_count; /* all RX bytes, including errored pks
* and the MAC headers for each packet
*/
unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
* and the MAC headers and padding for
* each packet.
*/
unsigned int rxerr_crc; unsigned int rxerr_crc;
unsigned int rxerr_phy; unsigned int rxerr_phy;
unsigned int rxerr_phy_code[32]; unsigned int rxerr_phy_code[32];
...@@ -152,6 +158,14 @@ struct ath5k_statistics { ...@@ -152,6 +158,14 @@ struct ath5k_statistics {
#define ATH_CHAN_MAX (14+14+14+252+20) #define ATH_CHAN_MAX (14+14+14+252+20)
#endif #endif
struct ath5k_vif {
bool assoc; /* are we associated or not */
enum nl80211_iftype opmode;
int bslot;
struct ath5k_buf *bbuf; /* beacon buffer */
u8 lladdr[ETH_ALEN];
};
/* Software Carrier, keeps track of the driver state /* Software Carrier, keeps track of the driver state
* associated with an instance of a device */ * associated with an instance of a device */
struct ath5k_softc { struct ath5k_softc {
...@@ -188,10 +202,11 @@ struct ath5k_softc { ...@@ -188,10 +202,11 @@ struct ath5k_softc {
unsigned int curmode; /* current phy mode */ unsigned int curmode; /* current phy mode */
struct ieee80211_channel *curchan; /* current h/w channel */ struct ieee80211_channel *curchan; /* current h/w channel */
struct ieee80211_vif *vif; u16 nvifs;
enum ath5k_int imask; /* interrupt mask copy */ enum ath5k_int imask; /* interrupt mask copy */
u8 lladdr[ETH_ALEN];
u8 bssidmask[ETH_ALEN]; u8 bssidmask[ETH_ALEN];
unsigned int led_pin, /* GPIO pin for driving LED */ unsigned int led_pin, /* GPIO pin for driving LED */
...@@ -219,7 +234,10 @@ struct ath5k_softc { ...@@ -219,7 +234,10 @@ struct ath5k_softc {
spinlock_t block; /* protects beacon */ spinlock_t block; /* protects beacon */
struct tasklet_struct beacontq; /* beacon intr tasklet */ struct tasklet_struct beacontq; /* beacon intr tasklet */
struct ath5k_buf *bbuf; /* beacon buffer */ struct list_head bcbuf; /* beacon buffer */
struct ieee80211_vif *bslot[ATH_BCBUF];
u16 num_ap_vifs;
u16 num_adhoc_vifs;
unsigned int bhalq, /* SW q for outgoing beacons */ unsigned int bhalq, /* SW q for outgoing beacons */
bmisscount, /* missed beacon transmits */ bmisscount, /* missed beacon transmits */
bintval, /* beacon interval in TU */ bintval, /* beacon interval in TU */
......
...@@ -587,6 +587,8 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf, ...@@ -587,6 +587,8 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
st->rxerr_jumbo*100/st->rx_all_count : 0); st->rxerr_jumbo*100/st->rx_all_count : 0);
len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%d]\n", len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%d]\n",
st->rx_all_count); st->rx_all_count);
len += snprintf(buf+len, sizeof(buf)-len, "RX-all-bytes\t%d\n",
st->rx_bytes_count);
len += snprintf(buf+len, sizeof(buf)-len, len += snprintf(buf+len, sizeof(buf)-len,
"\nTX\n---------------------\n"); "\nTX\n---------------------\n");
...@@ -604,6 +606,8 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf, ...@@ -604,6 +606,8 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
st->txerr_filt*100/st->tx_all_count : 0); st->txerr_filt*100/st->tx_all_count : 0);
len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%d]\n", len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%d]\n",
st->tx_all_count); st->tx_all_count);
len += snprintf(buf+len, sizeof(buf)-len, "TX-all-bytes\t%d\n",
st->tx_bytes_count);
if (len > sizeof(buf)) if (len > sizeof(buf))
len = sizeof(buf); len = sizeof(buf);
......
...@@ -167,7 +167,7 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, ...@@ -167,7 +167,7 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
* ieee80211_duration() for a brief description of * ieee80211_duration() for a brief description of
* what rate we should choose to TX ACKs. */ * what rate we should choose to TX ACKs. */
tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw, tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
sc->vif, 10, rate)); NULL, 10, rate));
ath5k_hw_reg_write(ah, tx_time, reg); ath5k_hw_reg_write(ah, tx_time, reg);
...@@ -1060,7 +1060,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, ...@@ -1060,7 +1060,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
* XXX: rethink this after new mode changes to * XXX: rethink this after new mode changes to
* mac80211 are integrated */ * mac80211 are integrated */
if (ah->ah_version == AR5K_AR5212 && if (ah->ah_version == AR5K_AR5212 &&
ah->ah_sc->vif != NULL) ah->ah_sc->nvifs)
ath5k_hw_write_rate_duration(ah, mode); ath5k_hw_write_rate_duration(ah, mode);
/* /*
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#define HAL_PROCESS_ANI 0x00000001 #define HAL_PROCESS_ANI 0x00000001
#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI)) #define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI) && ah->curchan)
#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
...@@ -93,6 +93,13 @@ struct ath9k_mib_stats { ...@@ -93,6 +93,13 @@ struct ath9k_mib_stats {
u32 beacons; u32 beacons;
}; };
struct ath_cycle_counters {
u32 cycles;
u32 rx_frame;
u32 rx_clear;
u32 tx_frame;
};
/* INI default values for ANI registers */ /* INI default values for ANI registers */
struct ath9k_ani_default { struct ath9k_ani_default {
u16 m1ThreshLow; u16 m1ThreshLow;
...@@ -123,20 +130,11 @@ struct ar5416AniState { ...@@ -123,20 +130,11 @@ struct ar5416AniState {
u8 ofdmWeakSigDetectOff; u8 ofdmWeakSigDetectOff;
u8 cckWeakSigThreshold; u8 cckWeakSigThreshold;
u32 listenTime; u32 listenTime;
u32 ofdmTrigHigh;
u32 ofdmTrigLow;
int32_t cckTrigHigh;
int32_t cckTrigLow;
int32_t rssiThrLow; int32_t rssiThrLow;
int32_t rssiThrHigh; int32_t rssiThrHigh;
u32 noiseFloor; u32 noiseFloor;
u32 txFrameCount;
u32 rxFrameCount;
u32 cycleCount;
u32 ofdmPhyErrCount; u32 ofdmPhyErrCount;
u32 cckPhyErrCount; u32 cckPhyErrCount;
u32 ofdmPhyErrBase;
u32 cckPhyErrBase;
int16_t pktRssi[2]; int16_t pktRssi[2];
int16_t ofdmErrRssi[2]; int16_t ofdmErrRssi[2];
int16_t cckErrRssi[2]; int16_t cckErrRssi[2];
...@@ -166,8 +164,7 @@ struct ar5416Stats { ...@@ -166,8 +164,7 @@ struct ar5416Stats {
void ath9k_enable_mib_counters(struct ath_hw *ah); void ath9k_enable_mib_counters(struct ath_hw *ah);
void ath9k_hw_disable_mib_counters(struct ath_hw *ah); void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, void ath9k_hw_update_cycle_counters(struct ath_hw *ah);
u32 *rxf_pcnt, u32 *txf_pcnt);
void ath9k_hw_ani_setup(struct ath_hw *ah); void ath9k_hw_ani_setup(struct ath_hw *ah);
void ath9k_hw_ani_init(struct ath_hw *ah); void ath9k_hw_ani_init(struct ath_hw *ah);
int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
......
...@@ -613,14 +613,11 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah) ...@@ -613,14 +613,11 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
rx_chainmask = ah->rxchainmask; rx_chainmask = ah->rxchainmask;
tx_chainmask = ah->txchainmask; tx_chainmask = ah->txchainmask;
ENABLE_REGWRITE_BUFFER(ah);
switch (rx_chainmask) { switch (rx_chainmask) {
case 0x5: case 0x5:
DISABLE_REGWRITE_BUFFER(ah);
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
AR_PHY_SWAP_ALT_CHAIN); AR_PHY_SWAP_ALT_CHAIN);
ENABLE_REGWRITE_BUFFER(ah);
case 0x3: case 0x3:
if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
...@@ -630,17 +627,18 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah) ...@@ -630,17 +627,18 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
case 0x1: case 0x1:
case 0x2: case 0x2:
case 0x7: case 0x7:
ENABLE_REGWRITE_BUFFER(ah);
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
break; break;
default: default:
ENABLE_REGWRITE_BUFFER(ah);
break; break;
} }
REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (tx_chainmask == 0x5) { if (tx_chainmask == 0x5) {
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
...@@ -726,7 +724,6 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah, ...@@ -726,7 +724,6 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
...@@ -818,7 +815,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, ...@@ -818,7 +815,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
...@@ -849,7 +845,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah, ...@@ -849,7 +845,6 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (AR_SREV_9271(ah)) { if (AR_SREV_9271(ah)) {
if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1) if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
...@@ -1053,7 +1048,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, ...@@ -1053,7 +1048,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
enum ath9k_ani_cmd cmd, enum ath9k_ani_cmd cmd,
int param) int param)
{ {
struct ar5416AniState *aniState = ah->curani; struct ar5416AniState *aniState = &ah->curchan->ani;
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
switch (cmd & ah->ani_function) { switch (cmd & ah->ani_function) {
...@@ -1225,8 +1220,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, ...@@ -1225,8 +1220,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
aniState->firstepLevel, aniState->firstepLevel,
aniState->listenTime); aniState->listenTime);
ath_print(common, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
aniState->cycleCount,
aniState->ofdmPhyErrCount, aniState->ofdmPhyErrCount,
aniState->cckPhyErrCount); aniState->cckPhyErrCount);
...@@ -1237,9 +1231,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, ...@@ -1237,9 +1231,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
enum ath9k_ani_cmd cmd, enum ath9k_ani_cmd cmd,
int param) int param)
{ {
struct ar5416AniState *aniState = ah->curani;
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan; struct ath9k_channel *chan = ah->curchan;
struct ar5416AniState *aniState = &chan->ani;
s32 value, value2; s32 value, value2;
switch (cmd & ah->ani_function) { switch (cmd & ah->ani_function) {
...@@ -1478,15 +1472,13 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, ...@@ -1478,15 +1472,13 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
ath_print(common, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"ANI parameters: SI=%d, ofdmWS=%s FS=%d " "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
"MRCcck=%s listenTime=%d CC=%d listen=%d " "MRCcck=%s listenTime=%d "
"ofdmErrs=%d cckErrs=%d\n", "ofdmErrs=%d cckErrs=%d\n",
aniState->spurImmunityLevel, aniState->spurImmunityLevel,
!aniState->ofdmWeakSigDetectOff ? "on" : "off", !aniState->ofdmWeakSigDetectOff ? "on" : "off",
aniState->firstepLevel, aniState->firstepLevel,
!aniState->mrcCCKOff ? "on" : "off", !aniState->mrcCCKOff ? "on" : "off",
aniState->listenTime, aniState->listenTime,
aniState->cycleCount,
aniState->listenTime,
aniState->ofdmPhyErrCount, aniState->ofdmPhyErrCount,
aniState->cckPhyErrCount); aniState->cckPhyErrCount);
return true; return true;
...@@ -1526,16 +1518,12 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah, ...@@ -1526,16 +1518,12 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
*/ */
static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
{ {
struct ar5416AniState *aniState;
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan; struct ath9k_channel *chan = ah->curchan;
struct ar5416AniState *aniState = &chan->ani;
struct ath9k_ani_default *iniDef; struct ath9k_ani_default *iniDef;
int index;
u32 val; u32 val;
index = ath9k_hw_get_ani_channel_idx(ah, chan);
aniState = &ah->ani[index];
ah->curani = aniState;
iniDef = &aniState->iniDef; iniDef = &aniState->iniDef;
ath_print(common, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
...@@ -1579,8 +1567,6 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) ...@@ -1579,8 +1567,6 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
aniState->mrcCCKOff = true; /* not available on pre AR9003 */ aniState->mrcCCKOff = true; /* not available on pre AR9003 */
aniState->cycleCount = 0;
} }
static void ar5008_hw_set_nf_limits(struct ath_hw *ah) static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
......
...@@ -20,6 +20,13 @@ ...@@ -20,6 +20,13 @@
#define AR9285_CLCAL_REDO_THRESH 1 #define AR9285_CLCAL_REDO_THRESH 1
enum ar9002_cal_types {
ADC_GAIN_CAL = BIT(0),
ADC_DC_CAL = BIT(1),
IQ_MISMATCH_CAL = BIT(2),
};
static void ar9002_hw_setup_calibration(struct ath_hw *ah, static void ar9002_hw_setup_calibration(struct ath_hw *ah,
struct ath9k_cal_list *currCal) struct ath9k_cal_list *currCal)
{ {
...@@ -45,13 +52,6 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah, ...@@ -45,13 +52,6 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah,
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"starting ADC DC Calibration\n"); "starting ADC DC Calibration\n");
break; break;
case ADC_DC_INIT_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
ath_print(common, ATH_DBG_CALIBRATE,
"starting Init ADC DC Calibration\n");
break;
case TEMP_COMP_CAL:
break; /* Not supported */
} }
REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
...@@ -96,25 +96,6 @@ static bool ar9002_hw_per_calibration(struct ath_hw *ah, ...@@ -96,25 +96,6 @@ static bool ar9002_hw_per_calibration(struct ath_hw *ah,
return iscaldone; return iscaldone;
} }
/* Assumes you are talking about the currently configured channel */
static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
enum ath9k_cal_types calType)
{
struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
switch (calType & ah->supp_cals) {
case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
return true;
case ADC_GAIN_CAL:
case ADC_DC_CAL:
if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
conf_is_ht20(conf)))
return true;
break;
}
return false;
}
static void ar9002_hw_iqcal_collect(struct ath_hw *ah) static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
{ {
int i; int i;
...@@ -541,7 +522,6 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset) ...@@ -541,7 +522,6 @@ static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
REG_WRITE(ah, regList[i][0], regList[i][1]); REG_WRITE(ah, regList[i][0], regList[i][1]);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
...@@ -877,24 +857,28 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -877,24 +857,28 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
/* Enable IQ, ADC Gain and ADC DC offset CALs */ /* Enable IQ, ADC Gain and ADC DC offset CALs */
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) { ah->supp_cals = IQ_MISMATCH_CAL;
if (AR_SREV_9160_10_OR_LATER(ah) &&
!(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan))) {
ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
INIT_CAL(&ah->adcgain_caldata); INIT_CAL(&ah->adcgain_caldata);
INSERT_CAL(ah, &ah->adcgain_caldata); INSERT_CAL(ah, &ah->adcgain_caldata);
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling ADC Gain Calibration.\n"); "enabling ADC Gain Calibration.\n");
}
if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
INIT_CAL(&ah->adcdc_caldata); INIT_CAL(&ah->adcdc_caldata);
INSERT_CAL(ah, &ah->adcdc_caldata); INSERT_CAL(ah, &ah->adcdc_caldata);
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling ADC DC Calibration.\n"); "enabling ADC DC Calibration.\n");
} }
if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
INIT_CAL(&ah->iq_caldata); INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->iq_caldata); INSERT_CAL(ah, &ah->iq_caldata);
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n"); "enabling IQ Calibration.\n");
}
ah->cal_list_curr = ah->cal_list; ah->cal_list_curr = ah->cal_list;
...@@ -950,13 +934,6 @@ static const struct ath9k_percal_data adc_dc_cal_single_sample = { ...@@ -950,13 +934,6 @@ static const struct ath9k_percal_data adc_dc_cal_single_sample = {
ar9002_hw_adc_dccal_collect, ar9002_hw_adc_dccal_collect,
ar9002_hw_adc_dccal_calibrate ar9002_hw_adc_dccal_calibrate
}; };
static const struct ath9k_percal_data adc_init_dc_cal = {
ADC_DC_INIT_CAL,
MIN_CAL_SAMPLES,
INIT_LOG_COUNT,
ar9002_hw_adc_dccal_collect,
ar9002_hw_adc_dccal_calibrate
};
static void ar9002_hw_init_cal_settings(struct ath_hw *ah) static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
{ {
...@@ -973,16 +950,12 @@ static void ar9002_hw_init_cal_settings(struct ath_hw *ah) ...@@ -973,16 +950,12 @@ static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
&adc_gain_cal_single_sample; &adc_gain_cal_single_sample;
ah->adcdc_caldata.calData = ah->adcdc_caldata.calData =
&adc_dc_cal_single_sample; &adc_dc_cal_single_sample;
ah->adcdc_calinitdata.calData =
&adc_init_dc_cal;
} else { } else {
ah->iq_caldata.calData = &iq_cal_multi_sample; ah->iq_caldata.calData = &iq_cal_multi_sample;
ah->adcgain_caldata.calData = ah->adcgain_caldata.calData =
&adc_gain_cal_multi_sample; &adc_gain_cal_multi_sample;
ah->adcdc_caldata.calData = ah->adcdc_caldata.calData =
&adc_dc_cal_multi_sample; &adc_dc_cal_multi_sample;
ah->adcdc_calinitdata.calData =
&adc_init_dc_cal;
} }
ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
} }
...@@ -996,7 +969,6 @@ void ar9002_hw_attach_calib_ops(struct ath_hw *ah) ...@@ -996,7 +969,6 @@ void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
priv_ops->init_cal_settings = ar9002_hw_init_cal_settings; priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
priv_ops->init_cal = ar9002_hw_init_cal; priv_ops->init_cal = ar9002_hw_init_cal;
priv_ops->setup_calibration = ar9002_hw_setup_calibration; priv_ops->setup_calibration = ar9002_hw_setup_calibration;
priv_ops->iscal_supported = ar9002_hw_iscal_supported;
ops->calibrate = ar9002_hw_calibrate; ops->calibrate = ar9002_hw_calibrate;
} }
...@@ -371,7 +371,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah, ...@@ -371,7 +371,6 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
udelay(1000); udelay(1000);
...@@ -468,7 +467,6 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah) ...@@ -468,7 +467,6 @@ static int ar9002_hw_get_radiorev(struct ath_hw *ah)
REG_WRITE(ah, AR_PHY(0x20), 0x00010000); REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
...@@ -574,11 +572,6 @@ void ar9002_hw_attach_ops(struct ath_hw *ah) ...@@ -574,11 +572,6 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
ar9002_hw_attach_calib_ops(ah); ar9002_hw_attach_calib_ops(ah);
ar9002_hw_attach_mac_ops(ah); ar9002_hw_attach_mac_ops(ah);
if (modparam_force_new_ani)
ath9k_hw_attach_ani_ops_new(ah);
else
ath9k_hw_attach_ani_ops_old(ah);
} }
void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
...@@ -627,6 +620,4 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -627,6 +620,4 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
...@@ -415,7 +415,6 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah, ...@@ -415,7 +415,6 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
static void ar9002_olc_init(struct ath_hw *ah) static void ar9002_olc_init(struct ath_hw *ah)
......
...@@ -18,6 +18,11 @@ ...@@ -18,6 +18,11 @@
#include "hw-ops.h" #include "hw-ops.h"
#include "ar9003_phy.h" #include "ar9003_phy.h"
enum ar9003_cal_types {
IQ_MISMATCH_CAL = BIT(0),
TEMP_COMP_CAL = BIT(1),
};
static void ar9003_hw_setup_calibration(struct ath_hw *ah, static void ar9003_hw_setup_calibration(struct ath_hw *ah,
struct ath9k_cal_list *currCal) struct ath9k_cal_list *currCal)
{ {
...@@ -50,11 +55,6 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah, ...@@ -50,11 +55,6 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"starting Temperature Compensation Calibration\n"); "starting Temperature Compensation Calibration\n");
break; break;
case ADC_DC_INIT_CAL:
case ADC_GAIN_CAL:
case ADC_DC_CAL:
/* Not yet */
break;
} }
} }
...@@ -314,27 +314,6 @@ static const struct ath9k_percal_data iq_cal_single_sample = { ...@@ -314,27 +314,6 @@ static const struct ath9k_percal_data iq_cal_single_sample = {
static void ar9003_hw_init_cal_settings(struct ath_hw *ah) static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
{ {
ah->iq_caldata.calData = &iq_cal_single_sample; ah->iq_caldata.calData = &iq_cal_single_sample;
ah->supp_cals = IQ_MISMATCH_CAL;
}
static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
enum ath9k_cal_types calType)
{
switch (calType & ah->supp_cals) {
case IQ_MISMATCH_CAL:
/*
* XXX: Run IQ Mismatch for non-CCK only
* Note that CHANNEL_B is never set though.
*/
return true;
case ADC_GAIN_CAL:
case ADC_DC_CAL:
return false;
case TEMP_COMP_CAL:
return true;
}
return false;
} }
/* /*
...@@ -773,15 +752,16 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, ...@@ -773,15 +752,16 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
/* Initialize list pointers */ /* Initialize list pointers */
ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
ah->supp_cals = IQ_MISMATCH_CAL;
if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { if (ah->supp_cals & IQ_MISMATCH_CAL) {
INIT_CAL(&ah->iq_caldata); INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->iq_caldata); INSERT_CAL(ah, &ah->iq_caldata);
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n"); "enabling IQ Calibration.\n");
} }
if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) { if (ah->supp_cals & TEMP_COMP_CAL) {
INIT_CAL(&ah->tempCompCalData); INIT_CAL(&ah->tempCompCalData);
INSERT_CAL(ah, &ah->tempCompCalData); INSERT_CAL(ah, &ah->tempCompCalData);
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
...@@ -808,7 +788,6 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah) ...@@ -808,7 +788,6 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
priv_ops->init_cal_settings = ar9003_hw_init_cal_settings; priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
priv_ops->init_cal = ar9003_hw_init_cal; priv_ops->init_cal = ar9003_hw_init_cal;
priv_ops->setup_calibration = ar9003_hw_setup_calibration; priv_ops->setup_calibration = ar9003_hw_setup_calibration;
priv_ops->iscal_supported = ar9003_hw_iscal_supported;
ops->calibrate = ar9003_hw_calibrate; ops->calibrate = ar9003_hw_calibrate;
} }
...@@ -333,6 +333,4 @@ void ar9003_hw_attach_ops(struct ath_hw *ah) ...@@ -333,6 +333,4 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
ar9003_hw_attach_phy_ops(ah); ar9003_hw_attach_phy_ops(ah);
ar9003_hw_attach_calib_ops(ah); ar9003_hw_attach_calib_ops(ah);
ar9003_hw_attach_mac_ops(ah); ar9003_hw_attach_mac_ops(ah);
ath9k_hw_attach_ani_ops_new(ah);
} }
...@@ -747,9 +747,9 @@ static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) ...@@ -747,9 +747,9 @@ static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
static bool ar9003_hw_ani_control(struct ath_hw *ah, static bool ar9003_hw_ani_control(struct ath_hw *ah,
enum ath9k_ani_cmd cmd, int param) enum ath9k_ani_cmd cmd, int param)
{ {
struct ar5416AniState *aniState = ah->curani;
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan; struct ath9k_channel *chan = ah->curchan;
struct ar5416AniState *aniState = &chan->ani;
s32 value, value2; s32 value, value2;
switch (cmd & ah->ani_function) { switch (cmd & ah->ani_function) {
...@@ -1005,15 +1005,13 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, ...@@ -1005,15 +1005,13 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
ath_print(common, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"ANI parameters: SI=%d, ofdmWS=%s FS=%d " "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
"MRCcck=%s listenTime=%d CC=%d listen=%d " "MRCcck=%s listenTime=%d "
"ofdmErrs=%d cckErrs=%d\n", "ofdmErrs=%d cckErrs=%d\n",
aniState->spurImmunityLevel, aniState->spurImmunityLevel,
!aniState->ofdmWeakSigDetectOff ? "on" : "off", !aniState->ofdmWeakSigDetectOff ? "on" : "off",
aniState->firstepLevel, aniState->firstepLevel,
!aniState->mrcCCKOff ? "on" : "off", !aniState->mrcCCKOff ? "on" : "off",
aniState->listenTime, aniState->listenTime,
aniState->cycleCount,
aniState->listenTime,
aniState->ofdmPhyErrCount, aniState->ofdmPhyErrCount,
aniState->cckPhyErrCount); aniState->cckPhyErrCount);
return true; return true;
...@@ -1067,12 +1065,9 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) ...@@ -1067,12 +1065,9 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan; struct ath9k_channel *chan = ah->curchan;
struct ath9k_ani_default *iniDef; struct ath9k_ani_default *iniDef;
int index;
u32 val; u32 val;
index = ath9k_hw_get_ani_channel_idx(ah, chan); aniState = &ah->curchan->ani;
aniState = &ah->ani[index];
ah->curani = aniState;
iniDef = &aniState->iniDef; iniDef = &aniState->iniDef;
ath_print(common, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
...@@ -1116,8 +1111,6 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) ...@@ -1116,8 +1111,6 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
aniState->cycleCount = 0;
} }
void ar9003_hw_attach_phy_ops(struct ath_hw *ah) void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
...@@ -1232,7 +1225,7 @@ void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) ...@@ -1232,7 +1225,7 @@ void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
{ {
struct ath_common *common = ath9k_hw_common(ah); struct ath_common *common = ath9k_hw_common(ah);
u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status; u32 status;
if (likely(!(common->debug_mask & ATH_DBG_RESET))) if (likely(!(common->debug_mask & ATH_DBG_RESET)))
return; return;
...@@ -1261,11 +1254,13 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) ...@@ -1261,11 +1254,13 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
"** BB mode: BB_gen_controls=0x%08x **\n", "** BB mode: BB_gen_controls=0x%08x **\n",
REG_READ(ah, AR_PHY_GEN_CTRL)); REG_READ(ah, AR_PHY_GEN_CTRL));
if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt)) ath9k_hw_update_cycle_counters(ah);
#define PCT(_field) (ah->cc_delta._field * 100 / ah->cc_delta.cycles)
if (ah->cc_delta.cycles)
ath_print(common, ATH_DBG_RESET, ath_print(common, ATH_DBG_RESET,
"** BB busy times: rx_clear=%d%%, " "** BB busy times: rx_clear=%d%%, "
"rx_frame=%d%%, tx_frame=%d%% **\n", "rx_frame=%d%%, tx_frame=%d%% **\n",
rxc_pcnt, rxf_pcnt, txf_pcnt); PCT(rx_clear), PCT(rx_frame), PCT(tx_frame));
ath_print(common, ATH_DBG_RESET, ath_print(common, ATH_DBG_RESET,
"==== BB update: done ====\n\n"); "==== BB update: done ====\n\n");
......
...@@ -241,7 +241,6 @@ struct ath_buf { ...@@ -241,7 +241,6 @@ struct ath_buf {
dma_addr_t bf_daddr; /* physical addr of desc */ dma_addr_t bf_daddr; /* physical addr of desc */
dma_addr_t bf_buf_addr; /* physical addr of data buffer */ dma_addr_t bf_buf_addr; /* physical addr of data buffer */
bool bf_stale; bool bf_stale;
bool bf_isnullfunc;
bool bf_tx_aborted; bool bf_tx_aborted;
u16 bf_flags; u16 bf_flags;
struct ath_buf_state bf_state; struct ath_buf_state bf_state;
...@@ -349,7 +348,6 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, ...@@ -349,7 +348,6 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
u16 tid, u16 *ssn); u16 tid, u16 *ssn);
void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
void ath9k_enable_ps(struct ath_softc *sc);
/********/ /********/
/* VIFs */ /* VIFs */
...@@ -573,8 +571,6 @@ struct ath_ant_comb { ...@@ -573,8 +571,6 @@ struct ath_ant_comb {
#define PS_WAIT_FOR_PSPOLL_DATA BIT(2) #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
#define PS_WAIT_FOR_TX_ACK BIT(3) #define PS_WAIT_FOR_TX_ACK BIT(3)
#define PS_BEACON_SYNC BIT(4) #define PS_BEACON_SYNC BIT(4)
#define PS_NULLFUNC_COMPLETED BIT(5)
#define PS_ENABLED BIT(6)
struct ath_wiphy; struct ath_wiphy;
struct ath_rate_table; struct ath_rate_table;
......
...@@ -186,7 +186,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) ...@@ -186,7 +186,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
return true; return true;
} }
if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) if (!(ah->supp_cals & currCal->calData->calType))
return true; return true;
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
...@@ -300,7 +300,6 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -300,7 +300,6 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
} }
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
...@@ -346,34 +345,34 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -346,34 +345,34 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
struct ieee80211_channel *c = chan->chan; struct ieee80211_channel *c = chan->chan;
struct ath9k_hw_cal_data *caldata = ah->caldata; struct ath9k_hw_cal_data *caldata = ah->caldata;
if (!caldata)
return false;
chan->channelFlags &= (~CHANNEL_CW_INT); chan->channelFlags &= (~CHANNEL_CW_INT);
if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
ath_print(common, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF did not complete in calibration window\n"); "NF did not complete in calibration window\n");
nf = 0;
caldata->rawNoiseFloor = nf;
return false; return false;
} else { }
ath9k_hw_do_getnf(ah, nfarray);
ath9k_hw_nf_sanitize(ah, nfarray); ath9k_hw_do_getnf(ah, nfarray);
nf = nfarray[0]; ath9k_hw_nf_sanitize(ah, nfarray);
if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) nf = nfarray[0];
&& nf > nfThresh) { if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
ath_print(common, ATH_DBG_CALIBRATE, && nf > nfThresh) {
"noise floor failed detected; " ath_print(common, ATH_DBG_CALIBRATE,
"detected %d, threshold %d\n", "noise floor failed detected; "
nf, nfThresh); "detected %d, threshold %d\n",
chan->channelFlags |= CHANNEL_CW_INT; nf, nfThresh);
} chan->channelFlags |= CHANNEL_CW_INT;
}
if (!caldata) {
chan->noisefloor = nf;
return false;
} }
h = caldata->nfCalHist; h = caldata->nfCalHist;
caldata->nfcal_pending = false; caldata->nfcal_pending = false;
ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray); ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
caldata->rawNoiseFloor = h[0].privNF; chan->noisefloor = h[0].privNF;
return true; return true;
} }
...@@ -401,10 +400,10 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah, ...@@ -401,10 +400,10 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
{ {
if (!ah->caldata || !ah->caldata->rawNoiseFloor) if (!ah->curchan || !ah->curchan->noisefloor)
return ath9k_hw_get_default_nf(ah, chan); return ath9k_hw_get_default_nf(ah, chan);
return ah->caldata->rawNoiseFloor; return ah->curchan->noisefloor;
} }
EXPORT_SYMBOL(ath9k_hw_getchan_noise); EXPORT_SYMBOL(ath9k_hw_getchan_noise);
......
...@@ -58,14 +58,6 @@ struct ar5416IniArray { ...@@ -58,14 +58,6 @@ struct ar5416IniArray {
} \ } \
} while (0) } while (0)
enum ath9k_cal_types {
ADC_DC_INIT_CAL = 0x1,
ADC_GAIN_CAL = 0x2,
ADC_DC_CAL = 0x4,
IQ_MISMATCH_CAL = 0x8,
TEMP_COMP_CAL = 0x10,
};
enum ath9k_cal_state { enum ath9k_cal_state {
CAL_INACTIVE, CAL_INACTIVE,
CAL_WAITING, CAL_WAITING,
...@@ -80,7 +72,7 @@ enum ath9k_cal_state { ...@@ -80,7 +72,7 @@ enum ath9k_cal_state {
#define PER_MAX_LOG_COUNT 10 #define PER_MAX_LOG_COUNT 10
struct ath9k_percal_data { struct ath9k_percal_data {
enum ath9k_cal_types calType; u32 calType;
u32 calNumSamples; u32 calNumSamples;
u32 calCountMax; u32 calCountMax;
void (*calCollect) (struct ath_hw *); void (*calCollect) (struct ath_hw *);
......
...@@ -488,6 +488,8 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf, ...@@ -488,6 +488,8 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
struct ath_softc *sc = file->private_data; struct ath_softc *sc = file->private_data;
struct ath_wiphy *aphy = sc->pri_wiphy;
struct ieee80211_channel *chan = aphy->hw->conf.channel;
char buf[512]; char buf[512];
unsigned int len = 0; unsigned int len = 0;
int i; int i;
...@@ -498,7 +500,8 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf, ...@@ -498,7 +500,8 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
"primary: %s (%s chan=%d ht=%d)\n", "primary: %s (%s chan=%d ht=%d)\n",
wiphy_name(sc->pri_wiphy->hw->wiphy), wiphy_name(sc->pri_wiphy->hw->wiphy),
ath_wiphy_state_str(sc->pri_wiphy->state), ath_wiphy_state_str(sc->pri_wiphy->state),
sc->pri_wiphy->chan_idx, sc->pri_wiphy->chan_is_ht); ieee80211_frequency_to_channel(chan->center_freq),
aphy->chan_is_ht);
put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_STA_ID0), addr); put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_STA_ID0), addr);
put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4); put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4);
...@@ -545,11 +548,13 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf, ...@@ -545,11 +548,13 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
struct ath_wiphy *aphy = sc->sec_wiphy[i]; struct ath_wiphy *aphy = sc->sec_wiphy[i];
if (aphy == NULL) if (aphy == NULL)
continue; continue;
chan = aphy->hw->conf.channel;
len += snprintf(buf + len, sizeof(buf) - len, len += snprintf(buf + len, sizeof(buf) - len,
"secondary: %s (%s chan=%d ht=%d)\n", "secondary: %s (%s chan=%d ht=%d)\n",
wiphy_name(aphy->hw->wiphy), wiphy_name(aphy->hw->wiphy),
ath_wiphy_state_str(aphy->state), ath_wiphy_state_str(aphy->state),
aphy->chan_idx, aphy->chan_is_ht); ieee80211_frequency_to_channel(chan->center_freq),
aphy->chan_is_ht);
} }
if (len > sizeof(buf)) if (len > sizeof(buf))
len = sizeof(buf); len = sizeof(buf);
...@@ -696,6 +701,8 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf, ...@@ -696,6 +701,8 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
PR("DESC CFG Error: ", desc_cfg_err); PR("DESC CFG Error: ", desc_cfg_err);
PR("DATA Underrun: ", data_underrun); PR("DATA Underrun: ", data_underrun);
PR("DELIM Underrun: ", delim_underrun); PR("DELIM Underrun: ", delim_underrun);
PR("TX-Pkts-All: ", tx_pkts_all);
PR("TX-Bytes-All: ", tx_bytes_all);
if (len > size) if (len > size)
len = size; len = size;
...@@ -709,6 +716,9 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf, ...@@ -709,6 +716,9 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq, void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
struct ath_buf *bf, struct ath_tx_status *ts) struct ath_buf *bf, struct ath_tx_status *ts)
{ {
TX_STAT_INC(txq->axq_qnum, tx_pkts_all);
sc->debug.stats.txstats[txq->axq_qnum].tx_bytes_all += bf->bf_mpdu->len;
if (bf_isampdu(bf)) { if (bf_isampdu(bf)) {
if (bf_isxretried(bf)) if (bf_isxretried(bf))
TX_STAT_INC(txq->axq_qnum, a_xretries); TX_STAT_INC(txq->axq_qnum, a_xretries);
...@@ -803,6 +813,13 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf, ...@@ -803,6 +813,13 @@ static ssize_t read_file_recv(struct file *file, char __user *user_buf,
PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL); PHY_ERR("HT-LENGTH", ATH9K_PHYERR_HT_LENGTH_ILLEGAL);
PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL); PHY_ERR("HT-RATE", ATH9K_PHYERR_HT_RATE_ILLEGAL);
len += snprintf(buf + len, size - len,
"%18s : %10u\n", "RX-Pkts-All",
sc->debug.stats.rxstats.rx_pkts_all);
len += snprintf(buf + len, size - len,
"%18s : %10u\n", "RX-Bytes-All",
sc->debug.stats.rxstats.rx_bytes_all);
if (len > size) if (len > size)
len = size; len = size;
...@@ -821,6 +838,9 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs) ...@@ -821,6 +838,9 @@ void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs)
u32 phyerr; u32 phyerr;
RX_STAT_INC(rx_pkts_all);
sc->debug.stats.rxstats.rx_bytes_all += rs->rs_datalen;
if (rs->rs_status & ATH9K_RXERR_CRC) if (rs->rs_status & ATH9K_RXERR_CRC)
RX_STAT_INC(crc_err); RX_STAT_INC(crc_err);
if (rs->rs_status & ATH9K_RXERR_DECRYPT) if (rs->rs_status & ATH9K_RXERR_DECRYPT)
......
...@@ -89,6 +89,10 @@ struct ath_rc_stats { ...@@ -89,6 +89,10 @@ struct ath_rc_stats {
/** /**
* struct ath_tx_stats - Statistics about TX * struct ath_tx_stats - Statistics about TX
* @tx_pkts_all: No. of total frames transmitted, including ones that
may have had errors.
* @tx_bytes_all: No. of total bytes transmitted, including ones that
may have had errors.
* @queued: Total MPDUs (non-aggr) queued * @queued: Total MPDUs (non-aggr) queued
* @completed: Total MPDUs (non-aggr) completed * @completed: Total MPDUs (non-aggr) completed
* @a_aggr: Total no. of aggregates queued * @a_aggr: Total no. of aggregates queued
...@@ -107,6 +111,8 @@ struct ath_rc_stats { ...@@ -107,6 +111,8 @@ struct ath_rc_stats {
* @delim_urn: TX delimiter underrun errors * @delim_urn: TX delimiter underrun errors
*/ */
struct ath_tx_stats { struct ath_tx_stats {
u32 tx_pkts_all;
u32 tx_bytes_all;
u32 queued; u32 queued;
u32 completed; u32 completed;
u32 a_aggr; u32 a_aggr;
...@@ -124,6 +130,10 @@ struct ath_tx_stats { ...@@ -124,6 +130,10 @@ struct ath_tx_stats {
/** /**
* struct ath_rx_stats - RX Statistics * struct ath_rx_stats - RX Statistics
* @rx_pkts_all: No. of total frames received, including ones that
may have had errors.
* @rx_bytes_all: No. of total bytes received, including ones that
may have had errors.
* @crc_err: No. of frames with incorrect CRC value * @crc_err: No. of frames with incorrect CRC value
* @decrypt_crc_err: No. of frames whose CRC check failed after * @decrypt_crc_err: No. of frames whose CRC check failed after
decryption process completed decryption process completed
...@@ -136,6 +146,8 @@ struct ath_tx_stats { ...@@ -136,6 +146,8 @@ struct ath_tx_stats {
* @phy_err_stats: Individual PHY error statistics * @phy_err_stats: Individual PHY error statistics
*/ */
struct ath_rx_stats { struct ath_rx_stats {
u32 rx_pkts_all;
u32 rx_bytes_all;
u32 crc_err; u32 crc_err;
u32 decrypt_crc_err; u32 decrypt_crc_err;
u32 phy_err; u32 phy_err;
......
...@@ -179,6 +179,9 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, ...@@ -179,6 +179,9 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
struct modal_eep_4k_header *pModal = &eep->modalHeader; struct modal_eep_4k_header *pModal = &eep->modalHeader;
struct base_eep_header_4k *pBase = &eep->baseEepHeader; struct base_eep_header_4k *pBase = &eep->baseEepHeader;
u16 ver_minor;
ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
switch (param) { switch (param) {
case EEP_NFTHRESH_2: case EEP_NFTHRESH_2:
...@@ -204,7 +207,7 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, ...@@ -204,7 +207,7 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
case EEP_DB_2: case EEP_DB_2:
return pModal->db1_1; return pModal->db1_1;
case EEP_MINOR_REV: case EEP_MINOR_REV:
return pBase->version & AR5416_EEP_VER_MINOR_MASK; return ver_minor;
case EEP_TX_MASK: case EEP_TX_MASK:
return pBase->txMask; return pBase->txMask;
case EEP_RX_MASK: case EEP_RX_MASK:
...@@ -217,6 +220,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, ...@@ -217,6 +220,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
return pModal->version; return pModal->version;
case EEP_ANT_DIV_CTL1: case EEP_ANT_DIV_CTL1:
return pModal->antdiv_ctl1; return pModal->antdiv_ctl1;
case EEP_TXGAIN_TYPE:
if (ver_minor >= AR5416_EEP_MINOR_VER_19)
return pBase->txGainType;
else
return AR5416_EEP_TXGAIN_ORIGINAL;
default: default:
return 0; return 0;
} }
...@@ -500,7 +508,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, ...@@ -500,7 +508,6 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
} }
...@@ -832,7 +839,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, ...@@ -832,7 +839,6 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
static void ath9k_hw_4k_set_addac(struct ath_hw *ah, static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
......
...@@ -380,15 +380,6 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv) ...@@ -380,15 +380,6 @@ static void ath9k_enable_regwrite_buffer(void *hw_priv)
atomic_inc(&priv->wmi->mwrite_cnt); atomic_inc(&priv->wmi->mwrite_cnt);
} }
static void ath9k_disable_regwrite_buffer(void *hw_priv)
{
struct ath_hw *ah = (struct ath_hw *) hw_priv;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
atomic_dec(&priv->wmi->mwrite_cnt);
}
static void ath9k_regwrite_flush(void *hw_priv) static void ath9k_regwrite_flush(void *hw_priv)
{ {
struct ath_hw *ah = (struct ath_hw *) hw_priv; struct ath_hw *ah = (struct ath_hw *) hw_priv;
...@@ -397,6 +388,8 @@ static void ath9k_regwrite_flush(void *hw_priv) ...@@ -397,6 +388,8 @@ static void ath9k_regwrite_flush(void *hw_priv)
u32 rsp_status; u32 rsp_status;
int r; int r;
atomic_dec(&priv->wmi->mwrite_cnt);
mutex_lock(&priv->wmi->multi_write_mutex); mutex_lock(&priv->wmi->multi_write_mutex);
if (priv->wmi->multi_write_idx) { if (priv->wmi->multi_write_idx) {
...@@ -420,7 +413,6 @@ static const struct ath_ops ath9k_common_ops = { ...@@ -420,7 +413,6 @@ static const struct ath_ops ath9k_common_ops = {
.read = ath9k_regread, .read = ath9k_regread,
.write = ath9k_regwrite, .write = ath9k_regwrite,
.enable_write_buffer = ath9k_enable_regwrite_buffer, .enable_write_buffer = ath9k_enable_regwrite_buffer,
.disable_write_buffer = ath9k_disable_regwrite_buffer,
.write_flush = ath9k_regwrite_flush, .write_flush = ath9k_regwrite_flush,
}; };
......
...@@ -760,23 +760,12 @@ void ath9k_ani_work(struct work_struct *work) ...@@ -760,23 +760,12 @@ void ath9k_ani_work(struct work_struct *work)
ath9k_hw_ani_monitor(ah, ah->curchan); ath9k_hw_ani_monitor(ah, ah->curchan);
/* Perform calibration if necessary */ /* Perform calibration if necessary */
if (longcal || shortcal) { if (longcal || shortcal)
common->ani.caldone = common->ani.caldone =
ath9k_hw_calibrate(ah, ah->curchan, ath9k_hw_calibrate(ah, ah->curchan,
common->rx_chainmask, common->rx_chainmask,
longcal); longcal);
if (longcal)
common->ani.noise_floor =
ath9k_hw_getchan_noise(ah, ah->curchan);
ath_print(common, ATH_DBG_ANI,
" calibrate chan %u/%x nf: %d\n",
ah->curchan->channel,
ah->curchan->channelFlags,
common->ani.noise_floor);
}
ath9k_htc_ps_restore(priv); ath9k_htc_ps_restore(priv);
} }
......
...@@ -128,17 +128,6 @@ static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds, ...@@ -128,17 +128,6 @@ static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf); ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
} }
static inline void ath9k_hw_procmibevent(struct ath_hw *ah)
{
ath9k_hw_ops(ah)->ani_proc_mib_event(ah);
}
static inline void ath9k_hw_ani_monitor(struct ath_hw *ah,
struct ath9k_channel *chan)
{
ath9k_hw_ops(ah)->ani_monitor(ah, chan);
}
/* Private hardware call ops */ /* Private hardware call ops */
/* PHY ops */ /* PHY ops */
...@@ -276,15 +265,4 @@ static inline void ath9k_hw_setup_calibration(struct ath_hw *ah, ...@@ -276,15 +265,4 @@ static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal); ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
} }
static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
enum ath9k_cal_types calType)
{
return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
}
static inline void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
{
ath9k_hw_private_ops(ah)->ani_reset(ah, is_scanning);
}
#endif /* ATH9K_HW_OPS_H */ #endif /* ATH9K_HW_OPS_H */
...@@ -299,7 +299,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah) ...@@ -299,7 +299,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
/* This should work for all families including legacy */ /* This should work for all families including legacy */
...@@ -371,10 +370,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah) ...@@ -371,10 +370,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
ah->config.pcie_clock_req = 0; ah->config.pcie_clock_req = 0;
ah->config.pcie_waen = 0; ah->config.pcie_waen = 0;
ah->config.analog_shiftreg = 1; ah->config.analog_shiftreg = 1;
ah->config.ofdm_trig_low = 200;
ah->config.ofdm_trig_high = 500;
ah->config.cck_trig_high = 200;
ah->config.cck_trig_low = 100;
ah->config.enable_ani = true; ah->config.enable_ani = true;
for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
...@@ -676,7 +671,6 @@ static void ath9k_hw_init_qos(struct ath_hw *ah) ...@@ -676,7 +671,6 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
static void ath9k_hw_init_pll(struct ath_hw *ah, static void ath9k_hw_init_pll(struct ath_hw *ah,
...@@ -741,7 +735,6 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, ...@@ -741,7 +735,6 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (AR_SREV_9300_20_OR_LATER(ah)) { if (AR_SREV_9300_20_OR_LATER(ah)) {
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
...@@ -885,7 +878,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah) ...@@ -885,7 +878,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
/* /*
* Restore TX Trigger Level to its pre-reset value. * Restore TX Trigger Level to its pre-reset value.
...@@ -933,7 +925,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah) ...@@ -933,7 +925,6 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (AR_SREV_9300_20_OR_LATER(ah)) if (AR_SREV_9300_20_OR_LATER(ah))
ath9k_hw_reset_txstatus_ring(ah); ath9k_hw_reset_txstatus_ring(ah);
...@@ -1031,7 +1022,6 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) ...@@ -1031,7 +1022,6 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
REG_WRITE(ah, AR_RTC_RC, rst_flags); REG_WRITE(ah, AR_RTC_RC, rst_flags);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
udelay(50); udelay(50);
...@@ -1070,7 +1060,6 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) ...@@ -1070,7 +1060,6 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
udelay(2); udelay(2);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (!AR_SREV_9300_20_OR_LATER(ah)) if (!AR_SREV_9300_20_OR_LATER(ah))
udelay(2); udelay(2);
...@@ -1239,7 +1228,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -1239,7 +1228,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
return -EIO; return -EIO;
if (curchan && !ah->chip_fullsleep && ah->caldata) if (curchan && !ah->chip_fullsleep)
ath9k_hw_getnf(ah, curchan); ath9k_hw_getnf(ah, curchan);
ah->caldata = caldata; ah->caldata = caldata;
...@@ -1374,7 +1363,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -1374,7 +1363,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
r = ath9k_hw_rf_set_freq(ah, chan); r = ath9k_hw_rf_set_freq(ah, chan);
if (r) if (r)
...@@ -1386,7 +1374,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -1386,7 +1374,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
ah->intr_txqs = 0; ah->intr_txqs = 0;
for (i = 0; i < ah->caps.total_queues; i++) for (i = 0; i < ah->caps.total_queues; i++)
...@@ -1434,7 +1421,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -1434,7 +1421,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
/* /*
* For big endian systems turn on swapping for descriptors * For big endian systems turn on swapping for descriptors
...@@ -1684,7 +1670,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) ...@@ -1684,7 +1670,6 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
beacon_period &= ~ATH9K_BEACON_ENA; beacon_period &= ~ATH9K_BEACON_ENA;
if (beacon_period & ATH9K_BEACON_RESET_TSF) { if (beacon_period & ATH9K_BEACON_RESET_TSF) {
...@@ -1712,7 +1697,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, ...@@ -1712,7 +1697,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
REG_RMW_FIELD(ah, AR_RSSI_THR, REG_RMW_FIELD(ah, AR_RSSI_THR,
AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
...@@ -1758,7 +1742,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, ...@@ -1758,7 +1742,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
REG_SET_BIT(ah, AR_TIMER_MODE, REG_SET_BIT(ah, AR_TIMER_MODE,
AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
...@@ -2176,7 +2159,6 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) ...@@ -2176,7 +2159,6 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
EXPORT_SYMBOL(ath9k_hw_setrxfilter); EXPORT_SYMBOL(ath9k_hw_setrxfilter);
......
...@@ -70,19 +70,13 @@ ...@@ -70,19 +70,13 @@
#define ENABLE_REGWRITE_BUFFER(_ah) \ #define ENABLE_REGWRITE_BUFFER(_ah) \
do { \ do { \
if (AR_SREV_9271(_ah)) \ if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \ ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
} while (0) } while (0)
#define DISABLE_REGWRITE_BUFFER(_ah) \
do { \
if (AR_SREV_9271(_ah)) \
ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
} while (0)
#define REGWRITE_BUFFER_FLUSH(_ah) \ #define REGWRITE_BUFFER_FLUSH(_ah) \
do { \ do { \
if (AR_SREV_9271(_ah)) \ if (ath9k_hw_common(_ah)->ops->write_flush) \
ath9k_hw_common(_ah)->ops->write_flush((_ah)); \ ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
} while (0) } while (0)
...@@ -342,7 +336,6 @@ struct ath9k_hw_cal_data { ...@@ -342,7 +336,6 @@ struct ath9k_hw_cal_data {
int32_t CalValid; int32_t CalValid;
int8_t iCoff; int8_t iCoff;
int8_t qCoff; int8_t qCoff;
int16_t rawNoiseFloor;
bool paprd_done; bool paprd_done;
bool nfcal_pending; bool nfcal_pending;
bool nfcal_interference; bool nfcal_interference;
...@@ -353,9 +346,11 @@ struct ath9k_hw_cal_data { ...@@ -353,9 +346,11 @@ struct ath9k_hw_cal_data {
struct ath9k_channel { struct ath9k_channel {
struct ieee80211_channel *chan; struct ieee80211_channel *chan;
struct ar5416AniState ani;
u16 channel; u16 channel;
u32 channelFlags; u32 channelFlags;
u32 chanmode; u32 chanmode;
s16 noisefloor;
}; };
#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
...@@ -514,14 +509,6 @@ struct ath_hw_antcomb_conf { ...@@ -514,14 +509,6 @@ struct ath_hw_antcomb_conf {
* @setup_calibration: set up calibration * @setup_calibration: set up calibration
* @iscal_supported: used to query if a type of calibration is supported * @iscal_supported: used to query if a type of calibration is supported
* *
* @ani_reset: reset ANI parameters to default values
* @ani_lower_immunity: lower the noise immunity level. The level controls
* the power-based packet detection on hardware. If a power jump is
* detected the adapter takes it as an indication that a packet has
* arrived. The level ranges from 0-5. Each level corresponds to a
* few dB more of noise immunity. If you have a strong time-varying
* interference that is causing false detections (OFDM timing errors or
* CCK timing errors) the level can be increased.
* @ani_cache_ini_regs: cache the values for ANI from the initial * @ani_cache_ini_regs: cache the values for ANI from the initial
* register settings through the register initialization. * register settings through the register initialization.
*/ */
...@@ -535,8 +522,6 @@ struct ath_hw_private_ops { ...@@ -535,8 +522,6 @@ struct ath_hw_private_ops {
bool (*macversion_supported)(u32 macversion); bool (*macversion_supported)(u32 macversion);
void (*setup_calibration)(struct ath_hw *ah, void (*setup_calibration)(struct ath_hw *ah,
struct ath9k_cal_list *currCal); struct ath9k_cal_list *currCal);
bool (*iscal_supported)(struct ath_hw *ah,
enum ath9k_cal_types calType);
/* PHY ops */ /* PHY ops */
int (*rf_set_freq)(struct ath_hw *ah, int (*rf_set_freq)(struct ath_hw *ah,
...@@ -568,8 +553,6 @@ struct ath_hw_private_ops { ...@@ -568,8 +553,6 @@ struct ath_hw_private_ops {
void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
/* ANI */ /* ANI */
void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
void (*ani_lower_immunity)(struct ath_hw *ah);
void (*ani_cache_ini_regs)(struct ath_hw *ah); void (*ani_cache_ini_regs)(struct ath_hw *ah);
}; };
...@@ -581,11 +564,6 @@ struct ath_hw_private_ops { ...@@ -581,11 +564,6 @@ struct ath_hw_private_ops {
* *
* @config_pci_powersave: * @config_pci_powersave:
* @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
*
* @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
* thresholds being reached or having overflowed.
* @ani_monitor: called periodically by the core driver to collect
* MIB stats and adjust ANI if specific thresholds have been reached.
*/ */
struct ath_hw_ops { struct ath_hw_ops {
void (*config_pci_powersave)(struct ath_hw *ah, void (*config_pci_powersave)(struct ath_hw *ah,
...@@ -626,9 +604,6 @@ struct ath_hw_ops { ...@@ -626,9 +604,6 @@ struct ath_hw_ops {
u32 burstDuration); u32 burstDuration);
void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds, void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
u32 vmf); u32 vmf);
void (*ani_proc_mib_event)(struct ath_hw *ah);
void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
}; };
struct ath_nf_limits { struct ath_nf_limits {
...@@ -689,10 +664,9 @@ struct ath_hw { ...@@ -689,10 +664,9 @@ struct ath_hw {
u32 atim_window; u32 atim_window;
/* Calibration */ /* Calibration */
enum ath9k_cal_types supp_cals; u32 supp_cals;
struct ath9k_cal_list iq_caldata; struct ath9k_cal_list iq_caldata;
struct ath9k_cal_list adcgain_caldata; struct ath9k_cal_list adcgain_caldata;
struct ath9k_cal_list adcdc_calinitdata;
struct ath9k_cal_list adcdc_caldata; struct ath9k_cal_list adcdc_caldata;
struct ath9k_cal_list tempCompCalData; struct ath9k_cal_list tempCompCalData;
struct ath9k_cal_list *cal_list; struct ath9k_cal_list *cal_list;
...@@ -761,13 +735,13 @@ struct ath_hw { ...@@ -761,13 +735,13 @@ struct ath_hw {
/* ANI */ /* ANI */
u32 proc_phyerr; u32 proc_phyerr;
u32 aniperiod; u32 aniperiod;
struct ar5416AniState *curani;
struct ar5416AniState ani[255];
int totalSizeDesired[5]; int totalSizeDesired[5];
int coarse_high[5]; int coarse_high[5];
int coarse_low[5]; int coarse_low[5];
int firpwr[5]; int firpwr[5];
enum ath9k_ani_cmd ani_function; enum ath9k_ani_cmd ani_function;
struct ath_cycle_counters cc, cc_delta;
int32_t listen_time;
/* Bluetooth coexistance */ /* Bluetooth coexistance */
struct ath_btcoex_hw btcoex_hw; struct ath_btcoex_hw btcoex_hw;
...@@ -988,8 +962,9 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); ...@@ -988,8 +962,9 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
* older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
*/ */
extern int modparam_force_new_ani; extern int modparam_force_new_ani;
void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah); void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah); void ath9k_hw_proc_mib_event(struct ath_hw *ah);
void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
#define ATH_PCIE_CAP_LINK_CTRL 0x70 #define ATH_PCIE_CAP_LINK_CTRL 0x70
#define ATH_PCIE_CAP_LINK_L0S 1 #define ATH_PCIE_CAP_LINK_L0S 1
......
...@@ -56,7 +56,7 @@ MODULE_PARM_DESC(blink, "Enable LED blink on activity"); ...@@ -56,7 +56,7 @@ MODULE_PARM_DESC(blink, "Enable LED blink on activity");
* on 5 MHz steps, we support the channels which we know * on 5 MHz steps, we support the channels which we know
* we have calibration data for all cards though to make * we have calibration data for all cards though to make
* this static */ * this static */
static struct ieee80211_channel ath9k_2ghz_chantable[] = { static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
CHAN2G(2412, 0), /* Channel 1 */ CHAN2G(2412, 0), /* Channel 1 */
CHAN2G(2417, 1), /* Channel 2 */ CHAN2G(2417, 1), /* Channel 2 */
CHAN2G(2422, 2), /* Channel 3 */ CHAN2G(2422, 2), /* Channel 3 */
...@@ -77,7 +77,7 @@ static struct ieee80211_channel ath9k_2ghz_chantable[] = { ...@@ -77,7 +77,7 @@ static struct ieee80211_channel ath9k_2ghz_chantable[] = {
* on 5 MHz steps, we support the channels which we know * on 5 MHz steps, we support the channels which we know
* we have calibration data for all cards though to make * we have calibration data for all cards though to make
* this static */ * this static */
static struct ieee80211_channel ath9k_5ghz_chantable[] = { static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
/* _We_ call this UNII 1 */ /* _We_ call this UNII 1 */
CHAN5G(5180, 14), /* Channel 36 */ CHAN5G(5180, 14), /* Channel 36 */
CHAN5G(5200, 15), /* Channel 40 */ CHAN5G(5200, 15), /* Channel 40 */
...@@ -477,10 +477,17 @@ static int ath9k_init_queues(struct ath_softc *sc) ...@@ -477,10 +477,17 @@ static int ath9k_init_queues(struct ath_softc *sc)
return -EIO; return -EIO;
} }
static void ath9k_init_channels_rates(struct ath_softc *sc) static int ath9k_init_channels_rates(struct ath_softc *sc)
{ {
void *channels;
if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) { if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable; channels = kmemdup(ath9k_2ghz_chantable,
sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
if (!channels)
return -ENOMEM;
sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
sc->sbands[IEEE80211_BAND_2GHZ].n_channels = sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
ARRAY_SIZE(ath9k_2ghz_chantable); ARRAY_SIZE(ath9k_2ghz_chantable);
...@@ -490,7 +497,15 @@ static void ath9k_init_channels_rates(struct ath_softc *sc) ...@@ -490,7 +497,15 @@ static void ath9k_init_channels_rates(struct ath_softc *sc)
} }
if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; channels = kmemdup(ath9k_5ghz_chantable,
sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
if (!channels) {
if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
return -ENOMEM;
}
sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
sc->sbands[IEEE80211_BAND_5GHZ].n_channels = sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
ARRAY_SIZE(ath9k_5ghz_chantable); ARRAY_SIZE(ath9k_5ghz_chantable);
...@@ -499,6 +514,7 @@ static void ath9k_init_channels_rates(struct ath_softc *sc) ...@@ -499,6 +514,7 @@ static void ath9k_init_channels_rates(struct ath_softc *sc)
sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
ARRAY_SIZE(ath9k_legacy_rates) - 4; ARRAY_SIZE(ath9k_legacy_rates) - 4;
} }
return 0;
} }
static void ath9k_init_misc(struct ath_softc *sc) static void ath9k_init_misc(struct ath_softc *sc)
...@@ -506,7 +522,6 @@ static void ath9k_init_misc(struct ath_softc *sc) ...@@ -506,7 +522,6 @@ static void ath9k_init_misc(struct ath_softc *sc)
struct ath_common *common = ath9k_hw_common(sc->sc_ah); struct ath_common *common = ath9k_hw_common(sc->sc_ah);
int i = 0; int i = 0;
common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
sc->config.txpowlimit = ATH_TXPOWER_MAX; sc->config.txpowlimit = ATH_TXPOWER_MAX;
...@@ -595,8 +610,11 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, ...@@ -595,8 +610,11 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
if (ret) if (ret)
goto err_btcoex; goto err_btcoex;
ret = ath9k_init_channels_rates(sc);
if (ret)
goto err_btcoex;
ath9k_init_crypto(sc); ath9k_init_crypto(sc);
ath9k_init_channels_rates(sc);
ath9k_init_misc(sc); ath9k_init_misc(sc);
return 0; return 0;
...@@ -639,6 +657,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) ...@@ -639,6 +657,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
hw->wiphy->interface_modes = hw->wiphy->interface_modes =
BIT(NL80211_IFTYPE_AP) | BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_WDS) |
BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_ADHOC) |
BIT(NL80211_IFTYPE_MESH_POINT); BIT(NL80211_IFTYPE_MESH_POINT);
...@@ -756,6 +775,12 @@ static void ath9k_deinit_softc(struct ath_softc *sc) ...@@ -756,6 +775,12 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
{ {
int i = 0; int i = 0;
if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
if ((sc->btcoex.no_stomp_timer) && if ((sc->btcoex.no_stomp_timer) &&
sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
......
...@@ -40,7 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, ...@@ -40,7 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
} }
u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
...@@ -492,8 +491,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -492,8 +491,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
REG_WRITE(ah, AR_DMISC(q), REG_WRITE(ah, AR_DMISC(q),
AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
REGWRITE_BUFFER_FLUSH(ah);
if (qi->tqi_cbrPeriod) { if (qi->tqi_cbrPeriod) {
REG_WRITE(ah, AR_QCBRCFG(q), REG_WRITE(ah, AR_QCBRCFG(q),
SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
...@@ -509,8 +506,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -509,8 +506,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
AR_Q_RDYTIMECFG_EN); AR_Q_RDYTIMECFG_EN);
} }
REGWRITE_BUFFER_FLUSH(ah);
REG_WRITE(ah, AR_DCHNTIME(q), REG_WRITE(ah, AR_DCHNTIME(q),
SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
...@@ -530,7 +525,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -530,7 +525,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
} }
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
REG_WRITE(ah, AR_DMISC(q), REG_WRITE(ah, AR_DMISC(q),
...@@ -553,7 +547,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -553,7 +547,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
| AR_D_MISC_POST_FR_BKOFF_DIS); | AR_D_MISC_POST_FR_BKOFF_DIS);
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
/* /*
* cwmin and cwmax should be 0 for beacon queue * cwmin and cwmax should be 0 for beacon queue
...@@ -585,7 +578,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) ...@@ -585,7 +578,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
REGWRITE_BUFFER_FLUSH(ah); REGWRITE_BUFFER_FLUSH(ah);
DISABLE_REGWRITE_BUFFER(ah);
break; break;
case ATH9K_TX_QUEUE_PSPOLL: case ATH9K_TX_QUEUE_PSPOLL:
......
...@@ -459,16 +459,6 @@ void ath_ani_calibrate(unsigned long data) ...@@ -459,16 +459,6 @@ void ath_ani_calibrate(unsigned long data)
ah->curchan, ah->curchan,
common->rx_chainmask, common->rx_chainmask,
longcal); longcal);
if (longcal)
common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
ah->curchan);
ath_print(common, ATH_DBG_ANI,
" calibrate chan %u/%x nf: %d\n",
ah->curchan->channel,
ah->curchan->channelFlags,
common->ani.noise_floor);
} }
} }
...@@ -723,7 +713,7 @@ irqreturn_t ath_isr(int irq, void *dev) ...@@ -723,7 +713,7 @@ irqreturn_t ath_isr(int irq, void *dev)
* it will clear whatever condition caused * it will clear whatever condition caused
* the interrupt. * the interrupt.
*/ */
ath9k_hw_procmibevent(ah); ath9k_hw_proc_mib_event(ah);
ath9k_hw_set_interrupts(ah, ah->imask); ath9k_hw_set_interrupts(ah, ah->imask);
} }
...@@ -1384,6 +1374,9 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, ...@@ -1384,6 +1374,9 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_STATION:
ic_opmode = NL80211_IFTYPE_STATION; ic_opmode = NL80211_IFTYPE_STATION;
break; break;
case NL80211_IFTYPE_WDS:
ic_opmode = NL80211_IFTYPE_WDS;
break;
case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_ADHOC:
case NL80211_IFTYPE_AP: case NL80211_IFTYPE_AP:
case NL80211_IFTYPE_MESH_POINT: case NL80211_IFTYPE_MESH_POINT:
...@@ -1491,7 +1484,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, ...@@ -1491,7 +1484,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
mutex_unlock(&sc->mutex); mutex_unlock(&sc->mutex);
} }
void ath9k_enable_ps(struct ath_softc *sc) static void ath9k_enable_ps(struct ath_softc *sc)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
...@@ -1505,13 +1498,32 @@ void ath9k_enable_ps(struct ath_softc *sc) ...@@ -1505,13 +1498,32 @@ void ath9k_enable_ps(struct ath_softc *sc)
} }
} }
static void ath9k_disable_ps(struct ath_softc *sc)
{
struct ath_hw *ah = sc->sc_ah;
sc->ps_enabled = false;
ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
ath9k_hw_setrxabort(ah, 0);
sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
PS_WAIT_FOR_CAB |
PS_WAIT_FOR_PSPOLL_DATA |
PS_WAIT_FOR_TX_ACK);
if (ah->imask & ATH9K_INT_TIM_TIMER) {
ah->imask &= ~ATH9K_INT_TIM_TIMER;
ath9k_hw_set_interrupts(ah, ah->imask);
}
}
}
static int ath9k_config(struct ieee80211_hw *hw, u32 changed) static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
{ {
struct ath_wiphy *aphy = hw->priv; struct ath_wiphy *aphy = hw->priv;
struct ath_softc *sc = aphy->sc; struct ath_softc *sc = aphy->sc;
struct ath_common *common = ath9k_hw_common(sc->sc_ah); struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ieee80211_conf *conf = &hw->conf; struct ieee80211_conf *conf = &hw->conf;
struct ath_hw *ah = sc->sc_ah;
bool disable_radio; bool disable_radio;
mutex_lock(&sc->mutex); mutex_lock(&sc->mutex);
...@@ -1558,35 +1570,10 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) ...@@ -1558,35 +1570,10 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
if (changed & IEEE80211_CONF_CHANGE_PS) { if (changed & IEEE80211_CONF_CHANGE_PS) {
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&sc->sc_pm_lock, flags); spin_lock_irqsave(&sc->sc_pm_lock, flags);
if (conf->flags & IEEE80211_CONF_PS) { if (conf->flags & IEEE80211_CONF_PS)
sc->ps_flags |= PS_ENABLED; ath9k_enable_ps(sc);
/* else
* At this point we know hardware has received an ACK ath9k_disable_ps(sc);
* of a previously sent null data frame.
*/
if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
ath9k_enable_ps(sc);
}
} else {
sc->ps_enabled = false;
sc->ps_flags &= ~(PS_ENABLED |
PS_NULLFUNC_COMPLETED);
ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
if (!(ah->caps.hw_caps &
ATH9K_HW_CAP_AUTOSLEEP)) {
ath9k_hw_setrxabort(sc->sc_ah, 0);
sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
PS_WAIT_FOR_CAB |
PS_WAIT_FOR_PSPOLL_DATA |
PS_WAIT_FOR_TX_ACK);
if (ah->imask & ATH9K_INT_TIM_TIMER) {
ah->imask &= ~ATH9K_INT_TIM_TIMER;
ath9k_hw_set_interrupts(sc->sc_ah,
ah->imask);
}
}
}
spin_unlock_irqrestore(&sc->sc_pm_lock, flags); spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
} }
...@@ -2004,15 +1991,32 @@ static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, ...@@ -2004,15 +1991,32 @@ static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
struct ath_wiphy *aphy = hw->priv; struct ath_wiphy *aphy = hw->priv;
struct ath_softc *sc = aphy->sc; struct ath_softc *sc = aphy->sc;
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah); struct ieee80211_supported_band *sband;
struct ieee80211_conf *conf = &hw->conf; struct ath9k_channel *chan;
sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
if (sband && idx >= sband->n_channels) {
idx -= sband->n_channels;
sband = NULL;
}
if (!sband)
sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
if (idx != 0) if (!sband || idx >= sband->n_channels)
return -ENOENT; return -ENOENT;
survey->channel = conf->channel; survey->channel = &sband->channels[idx];
survey->filled = SURVEY_INFO_NOISE_DBM; chan = &ah->channels[survey->channel->hw_value];
survey->noise = common->ani.noise_floor; survey->filled = 0;
if (chan == ah->curchan)
survey->filled |= SURVEY_INFO_IN_USE;
if (chan->noisefloor) {
survey->filled |= SURVEY_INFO_NOISE_DBM;
survey->noise = chan->noisefloor;
}
return 0; return 0;
} }
......
...@@ -1648,13 +1648,6 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, ...@@ -1648,13 +1648,6 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
bf->bf_buf_addr = bf->bf_dmacontext; bf->bf_buf_addr = bf->bf_dmacontext;
/* tag if this is a nullfunc frame to enable PS when AP acks it */
if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
bf->bf_isnullfunc = true;
sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
} else
bf->bf_isnullfunc = false;
bf->bf_tx_aborted = false; bf->bf_tx_aborted = false;
return 0; return 0;
...@@ -2081,18 +2074,6 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) ...@@ -2081,18 +2074,6 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
break; break;
} }
/*
* We now know the nullfunc frame has been ACKed so we
* can disable RX.
*/
if (bf->bf_isnullfunc &&
(ts.ts_status & ATH9K_TX_ACKED)) {
if ((sc->ps_flags & PS_ENABLED))
ath9k_enable_ps(sc);
else
sc->ps_flags |= PS_NULLFUNC_COMPLETED;
}
/* /*
* Remove ath_buf's of the same transmit unit from txq, * Remove ath_buf's of the same transmit unit from txq,
* however leave the last descriptor back as the holding * however leave the last descriptor back as the holding
...@@ -2236,17 +2217,6 @@ void ath_tx_edma_tasklet(struct ath_softc *sc) ...@@ -2236,17 +2217,6 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
txok = !(txs.ts_status & ATH9K_TXERR_MASK); txok = !(txs.ts_status & ATH9K_TXERR_MASK);
/*
* Make sure null func frame is acked before configuring
* hw into ps mode.
*/
if (bf->bf_isnullfunc && txok) {
if ((sc->ps_flags & PS_ENABLED))
ath9k_enable_ps(sc);
else
sc->ps_flags |= PS_NULLFUNC_COMPLETED;
}
if (!bf_isampdu(bf)) { if (!bf_isampdu(bf)) {
if (txs.ts_status & ATH9K_TXERR_XRETRY) if (txs.ts_status & ATH9K_TXERR_XRETRY)
bf->bf_state.bf_type |= BUF_XRETRY; bf->bf_state.bf_type |= BUF_XRETRY;
......
...@@ -279,6 +279,7 @@ struct ar9170 { ...@@ -279,6 +279,7 @@ struct ar9170 {
unsigned int beacon_max_len; unsigned int beacon_max_len;
bool rx_stream; bool rx_stream;
bool tx_stream; bool tx_stream;
bool rx_filter;
unsigned int mem_blocks; unsigned int mem_blocks;
unsigned int mem_block_size; unsigned int mem_block_size;
unsigned int rx_size; unsigned int rx_size;
...@@ -314,6 +315,7 @@ struct ar9170 { ...@@ -314,6 +315,7 @@ struct ar9170 {
u64 cur_mc_hash; u64 cur_mc_hash;
u32 cur_filter; u32 cur_filter;
unsigned int filter_state; unsigned int filter_state;
unsigned int rx_filter_caps;
bool sniffer_enabled; bool sniffer_enabled;
/* MAC */ /* MAC */
......
...@@ -59,6 +59,16 @@ static inline int carl9170_flush_cab(struct ar9170 *ar, ...@@ -59,6 +59,16 @@ static inline int carl9170_flush_cab(struct ar9170 *ar,
return carl9170_bcn_ctrl(ar, vif_id, CARL9170_BCN_CTRL_DRAIN, 0, 0); return carl9170_bcn_ctrl(ar, vif_id, CARL9170_BCN_CTRL_DRAIN, 0, 0);
} }
static inline int carl9170_rx_filter(struct ar9170 *ar,
const unsigned int _rx_filter)
{
__le32 rx_filter = cpu_to_le32(_rx_filter);
return carl9170_exec_cmd(ar, CARL9170_CMD_RX_FILTER,
sizeof(rx_filter), (u8 *)&rx_filter,
0, NULL);
}
struct carl9170_cmd *carl9170_cmd_buf(struct ar9170 *ar, struct carl9170_cmd *carl9170_cmd_buf(struct ar9170 *ar,
const enum carl9170_cmd_oids cmd, const unsigned int len); const enum carl9170_cmd_oids cmd, const unsigned int len);
......
...@@ -257,6 +257,13 @@ static int carl9170_fw(struct ar9170 *ar, const __u8 *data, size_t len) ...@@ -257,6 +257,13 @@ static int carl9170_fw(struct ar9170 *ar, const __u8 *data, size_t len)
if (SUPP(CARL9170FW_USB_UP_STREAM)) if (SUPP(CARL9170FW_USB_UP_STREAM))
ar->fw.rx_stream = true; ar->fw.rx_stream = true;
if (SUPP(CARL9170FW_RX_FILTER)) {
ar->fw.rx_filter = true;
ar->rx_filter_caps = FIF_FCSFAIL | FIF_PLCPFAIL |
FIF_CONTROL | FIF_PSPOLL | FIF_OTHER_BSS |
FIF_PROMISC_IN_BSS;
}
ar->fw.vif_num = otus_desc->vif_num; ar->fw.vif_num = otus_desc->vif_num;
ar->fw.cmd_bufs = otus_desc->cmd_bufs; ar->fw.cmd_bufs = otus_desc->cmd_bufs;
ar->fw.address = le32_to_cpu(otus_desc->fw_address); ar->fw.address = le32_to_cpu(otus_desc->fw_address);
......
...@@ -53,6 +53,7 @@ enum carl9170_cmd_oids { ...@@ -53,6 +53,7 @@ enum carl9170_cmd_oids {
CARL9170_CMD_REBOOT = 0x04, CARL9170_CMD_REBOOT = 0x04,
CARL9170_CMD_BCN_CTRL = 0x05, CARL9170_CMD_BCN_CTRL = 0x05,
CARL9170_CMD_READ_TSF = 0x06, CARL9170_CMD_READ_TSF = 0x06,
CARL9170_CMD_RX_FILTER = 0x07,
/* CAM */ /* CAM */
CARL9170_CMD_EKEY = 0x10, CARL9170_CMD_EKEY = 0x10,
...@@ -153,6 +154,20 @@ struct carl9170_psm { ...@@ -153,6 +154,20 @@ struct carl9170_psm {
} __packed; } __packed;
#define CARL9170_PSM_SIZE 4 #define CARL9170_PSM_SIZE 4
struct carl9170_rx_filter_cmd {
__le32 rx_filter;
} __packed;
#define CARL9170_RX_FILTER_CMD_SIZE 4
#define CARL9170_RX_FILTER_BAD 0x01
#define CARL9170_RX_FILTER_OTHER_RA 0x02
#define CARL9170_RX_FILTER_DECRY_FAIL 0x04
#define CARL9170_RX_FILTER_CTL_OTHER 0x08
#define CARL9170_RX_FILTER_CTL_PSPOLL 0x10
#define CARL9170_RX_FILTER_CTL_BACKR 0x20
#define CARL9170_RX_FILTER_MGMT 0x40
#define CARL9170_RX_FILTER_DATA 0x80
struct carl9170_bcn_ctrl_cmd { struct carl9170_bcn_ctrl_cmd {
__le32 vif_id; __le32 vif_id;
__le32 mode; __le32 mode;
...@@ -188,6 +203,7 @@ struct carl9170_cmd { ...@@ -188,6 +203,7 @@ struct carl9170_cmd {
struct carl9170_rf_init rf_init; struct carl9170_rf_init rf_init;
struct carl9170_psm psm; struct carl9170_psm psm;
struct carl9170_bcn_ctrl_cmd bcn_ctrl; struct carl9170_bcn_ctrl_cmd bcn_ctrl;
struct carl9170_rx_filter_cmd rx_filter;
u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN]; u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
} __packed; } __packed;
} __packed; } __packed;
......
...@@ -66,6 +66,9 @@ enum carl9170fw_feature_list { ...@@ -66,6 +66,9 @@ enum carl9170fw_feature_list {
/* Firmware PSM support | CARL9170_CMD_PSM */ /* Firmware PSM support | CARL9170_CMD_PSM */
CARL9170FW_PSM, CARL9170FW_PSM,
/* Firmware RX filter | CARL9170_CMD_RX_FILTER */
CARL9170FW_RX_FILTER,
/* KEEP LAST */ /* KEEP LAST */
__CARL9170FW_FEATURE_NUM __CARL9170FW_FEATURE_NUM
}; };
...@@ -142,7 +145,7 @@ struct carl9170fw_fix_desc { ...@@ -142,7 +145,7 @@ struct carl9170fw_fix_desc {
(sizeof(struct carl9170fw_fix_desc)) (sizeof(struct carl9170fw_fix_desc))
#define CARL9170FW_DBG_DESC_MIN_VER 1 #define CARL9170FW_DBG_DESC_MIN_VER 1
#define CARL9170FW_DBG_DESC_CUR_VER 2 #define CARL9170FW_DBG_DESC_CUR_VER 3
struct carl9170fw_dbg_desc { struct carl9170fw_dbg_desc {
struct carl9170fw_desc_head head; struct carl9170fw_desc_head head;
...@@ -150,6 +153,7 @@ struct carl9170fw_dbg_desc { ...@@ -150,6 +153,7 @@ struct carl9170fw_dbg_desc {
__le32 counter_addr; __le32 counter_addr;
__le32 rx_total_addr; __le32 rx_total_addr;
__le32 rx_overrun_addr; __le32 rx_overrun_addr;
__le32 rx_filter;
/* Put your debugging definitions here */ /* Put your debugging definitions here */
} __packed; } __packed;
......
...@@ -731,6 +731,9 @@ struct ar9170_stream { ...@@ -731,6 +731,9 @@ struct ar9170_stream {
#define SET_VAL(reg, value, newvalue) \ #define SET_VAL(reg, value, newvalue) \
(value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg)) (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))
#define SET_CONSTVAL(reg, newvalue) \
(((newvalue) << reg##_S) & reg)
#define MOD_VAL(reg, value, newvalue) \ #define MOD_VAL(reg, value, newvalue) \
(((value) & ~reg) | (((newvalue) << reg##_S) & reg)) (((value) & ~reg) | (((newvalue) << reg##_S) & reg))
#endif /* __CARL9170_SHARED_HW_H */ #endif /* __CARL9170_SHARED_HW_H */
...@@ -380,6 +380,13 @@ static int carl9170_op_start(struct ieee80211_hw *hw) ...@@ -380,6 +380,13 @@ static int carl9170_op_start(struct ieee80211_hw *hw)
if (err) if (err)
goto out; goto out;
if (ar->fw.rx_filter) {
err = carl9170_rx_filter(ar, CARL9170_RX_FILTER_OTHER_RA |
CARL9170_RX_FILTER_CTL_OTHER | CARL9170_RX_FILTER_BAD);
if (err)
goto out;
}
err = carl9170_write_reg(ar, AR9170_MAC_REG_DMA_TRIGGER, err = carl9170_write_reg(ar, AR9170_MAC_REG_DMA_TRIGGER,
AR9170_DMA_TRIGGER_RXQ); AR9170_DMA_TRIGGER_RXQ);
if (err) if (err)
...@@ -840,8 +847,7 @@ static void carl9170_op_configure_filter(struct ieee80211_hw *hw, ...@@ -840,8 +847,7 @@ static void carl9170_op_configure_filter(struct ieee80211_hw *hw,
struct ar9170 *ar = hw->priv; struct ar9170 *ar = hw->priv;
/* mask supported flags */ /* mask supported flags */
*new_flags &= FIF_ALLMULTI | FIF_FCSFAIL | FIF_PLCPFAIL | *new_flags &= FIF_ALLMULTI | ar->rx_filter_caps;
FIF_OTHER_BSS | FIF_PROMISC_IN_BSS;
if (!IS_ACCEPTING_CMD(ar)) if (!IS_ACCEPTING_CMD(ar))
return; return;
...@@ -867,6 +873,26 @@ static void carl9170_op_configure_filter(struct ieee80211_hw *hw, ...@@ -867,6 +873,26 @@ static void carl9170_op_configure_filter(struct ieee80211_hw *hw,
WARN_ON(carl9170_set_operating_mode(ar)); WARN_ON(carl9170_set_operating_mode(ar));
} }
if (ar->fw.rx_filter && changed_flags & ar->rx_filter_caps) {
u32 rx_filter = 0;
if (!(*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)))
rx_filter |= CARL9170_RX_FILTER_BAD;
if (!(*new_flags & FIF_CONTROL))
rx_filter |= CARL9170_RX_FILTER_CTL_OTHER;
if (!(*new_flags & FIF_PSPOLL))
rx_filter |= CARL9170_RX_FILTER_CTL_PSPOLL;
if (!(*new_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))) {
rx_filter |= CARL9170_RX_FILTER_OTHER_RA;
rx_filter |= CARL9170_RX_FILTER_DECRY_FAIL;
}
WARN_ON(carl9170_rx_filter(ar, rx_filter));
}
mutex_unlock(&ar->mutex); mutex_unlock(&ar->mutex);
} }
......
...@@ -423,8 +423,8 @@ ...@@ -423,8 +423,8 @@
#define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
#define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 #define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c)
#define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c) #define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c)
#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c)
#define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000 #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000
#define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 #define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
#define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00 #define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00
...@@ -561,7 +561,4 @@ ...@@ -561,7 +561,4 @@
#define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000 #define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000
#define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23 #define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23
#define REDUCE_CHAIN_0 0x00000050
#define REDUCE_CHAIN_1 0x00000051
#endif /* __CARL9170_SHARED_PHY_H */ #endif /* __CARL9170_SHARED_PHY_H */
#ifndef __CARL9170_SHARED_VERSION_H #ifndef __CARL9170_SHARED_VERSION_H
#define __CARL9170_SHARED_VERSION_H #define __CARL9170_SHARED_VERSION_H
#define CARL9170FW_VERSION_YEAR 10 #define CARL9170FW_VERSION_YEAR 10
#define CARL9170FW_VERSION_MONTH 8 #define CARL9170FW_VERSION_MONTH 9
#define CARL9170FW_VERSION_DAY 30 #define CARL9170FW_VERSION_DAY 28
#define CARL9170FW_VERSION_GIT "1.8.8.1" #define CARL9170FW_VERSION_GIT "1.8.8.3"
#endif /* __CARL9170_SHARED_VERSION_H */ #endif /* __CARL9170_SHARED_VERSION_H */
...@@ -186,7 +186,8 @@ enum { ...@@ -186,7 +186,8 @@ enum {
#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */ #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */ #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */ #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */
#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */
#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
/* TSSI information */ /* TSSI information */
#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */ #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
......
...@@ -294,8 +294,10 @@ int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel) ...@@ -294,8 +294,10 @@ int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
*/ */
channelcookie = new_channel; channelcookie = new_channel;
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
channelcookie |= 0x100; channelcookie |= B43_SHM_SH_CHAN_5GHZ;
//FIXME set 40Mhz flag if required /* FIXME: set 40Mhz flag if required */
if (0)
channelcookie |= B43_SHM_SH_CHAN_40MHZ;
savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN); savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie); b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
......
...@@ -73,7 +73,6 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, ...@@ -73,7 +73,6 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
u16 value, u8 core, bool off); u16 value, u8 core, bool off);
static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
u16 value, u8 core); u16 value, u8 core);
static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel);
static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec) static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec)
{ {
...@@ -223,7 +222,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev) ...@@ -223,7 +222,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
if (i) if (i)
b43err(dev->wl, "radio post init timeout\n"); b43err(dev->wl, "radio post init timeout\n");
b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
nphy_channel_switch(dev, dev->phy.channel); b43_switch_channel(dev, dev->phy.channel);
b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
...@@ -3351,12 +3350,6 @@ static void b43_nphy_chanspec_setup(struct b43_wldev *dev, ...@@ -3351,12 +3350,6 @@ static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
b43_chantab_phy_upload(dev, e); b43_chantab_phy_upload(dev, e);
tmp = chanspec.channel;
if (chanspec.b_freq == 1)
tmp |= 0x0100;
if (chanspec.b_width == 3)
tmp |= 0x0200;
b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp);
if (nphy->radio_chanspec.channel == 14) { if (nphy->radio_chanspec.channel == 14) {
b43_nphy_classifier(dev, 2, 0); b43_nphy_classifier(dev, 2, 0);
...@@ -3438,18 +3431,6 @@ static int b43_nphy_set_chanspec(struct b43_wldev *dev, ...@@ -3438,18 +3431,6 @@ static int b43_nphy_set_chanspec(struct b43_wldev *dev,
return 0; return 0;
} }
/* Tune the hardware to a new channel */
static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
{
struct b43_phy_n *nphy = dev->phy.n;
struct b43_chanspec chanspec;
chanspec = nphy->radio_chanspec;
chanspec.channel = channel;
return b43_nphy_set_chanspec(dev, chanspec);
}
static int b43_nphy_op_allocate(struct b43_wldev *dev) static int b43_nphy_op_allocate(struct b43_wldev *dev)
{ {
struct b43_phy_n *nphy; struct b43_phy_n *nphy;
...@@ -3570,7 +3551,7 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, ...@@ -3570,7 +3551,7 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
} else { } else {
if (dev->phy.rev >= 3) { if (dev->phy.rev >= 3) {
b43_radio_init2056(dev); b43_radio_init2056(dev);
b43_nphy_set_chanspec(dev, nphy->radio_chanspec); b43_switch_channel(dev, dev->phy.channel);
} else { } else {
b43_radio_init2055(dev); b43_radio_init2055(dev);
} }
...@@ -3586,6 +3567,9 @@ static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) ...@@ -3586,6 +3567,9 @@ static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
static int b43_nphy_op_switch_channel(struct b43_wldev *dev, static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
unsigned int new_channel) unsigned int new_channel)
{ {
struct b43_phy_n *nphy = dev->phy.n;
struct b43_chanspec chanspec;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
if ((new_channel < 1) || (new_channel > 14)) if ((new_channel < 1) || (new_channel > 14))
return -EINVAL; return -EINVAL;
...@@ -3594,7 +3578,10 @@ static int b43_nphy_op_switch_channel(struct b43_wldev *dev, ...@@ -3594,7 +3578,10 @@ static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
return -EINVAL; return -EINVAL;
} }
return nphy_channel_switch(dev, new_channel); chanspec = nphy->radio_chanspec;
chanspec.channel = new_channel;
return b43_nphy_set_chanspec(dev, chanspec);
} }
static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
......
...@@ -11470,6 +11470,10 @@ static int ipw_net_init(struct net_device *dev) ...@@ -11470,6 +11470,10 @@ static int ipw_net_init(struct net_device *dev)
bg_band->channels = kcalloc(geo->bg_channels, bg_band->channels = kcalloc(geo->bg_channels,
sizeof(struct ieee80211_channel), sizeof(struct ieee80211_channel),
GFP_KERNEL); GFP_KERNEL);
if (!bg_band->channels) {
rc = -ENOMEM;
goto out;
}
/* translate geo->bg to bg_band.channels */ /* translate geo->bg to bg_band.channels */
for (i = 0; i < geo->bg_channels; i++) { for (i = 0; i < geo->bg_channels; i++) {
bg_band->channels[i].band = IEEE80211_BAND_2GHZ; bg_band->channels[i].band = IEEE80211_BAND_2GHZ;
...@@ -11505,6 +11509,10 @@ static int ipw_net_init(struct net_device *dev) ...@@ -11505,6 +11509,10 @@ static int ipw_net_init(struct net_device *dev)
a_band->channels = kcalloc(geo->a_channels, a_band->channels = kcalloc(geo->a_channels,
sizeof(struct ieee80211_channel), sizeof(struct ieee80211_channel),
GFP_KERNEL); GFP_KERNEL);
if (!a_band->channels) {
rc = -ENOMEM;
goto out;
}
/* translate geo->bg to a_band.channels */ /* translate geo->bg to a_band.channels */
for (i = 0; i < geo->a_channels; i++) { for (i = 0; i < geo->a_channels; i++) {
a_band->channels[i].band = IEEE80211_BAND_2GHZ; a_band->channels[i].band = IEEE80211_BAND_2GHZ;
......
...@@ -50,14 +50,20 @@ ...@@ -50,14 +50,20 @@
/* Highest firmware API version supported */ /* Highest firmware API version supported */
#define IWL1000_UCODE_API_MAX 3 #define IWL1000_UCODE_API_MAX 3
#define IWL100_UCODE_API_MAX 5
/* Lowest firmware API version supported */ /* Lowest firmware API version supported */
#define IWL1000_UCODE_API_MIN 1 #define IWL1000_UCODE_API_MIN 1
#define IWL100_UCODE_API_MIN 5
#define IWL1000_FW_PRE "iwlwifi-1000-" #define IWL1000_FW_PRE "iwlwifi-1000-"
#define _IWL1000_MODULE_FIRMWARE(api) IWL1000_FW_PRE #api ".ucode" #define _IWL1000_MODULE_FIRMWARE(api) IWL1000_FW_PRE #api ".ucode"
#define IWL1000_MODULE_FIRMWARE(api) _IWL1000_MODULE_FIRMWARE(api) #define IWL1000_MODULE_FIRMWARE(api) _IWL1000_MODULE_FIRMWARE(api)
#define IWL100_FW_PRE "iwlwifi-100-"
#define _IWL100_MODULE_FIRMWARE(api) IWL100_FW_PRE #api ".ucode"
#define IWL100_MODULE_FIRMWARE(api) _IWL100_MODULE_FIRMWARE(api)
/* /*
* For 1000, use advance thermal throttling critical temperature threshold, * For 1000, use advance thermal throttling critical temperature threshold,
...@@ -120,13 +126,13 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv) ...@@ -120,13 +126,13 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
{ {
if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES) priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES)
priv->cfg->num_of_queues = priv->cfg->base_params->num_of_queues =
priv->cfg->mod_params->num_of_queues; priv->cfg->mod_params->num_of_queues;
priv->hw_params.max_txq_num = priv->cfg->num_of_queues; priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
priv->hw_params.scd_bc_tbls_size = priv->hw_params.scd_bc_tbls_size =
priv->cfg->num_of_queues * priv->cfg->base_params->num_of_queues *
sizeof(struct iwlagn_scd_bc_tbl); sizeof(struct iwlagn_scd_bc_tbl);
priv->hw_params.tfd_size = sizeof(struct iwl_tfd); priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
priv->hw_params.max_stations = IWLAGN_STATION_COUNT; priv->hw_params.max_stations = IWLAGN_STATION_COUNT;
...@@ -244,29 +250,16 @@ static const struct iwl_ops iwl1000_ops = { ...@@ -244,29 +250,16 @@ static const struct iwl_ops iwl1000_ops = {
.led = &iwlagn_led_ops, .led = &iwlagn_led_ops,
}; };
struct iwl_cfg iwl1000_bgn_cfg = { static struct iwl_base_params iwl1000_base_params = {
.name = "Intel(R) Centrino(R) Wireless-N 1000 BGN",
.fw_name_pre = IWL1000_FW_PRE,
.ucode_api_max = IWL1000_UCODE_API_MAX,
.ucode_api_min = IWL1000_UCODE_API_MIN,
.sku = IWL_SKU_G|IWL_SKU_N,
.ops = &iwl1000_ops,
.eeprom_size = OTP_LOW_IMAGE_SIZE,
.eeprom_ver = EEPROM_1000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .num_of_queues = IWLAGN_NUM_QUEUES,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES, .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .eeprom_size = OTP_LOW_IMAGE_SIZE,
.valid_tx_ant = ANT_A,
.valid_rx_ant = ANT_AB,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true, .set_l0s = true,
.use_bsm = false, .use_bsm = false,
.max_ll_items = OTP_MAX_LL_ITEMS_1000, .max_ll_items = OTP_MAX_LL_ITEMS_1000,
.shadow_ram_support = false, .shadow_ram_support = false,
.ht_greenfield_support = true,
.led_compensation = 51, .led_compensation = 51,
.use_rts_for_aggregation = true, /* use rts/cts protection */
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.support_ct_kill_exit = true, .support_ct_kill_exit = true,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF, .plcp_delta_threshold = IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF,
...@@ -277,6 +270,26 @@ struct iwl_cfg iwl1000_bgn_cfg = { ...@@ -277,6 +270,26 @@ struct iwl_cfg iwl1000_bgn_cfg = {
.sensitivity_calib_by_driver = true, .sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true, .chain_noise_calib_by_driver = true,
}; };
static struct iwl_ht_params iwl1000_ht_params = {
.ht_greenfield_support = true,
.use_rts_for_aggregation = true, /* use rts/cts protection */
};
struct iwl_cfg iwl1000_bgn_cfg = {
.name = "Intel(R) Centrino(R) Wireless-N 1000 BGN",
.fw_name_pre = IWL1000_FW_PRE,
.ucode_api_max = IWL1000_UCODE_API_MAX,
.ucode_api_min = IWL1000_UCODE_API_MIN,
.sku = IWL_SKU_G|IWL_SKU_N,
.valid_tx_ant = ANT_A,
.valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_1000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
.ops = &iwl1000_ops,
.mod_params = &iwlagn_mod_params,
.base_params = &iwl1000_base_params,
.ht_params = &iwl1000_ht_params,
};
struct iwl_cfg iwl1000_bg_cfg = { struct iwl_cfg iwl1000_bg_cfg = {
.name = "Intel(R) Centrino(R) Wireless-N 1000 BG", .name = "Intel(R) Centrino(R) Wireless-N 1000 BG",
...@@ -284,30 +297,45 @@ struct iwl_cfg iwl1000_bg_cfg = { ...@@ -284,30 +297,45 @@ struct iwl_cfg iwl1000_bg_cfg = {
.ucode_api_max = IWL1000_UCODE_API_MAX, .ucode_api_max = IWL1000_UCODE_API_MAX,
.ucode_api_min = IWL1000_UCODE_API_MIN, .ucode_api_min = IWL1000_UCODE_API_MIN,
.sku = IWL_SKU_G, .sku = IWL_SKU_G,
.valid_tx_ant = ANT_A,
.valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_1000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
.ops = &iwl1000_ops, .ops = &iwl1000_ops,
.eeprom_size = OTP_LOW_IMAGE_SIZE, .mod_params = &iwlagn_mod_params,
.base_params = &iwl1000_base_params,
};
struct iwl_cfg iwl100_bgn_cfg = {
.name = "Intel(R) 100 Series 1x1 BGN",
.fw_name_pre = IWL100_FW_PRE,
.ucode_api_max = IWL100_UCODE_API_MAX,
.ucode_api_min = IWL100_UCODE_API_MIN,
.sku = IWL_SKU_G|IWL_SKU_N,
.valid_tx_ant = ANT_A,
.valid_rx_ant = ANT_A,
.eeprom_ver = EEPROM_1000_EEPROM_VERSION, .eeprom_ver = EEPROM_1000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl1000_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.base_params = &iwl1000_base_params,
.ht_params = &iwl1000_ht_params,
};
struct iwl_cfg iwl100_bg_cfg = {
.name = "Intel(R) 100 Series 1x1 BG",
.fw_name_pre = IWL100_FW_PRE,
.ucode_api_max = IWL100_UCODE_API_MAX,
.ucode_api_min = IWL100_UCODE_API_MIN,
.sku = IWL_SKU_G,
.valid_tx_ant = ANT_A, .valid_tx_ant = ANT_A,
.valid_rx_ant = ANT_AB, .valid_rx_ant = ANT_A,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, .eeprom_ver = EEPROM_1000_EEPROM_VERSION,
.set_l0s = true, .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
.use_bsm = false, .ops = &iwl1000_ops,
.max_ll_items = OTP_MAX_LL_ITEMS_1000, .mod_params = &iwlagn_mod_params,
.shadow_ram_support = false, .base_params = &iwl1000_base_params,
.led_compensation = 51,
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.support_ct_kill_exit = true,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
.max_event_log_size = 128,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
}; };
MODULE_FIRMWARE(IWL1000_MODULE_FIRMWARE(IWL1000_UCODE_API_MAX)); MODULE_FIRMWARE(IWL1000_MODULE_FIRMWARE(IWL1000_UCODE_API_MAX));
MODULE_FIRMWARE(IWL100_MODULE_FIRMWARE(IWL100_UCODE_API_MAX));
...@@ -406,7 +406,7 @@ static bool iwl3945_good_plcp_health(struct iwl_priv *priv, ...@@ -406,7 +406,7 @@ static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
unsigned int plcp_msec; unsigned int plcp_msec;
unsigned long plcp_received_jiffies; unsigned long plcp_received_jiffies;
if (priv->cfg->plcp_delta_threshold == if (priv->cfg->base_params->plcp_delta_threshold ==
IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) { IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n"); IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
return rc; return rc;
...@@ -432,7 +432,7 @@ static bool iwl3945_good_plcp_health(struct iwl_priv *priv, ...@@ -432,7 +432,7 @@ static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
if ((combined_plcp_delta > 0) && if ((combined_plcp_delta > 0) &&
((combined_plcp_delta * 100) / plcp_msec) > ((combined_plcp_delta * 100) / plcp_msec) >
priv->cfg->plcp_delta_threshold) { priv->cfg->base_params->plcp_delta_threshold) {
/* /*
* if plcp_err exceed the threshold, the following * if plcp_err exceed the threshold, the following
* data is printed in csv format: * data is printed in csv format:
...@@ -444,7 +444,7 @@ static bool iwl3945_good_plcp_health(struct iwl_priv *priv, ...@@ -444,7 +444,7 @@ static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
*/ */
IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, " IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
"%u, %d, %u mSecs\n", "%u, %d, %u mSecs\n",
priv->cfg->plcp_delta_threshold, priv->cfg->base_params->plcp_delta_threshold,
le32_to_cpu(current_stat.rx.ofdm.plcp_err), le32_to_cpu(current_stat.rx.ofdm.plcp_err),
combined_plcp_delta, plcp_msec); combined_plcp_delta, plcp_msec);
/* /*
...@@ -2421,7 +2421,7 @@ int iwl3945_hw_set_hw_params(struct iwl_priv *priv) ...@@ -2421,7 +2421,7 @@ int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
} }
/* Assign number of Usable TX queues */ /* Assign number of Usable TX queues */
priv->hw_params.max_txq_num = priv->cfg->num_of_queues; priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd); priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K); priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
...@@ -2722,22 +2722,12 @@ static const struct iwl_ops iwl3945_ops = { ...@@ -2722,22 +2722,12 @@ static const struct iwl_ops iwl3945_ops = {
.led = &iwl3945_led_ops, .led = &iwl3945_led_ops,
}; };
static struct iwl_cfg iwl3945_bg_cfg = { static struct iwl_base_params iwl3945_base_params = {
.name = "3945BG",
.fw_name_pre = IWL3945_FW_PRE,
.ucode_api_max = IWL3945_UCODE_API_MAX,
.ucode_api_min = IWL3945_UCODE_API_MIN,
.sku = IWL_SKU_G,
.eeprom_size = IWL3945_EEPROM_IMG_SIZE, .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
.eeprom_ver = EEPROM_3945_EEPROM_VERSION,
.ops = &iwl3945_ops,
.num_of_queues = IWL39_NUM_QUEUES,
.mod_params = &iwl3945_mod_params,
.pll_cfg_val = CSR39_ANA_PLL_CFG_VAL, .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
.set_l0s = false, .set_l0s = false,
.use_bsm = true, .use_bsm = true,
.use_isr_legacy = true, .use_isr_legacy = true,
.ht_greenfield_support = false,
.led_compensation = 64, .led_compensation = 64,
.broken_powersave = true, .broken_powersave = true,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
...@@ -2746,25 +2736,28 @@ static struct iwl_cfg iwl3945_bg_cfg = { ...@@ -2746,25 +2736,28 @@ static struct iwl_cfg iwl3945_bg_cfg = {
.tx_power_by_driver = true, .tx_power_by_driver = true,
}; };
static struct iwl_cfg iwl3945_bg_cfg = {
.name = "3945BG",
.fw_name_pre = IWL3945_FW_PRE,
.ucode_api_max = IWL3945_UCODE_API_MAX,
.ucode_api_min = IWL3945_UCODE_API_MIN,
.sku = IWL_SKU_G,
.eeprom_ver = EEPROM_3945_EEPROM_VERSION,
.ops = &iwl3945_ops,
.mod_params = &iwl3945_mod_params,
.base_params = &iwl3945_base_params,
};
static struct iwl_cfg iwl3945_abg_cfg = { static struct iwl_cfg iwl3945_abg_cfg = {
.name = "3945ABG", .name = "3945ABG",
.fw_name_pre = IWL3945_FW_PRE, .fw_name_pre = IWL3945_FW_PRE,
.ucode_api_max = IWL3945_UCODE_API_MAX, .ucode_api_max = IWL3945_UCODE_API_MAX,
.ucode_api_min = IWL3945_UCODE_API_MIN, .ucode_api_min = IWL3945_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G, .sku = IWL_SKU_A|IWL_SKU_G,
.eeprom_size = IWL3945_EEPROM_IMG_SIZE,
.eeprom_ver = EEPROM_3945_EEPROM_VERSION, .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
.ops = &iwl3945_ops, .ops = &iwl3945_ops,
.num_of_queues = IWL39_NUM_QUEUES,
.mod_params = &iwl3945_mod_params, .mod_params = &iwl3945_mod_params,
.use_isr_legacy = true, .base_params = &iwl3945_base_params,
.ht_greenfield_support = false,
.led_compensation = 64,
.broken_powersave = true,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
.max_event_log_size = 512,
.tx_power_by_driver = true,
}; };
DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = { DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
......
...@@ -647,13 +647,13 @@ static int iwl4965_hw_set_hw_params(struct iwl_priv *priv) ...@@ -647,13 +647,13 @@ static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
{ {
if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES) priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
priv->cfg->num_of_queues = priv->cfg->base_params->num_of_queues =
priv->cfg->mod_params->num_of_queues; priv->cfg->mod_params->num_of_queues;
priv->hw_params.max_txq_num = priv->cfg->num_of_queues; priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM; priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
priv->hw_params.scd_bc_tbls_size = priv->hw_params.scd_bc_tbls_size =
priv->cfg->num_of_queues * priv->cfg->base_params->num_of_queues *
sizeof(struct iwl4965_scd_bc_tbl); sizeof(struct iwl4965_scd_bc_tbl);
priv->hw_params.tfd_size = sizeof(struct iwl_tfd); priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
priv->hw_params.max_stations = IWL4965_STATION_COUNT; priv->hw_params.max_stations = IWL4965_STATION_COUNT;
...@@ -1724,13 +1724,13 @@ static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, ...@@ -1724,13 +1724,13 @@ static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
u16 ssn_idx, u8 tx_fifo) u16 ssn_idx, u8 tx_fifo)
{ {
if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
(IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues (IWL49_FIRST_AMPDU_QUEUE +
<= txq_id)) { priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
IWL_WARN(priv, IWL_WARN(priv,
"queue number out of range: %d, must be %d to %d\n", "queue number out of range: %d, must be %d to %d\n",
txq_id, IWL49_FIRST_AMPDU_QUEUE, txq_id, IWL49_FIRST_AMPDU_QUEUE,
IWL49_FIRST_AMPDU_QUEUE + IWL49_FIRST_AMPDU_QUEUE +
priv->cfg->num_of_ampdu_queues - 1); priv->cfg->base_params->num_of_ampdu_queues - 1);
return -EINVAL; return -EINVAL;
} }
...@@ -1792,13 +1792,13 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id, ...@@ -1792,13 +1792,13 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
int ret; int ret;
if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
(IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues (IWL49_FIRST_AMPDU_QUEUE +
<= txq_id)) { priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
IWL_WARN(priv, IWL_WARN(priv,
"queue number out of range: %d, must be %d to %d\n", "queue number out of range: %d, must be %d to %d\n",
txq_id, IWL49_FIRST_AMPDU_QUEUE, txq_id, IWL49_FIRST_AMPDU_QUEUE,
IWL49_FIRST_AMPDU_QUEUE + IWL49_FIRST_AMPDU_QUEUE +
priv->cfg->num_of_ampdu_queues - 1); priv->cfg->base_params->num_of_ampdu_queues - 1);
return -EINVAL; return -EINVAL;
} }
...@@ -2302,26 +2302,14 @@ static const struct iwl_ops iwl4965_ops = { ...@@ -2302,26 +2302,14 @@ static const struct iwl_ops iwl4965_ops = {
.led = &iwlagn_led_ops, .led = &iwlagn_led_ops,
}; };
struct iwl_cfg iwl4965_agn_cfg = { static struct iwl_base_params iwl4965_base_params = {
.name = "Intel(R) Wireless WiFi Link 4965AGN",
.fw_name_pre = IWL4965_FW_PRE,
.ucode_api_max = IWL4965_UCODE_API_MAX,
.ucode_api_min = IWL4965_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.eeprom_size = IWL4965_EEPROM_IMG_SIZE, .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
.eeprom_ver = EEPROM_4965_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
.ops = &iwl4965_ops,
.num_of_queues = IWL49_NUM_QUEUES, .num_of_queues = IWL49_NUM_QUEUES,
.num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES, .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_AB,
.valid_rx_ant = ANT_ABC,
.pll_cfg_val = 0, .pll_cfg_val = 0,
.set_l0s = true, .set_l0s = true,
.use_bsm = true, .use_bsm = true,
.use_isr_legacy = true, .use_isr_legacy = true,
.ht_greenfield_support = false,
.broken_powersave = true, .broken_powersave = true,
.led_compensation = 61, .led_compensation = 61,
.chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS, .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
...@@ -2333,6 +2321,21 @@ struct iwl_cfg iwl4965_agn_cfg = { ...@@ -2333,6 +2321,21 @@ struct iwl_cfg iwl4965_agn_cfg = {
.ucode_tracing = true, .ucode_tracing = true,
.sensitivity_calib_by_driver = true, .sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true, .chain_noise_calib_by_driver = true,
};
struct iwl_cfg iwl4965_agn_cfg = {
.name = "Intel(R) Wireless WiFi Link 4965AGN",
.fw_name_pre = IWL4965_FW_PRE,
.ucode_api_max = IWL4965_UCODE_API_MAX,
.ucode_api_min = IWL4965_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.valid_tx_ant = ANT_AB,
.valid_rx_ant = ANT_ABC,
.eeprom_ver = EEPROM_4965_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
.ops = &iwl4965_ops,
.mod_params = &iwlagn_mod_params,
.base_params = &iwl4965_base_params,
/* /*
* Force use of chains B and C for scan RX on 5 GHz band * Force use of chains B and C for scan RX on 5 GHz band
* because the device has off-channel reception on chain A. * because the device has off-channel reception on chain A.
......
...@@ -170,13 +170,13 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) ...@@ -170,13 +170,13 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
{ {
if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES) priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES)
priv->cfg->num_of_queues = priv->cfg->base_params->num_of_queues =
priv->cfg->mod_params->num_of_queues; priv->cfg->mod_params->num_of_queues;
priv->hw_params.max_txq_num = priv->cfg->num_of_queues; priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
priv->hw_params.scd_bc_tbls_size = priv->hw_params.scd_bc_tbls_size =
priv->cfg->num_of_queues * priv->cfg->base_params->num_of_queues *
sizeof(struct iwlagn_scd_bc_tbl); sizeof(struct iwlagn_scd_bc_tbl);
priv->hw_params.tfd_size = sizeof(struct iwl_tfd); priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
priv->hw_params.max_stations = IWLAGN_STATION_COUNT; priv->hw_params.max_stations = IWLAGN_STATION_COUNT;
...@@ -217,13 +217,13 @@ static int iwl5150_hw_set_hw_params(struct iwl_priv *priv) ...@@ -217,13 +217,13 @@ static int iwl5150_hw_set_hw_params(struct iwl_priv *priv)
{ {
if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES) priv->cfg->mod_params->num_of_queues <= IWLAGN_NUM_QUEUES)
priv->cfg->num_of_queues = priv->cfg->base_params->num_of_queues =
priv->cfg->mod_params->num_of_queues; priv->cfg->mod_params->num_of_queues;
priv->hw_params.max_txq_num = priv->cfg->num_of_queues; priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
priv->hw_params.scd_bc_tbls_size = priv->hw_params.scd_bc_tbls_size =
priv->cfg->num_of_queues * priv->cfg->base_params->num_of_queues *
sizeof(struct iwlagn_scd_bc_tbl); sizeof(struct iwlagn_scd_bc_tbl);
priv->hw_params.tfd_size = sizeof(struct iwl_tfd); priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
priv->hw_params.max_stations = IWLAGN_STATION_COUNT; priv->hw_params.max_stations = IWLAGN_STATION_COUNT;
...@@ -504,27 +504,14 @@ static const struct iwl_ops iwl5150_ops = { ...@@ -504,27 +504,14 @@ static const struct iwl_ops iwl5150_ops = {
.led = &iwlagn_led_ops, .led = &iwlagn_led_ops,
}; };
struct iwl_cfg iwl5300_agn_cfg = { static struct iwl_base_params iwl5000_base_params = {
.name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
.fw_name_pre = IWL5000_FW_PRE,
.ucode_api_max = IWL5000_UCODE_API_MAX,
.ucode_api_min = IWL5000_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.ops = &iwl5000_ops,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .eeprom_size = IWLAGN_EEPROM_IMG_SIZE,
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .num_of_queues = IWLAGN_NUM_QUEUES,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES, .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_ABC,
.valid_rx_ant = ANT_ABC,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true, .set_l0s = true,
.use_bsm = false, .use_bsm = false,
.ht_greenfield_support = true,
.led_compensation = 51, .led_compensation = 51,
.use_rts_for_aggregation = true, /* use rts/cts protection */
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000, .chain_noise_scale = 1000,
...@@ -534,6 +521,26 @@ struct iwl_cfg iwl5300_agn_cfg = { ...@@ -534,6 +521,26 @@ struct iwl_cfg iwl5300_agn_cfg = {
.sensitivity_calib_by_driver = true, .sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true, .chain_noise_calib_by_driver = true,
}; };
static struct iwl_ht_params iwl5000_ht_params = {
.ht_greenfield_support = true,
.use_rts_for_aggregation = true, /* use rts/cts protection */
};
struct iwl_cfg iwl5300_agn_cfg = {
.name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
.fw_name_pre = IWL5000_FW_PRE,
.ucode_api_max = IWL5000_UCODE_API_MAX,
.ucode_api_min = IWL5000_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.valid_tx_ant = ANT_ABC,
.valid_rx_ant = ANT_ABC,
.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
.ops = &iwl5000_ops,
.mod_params = &iwlagn_mod_params,
.base_params = &iwl5000_base_params,
.ht_params = &iwl5000_ht_params,
};
struct iwl_cfg iwl5100_bgn_cfg = { struct iwl_cfg iwl5100_bgn_cfg = {
.name = "Intel(R) WiFi Link 5100 BGN", .name = "Intel(R) WiFi Link 5100 BGN",
...@@ -541,29 +548,14 @@ struct iwl_cfg iwl5100_bgn_cfg = { ...@@ -541,29 +548,14 @@ struct iwl_cfg iwl5100_bgn_cfg = {
.ucode_api_max = IWL5000_UCODE_API_MAX, .ucode_api_max = IWL5000_UCODE_API_MAX,
.ucode_api_min = IWL5000_UCODE_API_MIN, .ucode_api_min = IWL5000_UCODE_API_MIN,
.sku = IWL_SKU_G|IWL_SKU_N, .sku = IWL_SKU_G|IWL_SKU_N,
.ops = &iwl5000_ops, .valid_tx_ant = ANT_B,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_5000_EEPROM_VERSION, .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl5000_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_B, .base_params = &iwl5000_base_params,
.valid_rx_ant = ANT_AB, .ht_params = &iwl5000_ht_params,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.ht_greenfield_support = true,
.led_compensation = 51,
.use_rts_for_aggregation = true, /* use rts/cts protection */
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
.max_event_log_size = 512,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
}; };
struct iwl_cfg iwl5100_abg_cfg = { struct iwl_cfg iwl5100_abg_cfg = {
...@@ -572,27 +564,13 @@ struct iwl_cfg iwl5100_abg_cfg = { ...@@ -572,27 +564,13 @@ struct iwl_cfg iwl5100_abg_cfg = {
.ucode_api_max = IWL5000_UCODE_API_MAX, .ucode_api_max = IWL5000_UCODE_API_MAX,
.ucode_api_min = IWL5000_UCODE_API_MIN, .ucode_api_min = IWL5000_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G, .sku = IWL_SKU_A|IWL_SKU_G,
.ops = &iwl5000_ops, .valid_tx_ant = ANT_B,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_5000_EEPROM_VERSION, .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl5000_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_B, .base_params = &iwl5000_base_params,
.valid_rx_ant = ANT_AB,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.led_compensation = 51,
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
.max_event_log_size = 512,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
}; };
struct iwl_cfg iwl5100_agn_cfg = { struct iwl_cfg iwl5100_agn_cfg = {
...@@ -601,29 +579,14 @@ struct iwl_cfg iwl5100_agn_cfg = { ...@@ -601,29 +579,14 @@ struct iwl_cfg iwl5100_agn_cfg = {
.ucode_api_max = IWL5000_UCODE_API_MAX, .ucode_api_max = IWL5000_UCODE_API_MAX,
.ucode_api_min = IWL5000_UCODE_API_MIN, .ucode_api_min = IWL5000_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.ops = &iwl5000_ops, .valid_tx_ant = ANT_B,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_5000_EEPROM_VERSION, .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl5000_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_B, .base_params = &iwl5000_base_params,
.valid_rx_ant = ANT_AB, .ht_params = &iwl5000_ht_params,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.ht_greenfield_support = true,
.led_compensation = 51,
.use_rts_for_aggregation = true, /* use rts/cts protection */
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
.max_event_log_size = 512,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
}; };
struct iwl_cfg iwl5350_agn_cfg = { struct iwl_cfg iwl5350_agn_cfg = {
...@@ -632,29 +595,14 @@ struct iwl_cfg iwl5350_agn_cfg = { ...@@ -632,29 +595,14 @@ struct iwl_cfg iwl5350_agn_cfg = {
.ucode_api_max = IWL5000_UCODE_API_MAX, .ucode_api_max = IWL5000_UCODE_API_MAX,
.ucode_api_min = IWL5000_UCODE_API_MIN, .ucode_api_min = IWL5000_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.ops = &iwl5000_ops, .valid_tx_ant = ANT_ABC,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .valid_rx_ant = ANT_ABC,
.eeprom_ver = EEPROM_5050_EEPROM_VERSION, .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl5000_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_ABC, .base_params = &iwl5000_base_params,
.valid_rx_ant = ANT_ABC, .ht_params = &iwl5000_ht_params,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.ht_greenfield_support = true,
.led_compensation = 51,
.use_rts_for_aggregation = true, /* use rts/cts protection */
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
.max_event_log_size = 512,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
}; };
struct iwl_cfg iwl5150_agn_cfg = { struct iwl_cfg iwl5150_agn_cfg = {
...@@ -663,29 +611,14 @@ struct iwl_cfg iwl5150_agn_cfg = { ...@@ -663,29 +611,14 @@ struct iwl_cfg iwl5150_agn_cfg = {
.ucode_api_max = IWL5150_UCODE_API_MAX, .ucode_api_max = IWL5150_UCODE_API_MAX,
.ucode_api_min = IWL5150_UCODE_API_MIN, .ucode_api_min = IWL5150_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
.ops = &iwl5150_ops, .valid_tx_ant = ANT_A,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_5050_EEPROM_VERSION, .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl5150_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_A, .base_params = &iwl5000_base_params,
.valid_rx_ant = ANT_AB, .ht_params = &iwl5000_ht_params,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.ht_greenfield_support = true,
.led_compensation = 51,
.use_rts_for_aggregation = true, /* use rts/cts protection */
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
.max_event_log_size = 512,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
.need_dc_calib = true, .need_dc_calib = true,
}; };
...@@ -695,27 +628,13 @@ struct iwl_cfg iwl5150_abg_cfg = { ...@@ -695,27 +628,13 @@ struct iwl_cfg iwl5150_abg_cfg = {
.ucode_api_max = IWL5150_UCODE_API_MAX, .ucode_api_max = IWL5150_UCODE_API_MAX,
.ucode_api_min = IWL5150_UCODE_API_MIN, .ucode_api_min = IWL5150_UCODE_API_MIN,
.sku = IWL_SKU_A|IWL_SKU_G, .sku = IWL_SKU_A|IWL_SKU_G,
.ops = &iwl5150_ops, .valid_tx_ant = ANT_A,
.eeprom_size = IWLAGN_EEPROM_IMG_SIZE, .valid_rx_ant = ANT_AB,
.eeprom_ver = EEPROM_5050_EEPROM_VERSION, .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
.num_of_queues = IWLAGN_NUM_QUEUES, .ops = &iwl5150_ops,
.num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
.mod_params = &iwlagn_mod_params, .mod_params = &iwlagn_mod_params,
.valid_tx_ant = ANT_A, .base_params = &iwl5000_base_params,
.valid_rx_ant = ANT_AB,
.pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
.set_l0s = true,
.use_bsm = false,
.led_compensation = 51,
.chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
.plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
.chain_noise_scale = 1000,
.monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
.max_event_log_size = 512,
.ucode_tracing = true,
.sensitivity_calib_by_driver = true,
.chain_noise_calib_by_driver = true,
.need_dc_calib = true, .need_dc_calib = true,
}; };
......
...@@ -631,7 +631,8 @@ void iwl_sensitivity_calibration(struct iwl_priv *priv, void *resp) ...@@ -631,7 +631,8 @@ void iwl_sensitivity_calibration(struct iwl_priv *priv, void *resp)
} }
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
if (priv->cfg->bt_statistics) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
rx_info = &(((struct iwl_bt_notif_statistics *)resp)-> rx_info = &(((struct iwl_bt_notif_statistics *)resp)->
rx.general.common); rx.general.common);
ofdm = &(((struct iwl_bt_notif_statistics *)resp)->rx.ofdm); ofdm = &(((struct iwl_bt_notif_statistics *)resp)->rx.ofdm);
...@@ -786,7 +787,8 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp) ...@@ -786,7 +787,8 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
} }
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
if (priv->cfg->bt_statistics) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
rx_info = &(((struct iwl_bt_notif_statistics *)stat_resp)-> rx_info = &(((struct iwl_bt_notif_statistics *)stat_resp)->
rx.general.common); rx.general.common);
} else { } else {
...@@ -801,7 +803,8 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp) ...@@ -801,7 +803,8 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
rxon_band24 = !!(ctx->staging.flags & RXON_FLG_BAND_24G_MSK); rxon_band24 = !!(ctx->staging.flags & RXON_FLG_BAND_24G_MSK);
rxon_chnum = le16_to_cpu(ctx->staging.channel); rxon_chnum = le16_to_cpu(ctx->staging.channel);
if (priv->cfg->bt_statistics) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
stat_band24 = !!(((struct iwl_bt_notif_statistics *) stat_band24 = !!(((struct iwl_bt_notif_statistics *)
stat_resp)->flag & stat_resp)->flag &
STATISTICS_REPLY_FLG_BAND_24G_MSK); STATISTICS_REPLY_FLG_BAND_24G_MSK);
...@@ -861,16 +864,17 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp) ...@@ -861,16 +864,17 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
/* If this is the "chain_noise_num_beacons", determine: /* If this is the "chain_noise_num_beacons", determine:
* 1) Disconnected antennas (using signal strengths) * 1) Disconnected antennas (using signal strengths)
* 2) Differential gain (using silence noise) to balance receivers */ * 2) Differential gain (using silence noise) to balance receivers */
if (data->beacon_count != priv->cfg->chain_noise_num_beacons) if (data->beacon_count !=
priv->cfg->base_params->chain_noise_num_beacons)
return; return;
/* Analyze signal for disconnected antenna */ /* Analyze signal for disconnected antenna */
average_sig[0] = average_sig[0] = data->chain_signal_a /
(data->chain_signal_a) / priv->cfg->chain_noise_num_beacons; priv->cfg->base_params->chain_noise_num_beacons;
average_sig[1] = average_sig[1] = data->chain_signal_b /
(data->chain_signal_b) / priv->cfg->chain_noise_num_beacons; priv->cfg->base_params->chain_noise_num_beacons;
average_sig[2] = average_sig[2] = data->chain_signal_c /
(data->chain_signal_c) / priv->cfg->chain_noise_num_beacons; priv->cfg->base_params->chain_noise_num_beacons;
if (average_sig[0] >= average_sig[1]) { if (average_sig[0] >= average_sig[1]) {
max_average_sig = average_sig[0]; max_average_sig = average_sig[0];
...@@ -920,7 +924,9 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp) ...@@ -920,7 +924,9 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
* To be safe, simply mask out any chains that we know * To be safe, simply mask out any chains that we know
* are not on the device. * are not on the device.
*/ */
if (priv->cfg->advanced_bt_coexist && priv->bt_full_concurrent) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->advanced_bt_coexist &&
priv->bt_full_concurrent) {
/* operated as 1x1 in full concurrency mode */ /* operated as 1x1 in full concurrency mode */
active_chains &= first_antenna(priv->hw_params.valid_rx_ant); active_chains &= first_antenna(priv->hw_params.valid_rx_ant);
} else } else
...@@ -967,12 +973,12 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp) ...@@ -967,12 +973,12 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
active_chains); active_chains);
/* Analyze noise for rx balance */ /* Analyze noise for rx balance */
average_noise[0] = average_noise[0] = data->chain_noise_a /
((data->chain_noise_a) / priv->cfg->chain_noise_num_beacons); priv->cfg->base_params->chain_noise_num_beacons;
average_noise[1] = average_noise[1] = data->chain_noise_b /
((data->chain_noise_b) / priv->cfg->chain_noise_num_beacons); priv->cfg->base_params->chain_noise_num_beacons;
average_noise[2] = average_noise[2] = data->chain_noise_c /
((data->chain_noise_c) / priv->cfg->chain_noise_num_beacons); priv->cfg->base_params->chain_noise_num_beacons;
for (i = 0; i < NUM_RX_CHAINS; i++) { for (i = 0; i < NUM_RX_CHAINS; i++) {
if (!(data->disconn_array[i]) && if (!(data->disconn_array[i]) &&
......
...@@ -39,7 +39,8 @@ static int iwl_statistics_flag(struct iwl_priv *priv, char *buf, int bufsz) ...@@ -39,7 +39,8 @@ static int iwl_statistics_flag(struct iwl_priv *priv, char *buf, int bufsz)
int p = 0; int p = 0;
u32 flag; u32 flag;
if (priv->cfg->bt_statistics) if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics)
flag = le32_to_cpu(priv->_agn.statistics_bt.flag); flag = le32_to_cpu(priv->_agn.statistics_bt.flag);
else else
flag = le32_to_cpu(priv->_agn.statistics.flag); flag = le32_to_cpu(priv->_agn.statistics.flag);
...@@ -88,7 +89,8 @@ ssize_t iwl_ucode_rx_stats_read(struct file *file, char __user *user_buf, ...@@ -88,7 +89,8 @@ ssize_t iwl_ucode_rx_stats_read(struct file *file, char __user *user_buf,
* the last statistics notification from uCode * the last statistics notification from uCode
* might not reflect the current uCode activity * might not reflect the current uCode activity
*/ */
if (priv->cfg->bt_statistics) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
ofdm = &priv->_agn.statistics_bt.rx.ofdm; ofdm = &priv->_agn.statistics_bt.rx.ofdm;
cck = &priv->_agn.statistics_bt.rx.cck; cck = &priv->_agn.statistics_bt.rx.cck;
general = &priv->_agn.statistics_bt.rx.general.common; general = &priv->_agn.statistics_bt.rx.general.common;
...@@ -534,7 +536,8 @@ ssize_t iwl_ucode_tx_stats_read(struct file *file, ...@@ -534,7 +536,8 @@ ssize_t iwl_ucode_tx_stats_read(struct file *file,
* the last statistics notification from uCode * the last statistics notification from uCode
* might not reflect the current uCode activity * might not reflect the current uCode activity
*/ */
if (priv->cfg->bt_statistics) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
tx = &priv->_agn.statistics_bt.tx; tx = &priv->_agn.statistics_bt.tx;
accum_tx = &priv->_agn.accum_statistics_bt.tx; accum_tx = &priv->_agn.accum_statistics_bt.tx;
delta_tx = &priv->_agn.delta_statistics_bt.tx; delta_tx = &priv->_agn.delta_statistics_bt.tx;
...@@ -734,7 +737,8 @@ ssize_t iwl_ucode_general_stats_read(struct file *file, char __user *user_buf, ...@@ -734,7 +737,8 @@ ssize_t iwl_ucode_general_stats_read(struct file *file, char __user *user_buf,
* the last statistics notification from uCode * the last statistics notification from uCode
* might not reflect the current uCode activity * might not reflect the current uCode activity
*/ */
if (priv->cfg->bt_statistics) { if (priv->cfg->bt_params &&
priv->cfg->bt_params->bt_statistics) {
general = &priv->_agn.statistics_bt.general.common; general = &priv->_agn.statistics_bt.general.common;
dbg = &priv->_agn.statistics_bt.general.common.dbg; dbg = &priv->_agn.statistics_bt.general.common.dbg;
div = &priv->_agn.statistics_bt.general.common.div; div = &priv->_agn.statistics_bt.general.common.div;
......
...@@ -137,7 +137,7 @@ static void iwlagn_gain_computation(struct iwl_priv *priv, ...@@ -137,7 +137,7 @@ static void iwlagn_gain_computation(struct iwl_priv *priv,
continue; continue;
} }
delta_g = (priv->cfg->chain_noise_scale * delta_g = (priv->cfg->base_params->chain_noise_scale *
((s32)average_noise[default_chain] - ((s32)average_noise[default_chain] -
(s32)average_noise[i])) / 1500; (s32)average_noise[i])) / 1500;
...@@ -222,7 +222,8 @@ static void iwlagn_tx_cmd_protection(struct iwl_priv *priv, ...@@ -222,7 +222,8 @@ static void iwlagn_tx_cmd_protection(struct iwl_priv *priv,
return; return;
} }
if (priv->cfg->use_rts_for_aggregation && if (priv->cfg->ht_params &&
priv->cfg->ht_params->use_rts_for_aggregation &&
info->flags & IEEE80211_TX_CTL_AMPDU) { info->flags & IEEE80211_TX_CTL_AMPDU) {
*tx_flags |= TX_CMD_FLG_PROT_REQUIRE_MSK; *tx_flags |= TX_CMD_FLG_PROT_REQUIRE_MSK;
return; return;
......
...@@ -59,7 +59,7 @@ void iwl_free_isr_ict(struct iwl_priv *priv) ...@@ -59,7 +59,7 @@ void iwl_free_isr_ict(struct iwl_priv *priv)
int iwl_alloc_isr_ict(struct iwl_priv *priv) int iwl_alloc_isr_ict(struct iwl_priv *priv)
{ {
if (priv->cfg->use_isr_legacy) if (priv->cfg->base_params->use_isr_legacy)
return 0; return 0;
/* allocate shrared data table */ /* allocate shrared data table */
priv->_agn.ict_tbl_vir = priv->_agn.ict_tbl_vir =
......
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