staging: r8822be: Add phydm mini driver

The RTL8822BE, an 802.11ac wireless network card, is now appearing in
new computers. Its driver is being placed in staging to reduce the time
that users of this new card will have access to in-kernel drivers.

New Realtek wireless devices have a new method for PHY control and
dynamic management. The RTL8822BE is the first of these devices, thus
there is additional code required.

In the final version, this code will be a separate module; however,
it is combined with the r8822be driver to minimize the interference
with the drivers in the wireless tree.
Signed-off-by: NPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: NLarry Finger <Larry.Finger@lwfinger.net>
Cc: Yan-Hsuan Chuang <yhchuang@realtek.com>
Cc: Birming Chiu <birming@realtek.com>
Cc: Shaofu <shaofu@realtek.com>
Cc: Steven Ting <steventing@realtek.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/staging/rtlwifi/phydm/halphyrf_ce.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#include "phydm_kfree.h"
+
+#include "rtl8822b/phydm_iqk_8822b.h"
+
+#include "phydm_powertracking_ce.h"
+
+enum spur_cal_method { PLL_RESET, AFE_PHASE_SEL };
+
+enum pwrtrack_method {
+	BBSWING,
+	TXAGC,
+	MIX_MODE,
+	TSSI_MODE,
+	MIX_2G_TSSI_5G_MODE,
+	MIX_5G_TSSI_2G_MODE
+};
+
+typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void (*func_iqk)(void *, u8, u8, u8);
+typedef void (*func_lck)(void *);
+typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void (*func_set_xtal)(void *);
+
+struct txpwrtrack_cfg {
+	u8 swing_table_size_cck;
+	u8 swing_table_size_ofdm;
+	u8 threshold_iqk;
+	u8 threshold_dpk;
+	u8 average_thermal_num;
+	u8 rf_path_count;
+	u32 thermal_reg_addr;
+	func_set_pwr odm_tx_pwr_track_set_pwr;
+	func_iqk do_iqk;
+	func_lck phy_lc_calibrate;
+	func_swing get_delta_swing_table;
+	func_swing8814only get_delta_swing_table8814only;
+	func_swing_xtal get_delta_swing_xtal_table;
+	func_set_xtal odm_txxtaltrack_set_xtal;
+};
+
+void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
+
+void odm_clear_txpowertracking_state(void *dm_void);
+
+void odm_txpowertracking_callback_thermal_meter(void *dm);
+
+#define ODM_TARGET_CHNL_NUM_2G_5G 59
+
+void odm_reset_iqk_result(void *dm_void);
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
+
+void phydm_rf_init(void *dm_void);
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /*  #ifndef __HAL_PHY_RF_H__ */

drivers/staging/rtlwifi/phydm/mp_precomp.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/

drivers/staging/rtlwifi/phydm/phydm_acs.c

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * *************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+u8 odm_get_auto_channel_select_result(void *dm_void, u8 band)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+	struct acs_info *acs = &dm->dm_acs;
+	u8 result;
+
+	if (band == ODM_BAND_2_4G) {
+		ODM_RT_TRACE(
+			dm, ODM_COMP_ACS,
+			"[struct acs_info] %s(): clean_channel_2g(%d)\n",
+			__func__, acs->clean_channel_2g);
+		result = (u8)acs->clean_channel_2g;
+	} else {
+		ODM_RT_TRACE(
+			dm, ODM_COMP_ACS,
+			"[struct acs_info] %s(): clean_channel_5g(%d)\n",
+			__func__, acs->clean_channel_5g);
+		result = (u8)acs->clean_channel_5g;
+	}
+
+	return result;
+}
+
+static void odm_auto_channel_select_setting(void *dm_void, bool is_enable)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+	u16 period = 0x2710; /* 40ms in default */
+	u16 nhm_type = 0x7;
+
+	ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
+
+	if (is_enable) {
+		/* 20 ms */
+		period = 0x1388;
+		nhm_type = 0x1;
+	}
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		/* PHY parameters initialize for ac series */
+
+		/* 0x990[31:16]=0x2710
+		 * Time duration for NHM unit: 4us, 0x2710=40ms
+		 */
+		odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period);
+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+		/* PHY parameters initialize for n series */
+
+		/* 0x894[31:16]=0x2710
+		 * Time duration for NHM unit: 4us, 0x2710=40ms
+		 */
+		odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, period);
+	}
+}
+
+void odm_auto_channel_select_init(void *dm_void)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+	struct acs_info *acs = &dm->dm_acs;
+	u8 i;
+
+	if (!(dm->support_ability & ODM_BB_NHM_CNT))
+		return;
+
+	if (acs->is_force_acs_result)
+		return;
+
+	ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
+
+	acs->clean_channel_2g = 1;
+	acs->clean_channel_5g = 36;
+
+	for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
+		acs->channel_info_2g[0][i] = 0;
+		acs->channel_info_2g[1][i] = 0;
+	}
+
+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+		for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
+			acs->channel_info_5g[0][i] = 0;
+			acs->channel_info_5g[1][i] = 0;
+		}
+	}
+}
+
+void odm_auto_channel_select_reset(void *dm_void)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+	struct acs_info *acs = &dm->dm_acs;
+
+	if (!(dm->support_ability & ODM_BB_NHM_CNT))
+		return;
+
+	if (acs->is_force_acs_result)
+		return;
+
+	ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s()=========>\n", __func__);
+
+	odm_auto_channel_select_setting(dm, true); /* for 20ms measurement */
+	phydm_nhm_counter_statistics_reset(dm);
+}
+
+void odm_auto_channel_select(void *dm_void, u8 channel)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+	struct acs_info *acs = &dm->dm_acs;
+	u8 channel_idx = 0, search_idx = 0;
+	u16 max_score = 0;
+
+	if (!(dm->support_ability & ODM_BB_NHM_CNT)) {
+		ODM_RT_TRACE(
+			dm, ODM_COMP_DIG,
+			"%s(): Return: support_ability ODM_BB_NHM_CNT is disabled\n",
+			__func__);
+		return;
+	}
+
+	if (acs->is_force_acs_result) {
+		ODM_RT_TRACE(
+			dm, ODM_COMP_DIG,
+			"%s(): Force 2G clean channel = %d, 5G clean channel = %d\n",
+			__func__, acs->clean_channel_2g, acs->clean_channel_5g);
+		return;
+	}
+
+	ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): channel = %d=========>\n",
+		     __func__, channel);
+
+	phydm_get_nhm_counter_statistics(dm);
+	odm_auto_channel_select_setting(dm, false);
+
+	if (channel >= 1 && channel <= 14) {
+		channel_idx = channel - 1;
+		acs->channel_info_2g[1][channel_idx]++;
+
+		if (acs->channel_info_2g[1][channel_idx] >= 2)
+			acs->channel_info_2g[0][channel_idx] =
+				(acs->channel_info_2g[0][channel_idx] >> 1) +
+				(acs->channel_info_2g[0][channel_idx] >> 2) +
+				(dm->nhm_cnt_0 >> 2);
+		else
+			acs->channel_info_2g[0][channel_idx] = dm->nhm_cnt_0;
+
+		ODM_RT_TRACE(dm, ODM_COMP_ACS, "%s(): nhm_cnt_0 = %d\n",
+			     __func__, dm->nhm_cnt_0);
+		ODM_RT_TRACE(
+			dm, ODM_COMP_ACS,
+			"%s(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n",
+			__func__, channel_idx,
+			acs->channel_info_2g[0][channel_idx], channel_idx,
+			acs->channel_info_2g[1][channel_idx]);
+
+		for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G;
+		     search_idx++) {
+			if (acs->channel_info_2g[1][search_idx] != 0 &&
+			    acs->channel_info_2g[0][search_idx] >= max_score) {
+				max_score = acs->channel_info_2g[0][search_idx];
+				acs->clean_channel_2g = search_idx + 1;
+			}
+		}
+		ODM_RT_TRACE(
+			dm, ODM_COMP_ACS,
+			"(1)%s(): 2G: clean_channel_2g = %d, max_score = %d\n",
+			__func__, acs->clean_channel_2g, max_score);
+
+	} else if (channel >= 36) {
+		/* Need to do */
+		acs->clean_channel_5g = channel;
+	}
+}

drivers/staging/rtlwifi/phydm/phydm_acs.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMACS_H__
+#define __PHYDMACS_H__
+
+#define ACS_VERSION "1.1" /*20150729 by YuChen*/
+#define CLM_VERSION "1.0"
+
+#define ODM_MAX_CHANNEL_2G 14
+#define ODM_MAX_CHANNEL_5G 24
+
+/* For phydm_auto_channel_select_setting_ap() */
+#define STORE_DEFAULT_NHM_SETTING 0
+#define RESTORE_DEFAULT_NHM_SETTING 1
+#define ACS_NHM_SETTING 2
+
+struct acs_info {
+	bool is_force_acs_result;
+	u8 clean_channel_2g;
+	u8 clean_channel_5g;
+	/* channel_info[1]: channel score, channel_info[2]:channel_scan_times */
+	u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G];
+	u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
+};
+
+void odm_auto_channel_select_init(void *dm_void);
+
+void odm_auto_channel_select_reset(void *dm_void);
+
+void odm_auto_channel_select(void *dm_void, u8 channel);
+
+u8 odm_get_auto_channel_select_result(void *dm_void, u8 band);
+
+#endif /* #ifndef	__PHYDMACS_H__ */

drivers/staging/rtlwifi/phydm/phydm_adaptivity.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMADAPTIVITY_H__
+#define __PHYDMADAPTIVITY_H__
+
+/*20160902 changed by Kevin, refine method for searching pwdb lower bound*/
+#define ADAPTIVITY_VERSION "9.3.5"
+
+#define pwdb_upper_bound 7
+#define dfir_loss 5
+
+enum phydm_adapinfo {
+	PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
+	PHYDM_ADAPINFO_DCBACKOFF,
+	PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
+	PHYDM_ADAPINFO_TH_L2H_INI,
+	PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
+	PHYDM_ADAPINFO_AP_NUM_TH
+
+};
+
+enum phydm_set_lna {
+	phydm_disable_lna = 0,
+	phydm_enable_lna = 1,
+};
+
+enum phydm_trx_mux_type {
+	phydm_shutdown = 0,
+	phydm_standby_mode = 1,
+	phydm_tx_mode = 2,
+	phydm_rx_mode = 3
+};
+
+enum phydm_mac_edcca_type {
+	phydm_ignore_edcca = 0,
+	phydm_dont_ignore_edcca = 1
+};
+
+struct adaptivity_statistics {
+	s8 th_l2h_ini_backup;
+	s8 th_edcca_hl_diff_backup;
+	s8 igi_base;
+	u8 igi_target;
+	u8 nhm_wait;
+	s8 h2l_lb;
+	s8 l2h_lb;
+	bool is_first_link;
+	bool is_check;
+	bool dynamic_link_adaptivity;
+	u8 ap_num_th;
+	u8 adajust_igi_level;
+	bool acs_for_adaptivity;
+	s8 backup_l2h;
+	s8 backup_h2l;
+	bool is_stop_edcca;
+};
+
+void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca);
+
+void phydm_check_adaptivity(void *dm_void);
+
+void phydm_check_environment(void *dm_void);
+
+void phydm_nhm_counter_statistics_init(void *dm_void);
+
+void phydm_nhm_counter_statistics(void *dm_void);
+
+void phydm_nhm_counter_statistics_reset(void *dm_void);
+
+void phydm_get_nhm_counter_statistics(void *dm_void);
+
+void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state);
+
+void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H);
+
+void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
+		       enum phydm_trx_mux_type rx_mode);
+
+bool phydm_cal_nhm_cnt(void *dm_void);
+
+void phydm_search_pwdb_lower_bound(void *dm_void);
+
+void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
+				u32 value);
+
+void phydm_adaptivity_init(void *dm_void);
+
+void phydm_adaptivity(void *dm_void);
+
+void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
+
+void phydm_pause_edcca_work_item_callback(void *dm_void);
+
+void phydm_resume_edcca_work_item_callback(void *dm_void);
+
+#endif

drivers/staging/rtlwifi/phydm/phydm_adc_sampling.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __INC_ADCSMP_H
+#define __INC_ADCSMP_H
+
+#define DYNAMIC_LA_MODE "1.0" /*2016.07.15  Dino */
+
+struct rt_adcsmp_string {
+	u32 *octet;
+	u32 length;
+	u32 buffer_size;
+	u32 start_pos;
+};
+
+enum rt_adcsmp_trig_sel {
+	PHYDM_ADC_BB_TRIG = 0,
+	PHYDM_ADC_MAC_TRIG = 1,
+	PHYDM_ADC_RF0_TRIG = 2,
+	PHYDM_ADC_RF1_TRIG = 3,
+	PHYDM_MAC_TRIG = 4
+};
+
+enum rt_adcsmp_trig_sig_sel {
+	ADCSMP_TRIG_CRCOK = 0,
+	ADCSMP_TRIG_CRCFAIL = 1,
+	ADCSMP_TRIG_CCA = 2,
+	ADCSMP_TRIG_REG = 3
+};
+
+enum rt_adcsmp_state {
+	ADCSMP_STATE_IDLE = 0,
+	ADCSMP_STATE_SET = 1,
+	ADCSMP_STATE_QUERY = 2
+};
+
+struct rt_adcsmp {
+	struct rt_adcsmp_string adc_smp_buf;
+	enum rt_adcsmp_state adc_smp_state;
+	u8 la_trig_mode;
+	u32 la_trig_sig_sel;
+	u8 la_dma_type;
+	u32 la_trigger_time;
+	u32 la_mac_ref_mask;
+	u32 la_dbg_port;
+	u8 la_trigger_edge;
+	u8 la_smp_rate;
+	u32 la_count;
+	u8 is_bb_trigger;
+	u8 la_work_item_index;
+};
+
+void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
+		 u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time);
+
+void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused);
+
+s32 adc_smp_get_sample_counts(void *dm_void);
+
+s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
+			      u32 index);
+
+void adc_smp_stop(void *dm_void);
+
+void adc_smp_init(void *dm_void);
+
+void adc_smp_de_init(void *dm_void);
+
+void phydm_la_mode_bb_setting(void *dm_void);
+
+void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec);
+
+void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
+				  char *output, u32 *_out_len, u32 input_num);
+#endif

drivers/staging/rtlwifi/phydm/phydm_antdiv.c

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * *************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ******************************************************
+ * when antenna test utility is on or some testing need to disable antenna
+ * diversity, call this function to disable all ODM related mechanisms which
+ * will switch antenna.
+ * *******************************************************/
+void odm_stop_antenna_switch_dm(void *dm_void)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+
+	/* disable ODM antenna diversity */
+	dm->support_ability &= ~ODM_BB_ANT_DIV;
+	ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV, "STOP Antenna Diversity\n");
+}
+
+void phydm_enable_antenna_diversity(void *dm_void)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+
+	dm->support_ability |= ODM_BB_ANT_DIV;
+	ODM_RT_TRACE(dm, ODM_COMP_ANT_DIV,
+		     "AntDiv is enabled & Re-Init AntDiv\n");
+	odm_antenna_diversity_init(dm);
+}
+
+void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
+			)
+{
+	struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
+
+	if (dm->support_ic_type == ODM_RTL8723B) {
+		if (ant_setting == 0) /* ant A*/
+			odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000);
+		else if (ant_setting == 1)
+			odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280);
+	} else if (dm->support_ic_type == ODM_RTL8723D) {
+		if (ant_setting == 0) /* ant A*/
+			odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000);
+		else if (ant_setting == 1)
+			odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280);
+	}
+}
+
+/* ****************************************************** */
+
+void odm_sw_ant_div_rest_after_link(void *dm_void) {}
+
+void odm_ant_div_reset(void *dm_void) {}
+
+void odm_antenna_diversity_init(void *dm_void) {}
+
+void odm_antenna_diversity(void *dm_void) {}

drivers/staging/rtlwifi/phydm/phydm_antdiv.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMANTDIV_H__
+#define __PHYDMANTDIV_H__
+
+/* 2.0 2014.11.04
+ * 2.1 2015.01.13 Dino
+ * 2.2 2015.01.16 Dino
+ * 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
+ * 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
+ * 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
+ *		  by BT, because antenna diversity only works when BT is disable
+ *		  or radio off
+ * 3.4 2015.08.28 Dino  1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
+ *		  Diversity
+ * 3.5 2015.10.07 Stanley  Always check antenna detection result from BT-coex.
+ *		  for 8723B, not from PHYDM
+ * 3.6 2015.11.16 Stanley
+ * 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
+ * 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
+ * 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
+ *		  add cmd for adjust truth table
+ */
+#define ANTDIV_VERSION "3.9"
+
+/* 1 ============================================================
+ * 1  Definition
+ * 1 ============================================================
+ */
+
+#define ANTDIV_INIT 0xff
+#define MAIN_ANT 1 /*ant A or ant Main   or S1*/
+#define AUX_ANT 2 /*AntB or ant Aux   or S0*/
+#define MAX_ANT 3 /* 3 for AP using*/
+
+#define ANT1_2G 0 /* = ANT2_5G	for 8723D  BTG S1 RX S0S1 diversity for 8723D,
+		   * TX fixed at S1
+		   */
+#define ANT2_2G 1 /* = ANT1_5G	for 8723D  BTG S0  RX S0S1 diversity for 8723D,
+		   * TX fixed at S1
+		   */
+/*smart antenna*/
+#define SUPPORT_RF_PATH_NUM 4
+#define SUPPORT_BEAM_PATTERN_NUM 4
+#define NUM_ANTENNA_8821A 2
+
+#define SUPPORT_BEAM_SET_PATTERN_NUM 8
+
+#define NO_FIX_TX_ANT 0
+#define FIX_TX_AT_MAIN 1
+#define FIX_AUX_AT_MAIN 2
+
+/* Antenna Diversty Control type */
+#define ODM_AUTO_ANT 0
+#define ODM_FIX_MAIN_ANT 1
+#define ODM_FIX_AUX_ANT 2
+
+#define ODM_N_ANTDIV_SUPPORT                                                   \
+	(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F |           \
+	 ODM_RTL8723D | ODM_RTL8195A)
+#define ODM_AC_ANTDIV_SUPPORT                                                  \
+	(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C |             \
+	 ODM_RTL8822B | ODM_RTL8814B)
+#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
+#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
+#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
+
+#define ODM_ANTDIV_2G_SUPPORT_IC                                               \
+	(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A |           \
+	 ODM_RTL8188F | ODM_RTL8723D)
+#define ODM_ANTDIV_5G_SUPPORT_IC                                               \
+	(ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
+
+#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
+
+#define ODM_ANTDIV_2G BIT(0)
+#define ODM_ANTDIV_5G BIT(1)
+
+#define ANTDIV_ON 1
+#define ANTDIV_OFF 0
+
+#define FAT_ON 1
+#define FAT_OFF 0
+
+#define TX_BY_DESC 1
+#define TX_BY_REG 0
+
+#define RSSI_METHOD 0
+#define EVM_METHOD 1
+#define CRC32_METHOD 2
+
+#define INIT_ANTDIV_TIMMER 0
+#define CANCEL_ANTDIV_TIMMER 1
+#define RELEASE_ANTDIV_TIMMER 2
+
+#define CRC32_FAIL 1
+#define CRC32_OK 0
+
+#define evm_rssi_th_high 25
+#define evm_rssi_th_low 20
+
+#define NORMAL_STATE_MIAN 1
+#define NORMAL_STATE_AUX 2
+#define TRAINING_STATE 3
+
+#define FORCE_RSSI_DIFF 10
+
+#define CSI_ON 1
+#define CSI_OFF 0
+
+#define DIVON_CSIOFF 1
+#define DIVOFF_CSION 2
+
+#define BDC_DIV_TRAIN_STATE 0
+#define bdc_bfer_train_state 1
+#define BDC_DECISION_STATE 2
+#define BDC_BF_HOLD_STATE 3
+#define BDC_DIV_HOLD_STATE 4
+
+#define BDC_MODE_1 1
+#define BDC_MODE_2 2
+#define BDC_MODE_3 3
+#define BDC_MODE_4 4
+#define BDC_MODE_NULL 0xff
+
+/*SW S0S1 antenna diversity*/
+#define SWAW_STEP_INIT 0xff
+#define SWAW_STEP_PEEK 0
+#define SWAW_STEP_DETERMINE 1
+
+#define RSSI_CHECK_RESET_PERIOD 10
+#define RSSI_CHECK_THRESHOLD 50
+
+/*Hong Lin Smart antenna*/
+#define HL_SMTANT_2WIRE_DATA_LEN 24
+
+/* 1 ============================================================
+ * 1  structure
+ * 1 ============================================================
+ */
+
+struct sw_antenna_switch {
+	u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
+			     *than check this antenna again
+			     */
+	u8 try_flag;
+	s32 pre_rssi;
+	u8 cur_antenna;
+	u8 pre_antenna;
+	u8 rssi_trying;
+	u8 reset_idx;
+	u8 train_time;
+	u8 train_time_flag; /*base on RSSI difference between two antennas*/
+	struct timer_list phydm_sw_antenna_switch_timer;
+	u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
+	bool is_sw_ant_div_by_ctrl_frame;
+
+	/* AntDect (Before link Antenna Switch check) need to be moved*/
+	u16 single_ant_counter;
+	u16 dual_ant_counter;
+	u16 aux_fail_detec_counter;
+	u16 retry_counter;
+	u8 swas_no_link_state;
+	u32 swas_no_link_bk_reg948;
+	bool ANTA_ON; /*To indicate ant A is or not*/
+	bool ANTB_ON; /*To indicate ant B is on or not*/
+	bool pre_aux_fail_detec;
+	bool rssi_ant_dect_result;
+	u8 ant_5g;
+	u8 ant_2g;
+};
+
+struct fast_antenna_training {
+	u8 bssid[6];
+	u8 antsel_rx_keep_0;
+	u8 antsel_rx_keep_1;
+	u8 antsel_rx_keep_2;
+	u8 antsel_rx_keep_3;
+	u32 ant_sum_rssi[7];
+	u32 ant_rssi_cnt[7];
+	u32 ant_ave_rssi[7];
+	u8 fat_state;
+	u32 train_idx;
+	u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
+	u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
+	u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
+	u8 rx_idle_ant;
+	u8 ant_div_on_off;
+	bool is_become_linked;
+	u32 min_max_rssi;
+	u8 idx_ant_div_counter_2g;
+	u8 idx_ant_div_counter_5g;
+	u8 ant_div_2g_5g;
+
+	u32 cck_ctrl_frame_cnt_main;
+	u32 cck_ctrl_frame_cnt_aux;
+	u32 ofdm_ctrl_frame_cnt_main;
+	u32 ofdm_ctrl_frame_cnt_aux;
+	u32 main_ant_ctrl_frame_sum;
+	u32 aux_ant_ctrl_frame_sum;
+	u32 main_ant_ctrl_frame_cnt;
+	u32 aux_ant_ctrl_frame_cnt;
+	u8 b_fix_tx_ant;
+	bool fix_ant_bfee;
+	bool enable_ctrl_frame_antdiv;
+	bool use_ctrl_frame_antdiv;
+	u8 hw_antsw_occur;
+	u8 *p_force_tx_ant_by_desc;
+	u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
+				  *outer parameter later
+				  */
+	u8 *p_default_s0_s1;
+	u8 default_s0_s1;
+};
+
+/* 1 ============================================================
+ * 1  enumeration
+ * 1 ============================================================
+ */
+
+/*Fast antenna training*/
+enum fat_state {
+	FAT_BEFORE_LINK_STATE = 0,
+	FAT_PREPARE_STATE = 1,
+	FAT_TRAINING_STATE = 2,
+	FAT_DECISION_STATE = 3
+};
+
+enum ant_div_type {
+	NO_ANTDIV = 0xFF,
+	CG_TRX_HW_ANTDIV = 0x01,
+	CGCS_RX_HW_ANTDIV = 0x02,
+	FIXED_HW_ANTDIV = 0x03,
+	CG_TRX_SMART_ANTDIV = 0x04,
+	CGCS_RX_SW_ANTDIV = 0x05,
+	/*8723B intrnal switch S0 S1*/
+	S0S1_SW_ANTDIV = 0x06,
+	/*TRX S0S1 diversity for 8723D*/
+	S0S1_TRX_HW_ANTDIV = 0x07,
+	/*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
+	 *each ant. is equipped with 4 antenna patterns
+	 */
+	HL_SW_SMART_ANT_TYPE1 = 0x10,
+	/*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
+	HL_SW_SMART_ANT_TYPE2 = 0x11,
+};
+
+/* 1 ============================================================
+ * 1  function prototype
+ * 1 ============================================================
+ */
+
+void odm_stop_antenna_switch_dm(void *dm_void);
+
+void phydm_enable_antenna_diversity(void *dm_void);
+
+void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
+			);
+
+#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
+
+void odm_sw_ant_div_rest_after_link(void *dm_void);
+
+void odm_ant_div_reset(void *dm_void);
+
+void odm_antenna_diversity_init(void *dm_void);
+
+void odm_antenna_diversity(void *dm_void);
+
+#endif /*#ifndef	__ODMANTDIV_H__*/

drivers/staging/rtlwifi/phydm/phydm_beamforming.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __INC_PHYDM_BEAMFORMING_H
+#define __INC_PHYDM_BEAMFORMING_H
+
+/*Beamforming Related*/
+#include "txbf/halcomtxbf.h"
+#include "txbf/haltxbfjaguar.h"
+#include "txbf/haltxbf8822b.h"
+#include "txbf/haltxbfinterface.h"
+
+#define beamforming_gid_paid(adapter, tcb)
+#define phydm_acting_determine(dm, type) false
+#define beamforming_enter(dm, sta_idx)
+#define beamforming_leave(dm, RA)
+#define beamforming_end_fw(dm)
+#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
+#define beamforming_control_v2(dm, idx, mode, BW, period) true
+#define phydm_beamforming_end_sw(dm, _status)
+#define beamforming_timer_callback(dm)
+#define phydm_beamforming_init(dm)
+#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
+#define beamforming_watchdog(dm)
+#define phydm_beamforming_watchdog(dm)
+
+#endif

drivers/staging/rtlwifi/phydm/phydm_ccx.h

+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2016  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+#ifndef __PHYDMCCX_H__
+#define __PHYDMCCX_H__
+
+#define CCX_EN 1
+
+#define SET_NHM_SETTING 0
+#define STORE_NHM_SETTING 1
+#define RESTORE_NHM_SETTING 2
+
+enum nhm_inexclude_cca { NHM_EXCLUDE_CCA, NHM_INCLUDE_CCA };
+
+enum nhm_inexclude_txon { NHM_EXCLUDE_TXON, NHM_INCLUDE_TXON };
+
+struct ccx_info {
+	/*Settings*/
+	u8 NHM_th[11];
+	u16 NHM_period; /* 4us per unit */
+	u16 CLM_period; /* 4us per unit */
+	enum nhm_inexclude_txon nhm_inexclude_txon;
+	enum nhm_inexclude_cca nhm_inexclude_cca;
+
+	/*Previous Settings*/
+	u8 NHM_th_restore[11];
+	u16 NHM_period_restore; /* 4us per unit */
+	u16 CLM_period_restore; /* 4us per unit */
+	enum nhm_inexclude_txon NHM_inexclude_txon_restore;
+	enum nhm_inexclude_cca NHM_inexclude_cca_restore;
+
+	/*Report*/
+	u8 NHM_result[12];
+	u16 NHM_duration;
+	u16 CLM_result;
+
+	bool echo_NHM_en;
+	bool echo_CLM_en;
+	u8 echo_IGI;
+};
+
+/*NHM*/
+
+void phydm_nhm_setting(void *dm_void, u8 nhm_setting);
+
+void phydm_nhm_trigger(void *dm_void);
+
+void phydm_get_nhm_result(void *dm_void);
+
+bool phydm_check_nhm_ready(void *dm_void);
+
+/*CLM*/
+
+void phydm_clm_setting(void *dm_void);
+
+void phydm_clm_trigger(void *dm_void);
+
+bool phydm_check_cl_mready(void *dm_void);
+
+void phydm_get_cl_mresult(void *dm_void);
+
+#endif