提交 9b9d401b 编写于 作者: A Anton Vorontsov 提交者: Kumar Gala

powerpc/85xx: Add QE USB support for MPC8569E-MDS boards

- Add gpio-controller node for BCSR17, it is used to control USB
  speed and VBUS;
- Add timer node for QE GTM, needed for USB host;
- Add usb node itself;
- Add some probing code for BCSR GPIOs.

NOTE: QE USB doesn't work on prototype boards, but should work on
      pilot boards if specs and schematics are correct, though we
      don't have the pilot boards to actually test it.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
上级 818fcac5
...@@ -99,8 +99,18 @@ ...@@ -99,8 +99,18 @@
}; };
bcsr@1,0 { bcsr@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8569mds-bcsr"; compatible = "fsl,mpc8569mds-bcsr";
reg = <1 0 0x8000>; reg = <1 0 0x8000>;
ranges = <0 1 0 0x8000>;
bcsr17: gpio-controller@11 {
#gpio-cells = <2>;
compatible = "fsl,mpc8569mds-bcsr-gpio";
reg = <0x11 0x1>;
gpio-controller;
};
}; };
nand@3,0 { nand@3,0 {
...@@ -315,6 +325,14 @@ ...@@ -315,6 +325,14 @@
gpio-controller; gpio-controller;
}; };
qe_pio_f: gpio-controller@a0 {
#gpio-cells = <2>;
compatible = "fsl,mpc8569-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0xa0 0x18>;
gpio-controller;
};
pio1: ucc_pin@01 { pio1: ucc_pin@01 {
pio-map = < pio-map = <
/* port pin dir open_drain assignment has_irq */ /* port pin dir open_drain assignment has_irq */
...@@ -419,6 +437,16 @@ ...@@ -419,6 +437,16 @@
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
timer@440 {
compatible = "fsl,mpc8569-qe-gtm",
"fsl,qe-gtm", "fsl,gtm";
reg = <0x440 0x40>;
interrupts = <12 13 14 15>;
interrupt-parent = <&qeic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
spi@4c0 { spi@4c0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -446,6 +474,23 @@ ...@@ -446,6 +474,23 @@
mode = "cpu"; mode = "cpu";
}; };
usb@6c0 {
compatible = "fsl,mpc8569-qe-usb",
"fsl,mpc8323-qe-usb";
reg = <0x6c0 0x40 0x8b00 0x100>;
interrupts = <11>;
interrupt-parent = <&qeic>;
fsl,fullspeed-clock = "clk5";
fsl,lowspeed-clock = "brg10";
gpios = <&qe_pio_f 3 0 /* USBOE */
&qe_pio_f 4 0 /* USBTP */
&qe_pio_f 5 0 /* USBTN */
&qe_pio_f 6 0 /* USBRP */
&qe_pio_f 8 0 /* USBRN */
&bcsr17 6 0 /* SPEED */
&bcsr17 5 1>; /* POWER */
};
enet0: ucc@2000 { enet0: ucc@2000 {
device_type = "network"; device_type = "network";
compatible = "ucc_geth"; compatible = "ucc_geth";
......
...@@ -47,6 +47,7 @@ ...@@ -47,6 +47,7 @@
#include <asm/udbg.h> #include <asm/udbg.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h> #include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <asm/qe.h> #include <asm/qe.h>
#include <asm/qe_ic.h> #include <asm/qe_ic.h>
#include <asm/mpic.h> #include <asm/mpic.h>
...@@ -304,6 +305,9 @@ static struct of_device_id mpc85xx_ids[] = { ...@@ -304,6 +305,9 @@ static struct of_device_id mpc85xx_ids[] = {
static int __init mpc85xx_publish_devices(void) static int __init mpc85xx_publish_devices(void)
{ {
if (machine_is(mpc8569_mds))
simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
/* Publish the QE devices */ /* Publish the QE devices */
of_platform_bus_probe(NULL, mpc85xx_ids, NULL); of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
......
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