提交 9a21e55d 编写于 作者: D Dinh Nguyen

ARM: dts: socfpga: update L2 tag and data latency

Sets the appropriate L2-cache latencies for the SOCFPGA platform.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
上级 374b1057
......@@ -467,6 +467,8 @@
interrupts = <0 38 0x04>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <2 1 1>;
};
/* Local timer */
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册