drm/nve0/fb: note the memory voltage toggle, not using it yet

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c

@@ -101,8 +101,8 @@ nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts)
 
 	if (!(ram->mr[7] & 0x100))
 		vr = 0; /* binary driver does this.. bug? */
-	ram->mr[7] &= ~0x188;
-	ram->mr[7] |= (vr & 0x01) << 8;
+	ram->mr[7] &= ~0x388;
+	ram->mr[7] |= (vr & 0x03) << 8;
 	ram->mr[7] |= (vh & 0x01) << 7;
 	ram->mr[7] |= (lf & 0x01) << 3;
 

drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c

@@ -266,7 +266,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
 	const u32 ramcfg = ram->base.ramcfg.data;
 	const u32 timing = ram->base.timing.data;
 	int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08);
-	int mv = 1; /*XXX*/
+	int mv = 1; /*XXX: !(nv_ro08(bios, ramcfg + 0x02) & 0x04); */
 	u32 mask, data, i;
 
 	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
@@ -685,7 +685,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq)
 	const u32 ramcfg = ram->base.ramcfg.data;
 	const u32 timing = ram->base.timing.data;
 	int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08);
-	int mv = 1; /*XXX*/
+	int mv = 1; /*XXX: !(nv_ro08(bios, ramcfg + 0x02) & 0x04); */
 	u32 mask, data;
 
 	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);