MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.
This extends commit a8ca8b64 to cover MIPSxx-style board cache code. Signed-off-by: NKevin Cernekee <cernekee@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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