提交 9474980a 编写于 作者: Y Yongqiang Sun 提交者: Alex Deucher

drm/amd/display: Added timing sync trace.

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 5ea81b91
master alk-4.19.24 alk-4.19.30 alk-4.19.34 alk-4.19.36 alk-4.19.43 alk-4.19.48 alk-4.19.57 ck-4.19.67 ck-4.19.81 ck-4.19.91 github/fork/deepanshu1422/fix-typo-in-comment github/fork/haosdent/fix-typo linux-next v4.19.91 v4.19.90 v4.19.89 v4.19.88 v4.19.87 v4.19.86 v4.19.85 v4.19.84 v4.19.83 v4.19.82 v4.19.81 v4.19.80 v4.19.79 v4.19.78 v4.19.77 v4.19.76 v4.19.75 v4.19.74 v4.19.73 v4.19.72 v4.19.71 v4.19.70 v4.19.69 v4.19.68 v4.19.67 v4.19.66 v4.19.65 v4.19.64 v4.19.63 v4.19.62 v4.19.61 v4.19.60 v4.19.59 v4.19.58 v4.19.57 v4.19.56 v4.19.55 v4.19.54 v4.19.53 v4.19.52 v4.19.51 v4.19.50 v4.19.49 v4.19.48 v4.19.47 v4.19.46 v4.19.45 v4.19.44 v4.19.43 v4.19.42 v4.19.41 v4.19.40 v4.19.39 v4.19.38 v4.19.37 v4.19.36 v4.19.35 v4.19.34 v4.19.33 v4.19.32 v4.19.31 v4.19.30 v4.19.29 v4.19.28 v4.19.27 v4.19.26 v4.19.25 v4.19.24 v4.19.23 v4.19.22 v4.19.21 v4.19.20 v4.19.19 v4.19.18 v4.19.17 v4.19.16 v4.19.15 v4.19.14 v4.19.13 v4.19.12 v4.19.11 v4.19.10 v4.19.9 v4.19.8 v4.19.7 v4.19.6 v4.19.5 v4.19.4 v4.19.3 v4.19.2 v4.19.1 v4.19 v4.19-rc8 v4.19-rc7 v4.19-rc6 v4.19-rc5 v4.19-rc4 v4.19-rc3 v4.19-rc2 v4.19-rc1 ck-release-21 ck-release-20 ck-release-19.2 ck-release-19.1 ck-release-19 ck-release-18 ck-release-17.2 ck-release-17.1 ck-release-17 ck-release-16 ck-release-15.1 ck-release-15 ck-release-14 ck-release-13.2 ck-release-13 ck-release-12 ck-release-11 ck-release-10 ck-release-9 ck-release-7 alk-release-15 alk-release-14 alk-release-13.2 alk-release-13 alk-release-12 alk-release-11 alk-release-10 alk-release-9 alk-release-7
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......@@ -1488,8 +1488,10 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
core_dc->hwss.prepare_pipe_for_context(
core_dc, pipe_ctx, context);
}
if (apply_ctx)
if (apply_ctx) {
core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
context_timing_trace(dc, &context->res_ctx);
}
}
for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
......
......@@ -22,6 +22,13 @@
##__VA_ARGS__); \
} while (0)
#define TIMING_TRACE(...) do {\
if (dc->debug.timing_trace) \
dm_logger_write(logger, \
LOG_SYNC, \
##__VA_ARGS__); \
} while (0)
void pre_surface_trace(
const struct dc *dc,
const struct dc_surface *const *surfaces,
......@@ -268,3 +275,28 @@ void post_surface_trace(const struct dc *dc)
SURFACE_TRACE("post surface process.\n");
}
void context_timing_trace(
const struct dc *dc,
struct resource_context *res_ctx)
{
int i;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dal_logger *logger = core_dc->ctx->logger;
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
int h_pos = 0;
int v_pos = 0;
if (pipe_ctx->stream == NULL)
continue;
pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &h_pos, &v_pos);
TIMING_TRACE("Pipe_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
pipe_ctx->pipe_idx,
pipe_ctx->stream->public.timing.h_total,
pipe_ctx->stream->public.timing.v_total,
h_pos, v_pos);
}
}
......@@ -140,6 +140,7 @@ struct dc_debug {
bool max_disp_clk;
bool target_trace;
bool surface_trace;
bool timing_trace;
bool validation_trace;
bool disable_stutter;
bool disable_dcc;
......
......@@ -1892,7 +1892,6 @@ static void dce110_apply_ctx_for_surface(
program_blender(dc, pipe_ctx);
}
}
static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
......
......@@ -31,6 +31,7 @@
struct dc_context;
struct dc_link;
struct dc_surface_update;
struct resource_context;
/*
*
......@@ -85,6 +86,10 @@ void update_surface_trace(
void post_surface_trace(const struct dc *dc);
void context_timing_trace(
const struct dc *dc,
struct resource_context *res_ctx);
/* Any function which is empty or have incomplete implementation should be
* marked by this macro.
......
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