提交 8c7634c0 编写于 作者: P Peter Crosthwaite 提交者: Michal Simek

arm: dts: zynq: Move crystal freq. to board level

The fact that all supported boards use the same 33MHz crystal is a
co-incidence. The Zynq PS support a range of crystal freqs so the
hardcoded setting should be removed from the dtsi. Re-implement it
on the board level.

This prepares support for Zynq boards with different crystal
frequencies (e.g. the Digilent ZYBO).
Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
上级 d86e3104
...@@ -244,7 +244,6 @@ ...@@ -244,7 +244,6 @@
clkc: clkc@100 { clkc: clkc@100 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "xlnx,ps7-clkc"; compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
fclk-enable = <0>; fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
......
...@@ -34,6 +34,10 @@ ...@@ -34,6 +34,10 @@
}; };
}; };
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
......
...@@ -42,6 +42,10 @@ ...@@ -42,6 +42,10 @@
status = "okay"; status = "okay";
}; };
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
......
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
}; };
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
......
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
}; };
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
......
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