提交 8bac078c 编写于 作者: J Jaedon Shin 提交者: Ralf Baechle

MIPS: BMIPS: dts: Add uart device nodes to bcm7xxx platforms

Add two uart device nodes known as the uart1 and uart2 for the bcm7xxx
platforms.
Signed-off-by: NJaedon Shin <jaedon.shin@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9991/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 380e4270
...@@ -24,6 +24,8 @@ ...@@ -24,6 +24,8 @@
aliases { aliases {
uart0 = &uart0; uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
}; };
cpu_intc: cpu_intc { cpu_intc: cpu_intc {
...@@ -118,6 +120,30 @@ ...@@ -118,6 +120,30 @@
status = "disabled"; status = "disabled";
}; };
uart1: serial@406940 {
compatible = "ns16550a";
reg = <0x406940 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <65>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406980 {
compatible = "ns16550a";
reg = <0x406980 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <66>;
clocks = <&uart_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -18,6 +18,8 @@ ...@@ -18,6 +18,8 @@
aliases { aliases {
uart0 = &uart0; uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
}; };
cpu_intc: cpu_intc { cpu_intc: cpu_intc {
...@@ -112,6 +114,30 @@ ...@@ -112,6 +114,30 @@
status = "disabled"; status = "disabled";
}; };
uart1: serial@406840 {
compatible = "ns16550a";
reg = <0x406840 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <62>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406880 {
compatible = "ns16550a";
reg = <0x406880 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <63>;
clocks = <&uart_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -18,6 +18,8 @@ ...@@ -18,6 +18,8 @@
aliases { aliases {
uart0 = &uart0; uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
}; };
cpu_intc: cpu_intc { cpu_intc: cpu_intc {
...@@ -112,6 +114,30 @@ ...@@ -112,6 +114,30 @@
status = "disabled"; status = "disabled";
}; };
uart1: serial@406840 {
compatible = "ns16550a";
reg = <0x406840 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <62>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406880 {
compatible = "ns16550a";
reg = <0x406880 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <63>;
clocks = <&uart_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -24,6 +24,8 @@ ...@@ -24,6 +24,8 @@
aliases { aliases {
uart0 = &uart0; uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
}; };
cpu_intc: cpu_intc { cpu_intc: cpu_intc {
...@@ -118,6 +120,30 @@ ...@@ -118,6 +120,30 @@
status = "disabled"; status = "disabled";
}; };
uart1: serial@406840 {
compatible = "ns16550a";
reg = <0x406840 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <62>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406880 {
compatible = "ns16550a";
reg = <0x406880 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <63>;
clocks = <&uart_clk>;
status = "disabled";
};
enet0: ethernet@430000 { enet0: ethernet@430000 {
phy-mode = "internal"; phy-mode = "internal";
phy-handle = <&phy1>; phy-handle = <&phy1>;
......
...@@ -21,6 +21,14 @@ ...@@ -21,6 +21,14 @@
status = "okay"; status = "okay";
}; };
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -21,6 +21,14 @@ ...@@ -21,6 +21,14 @@
status = "okay"; status = "okay";
}; };
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -21,6 +21,14 @@ ...@@ -21,6 +21,14 @@
status = "okay"; status = "okay";
}; };
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
...@@ -21,6 +21,14 @@ ...@@ -21,6 +21,14 @@
status = "okay"; status = "okay";
}; };
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&enet0 { &enet0 {
status = "okay"; status = "okay";
}; };
......
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