提交 8737f818 编写于 作者: D Daniel Jurgens 提交者: Jason Gunthorpe

net/mlx5: Set software owner ID during init HCA

Generate a unique 128bit identifier for each host and pass that value to
firmware in the INIT_HCA command if it reports the sw_owner_id
capability. Each device bound to the mlx5_core driver will have the same
software owner ID.

In subsequent patches mlx5_core devices will be bound via a new VPort
command so that they can operate together under a single InfiniBand
device. Only devices that have the same software owner ID can be bound,
to prevent traffic intended for one host arriving at another.

The INIT_HCA command length was expanded by 128 bits. The command
length is provided as an input FW commands. Older FW does not have a
problem receiving this command in the new longer form.
Signed-off-by: NDaniel Jurgens <danielj@mellanox.com>
Reviewed-by: NParav Pandit <parav@mellanox.com>
Signed-off-by: NLeon Romanovsky <leon@kernel.org>
Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
上级 734dc065
...@@ -195,12 +195,20 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) ...@@ -195,12 +195,20 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
return 0; return 0;
} }
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev) int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
{ {
u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0}; u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0};
u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0}; u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0};
int i;
MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA); MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
if (MLX5_CAP_GEN(dev, sw_owner_id)) {
for (i = 0; i < 4; i++)
MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
sw_owner_id[i]);
}
return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
} }
......
...@@ -75,6 +75,8 @@ static unsigned int prof_sel = MLX5_DEFAULT_PROF; ...@@ -75,6 +75,8 @@ static unsigned int prof_sel = MLX5_DEFAULT_PROF;
module_param_named(prof_sel, prof_sel, uint, 0444); module_param_named(prof_sel, prof_sel, uint, 0444);
MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
static u32 sw_owner_id[4];
enum { enum {
MLX5_ATOMIC_REQ_MODE_BE = 0x0, MLX5_ATOMIC_REQ_MODE_BE = 0x0,
MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
...@@ -1055,7 +1057,7 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, ...@@ -1055,7 +1057,7 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
goto reclaim_boot_pages; goto reclaim_boot_pages;
} }
err = mlx5_cmd_init_hca(dev); err = mlx5_cmd_init_hca(dev, sw_owner_id);
if (err) { if (err) {
dev_err(&pdev->dev, "init hca failed\n"); dev_err(&pdev->dev, "init hca failed\n");
goto err_pagealloc_stop; goto err_pagealloc_stop;
...@@ -1577,6 +1579,8 @@ static int __init init(void) ...@@ -1577,6 +1579,8 @@ static int __init init(void)
{ {
int err; int err;
get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
mlx5_core_verify_params(); mlx5_core_verify_params();
mlx5_register_debugfs(); mlx5_register_debugfs();
......
...@@ -86,7 +86,7 @@ enum { ...@@ -86,7 +86,7 @@ enum {
int mlx5_query_hca_caps(struct mlx5_core_dev *dev); int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
int mlx5_query_board_id(struct mlx5_core_dev *dev); int mlx5_query_board_id(struct mlx5_core_dev *dev);
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev); int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev); int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev); int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
......
...@@ -79,6 +79,11 @@ ...@@ -79,6 +79,11 @@
<< __mlx5_dw_bit_off(typ, fld))); \ << __mlx5_dw_bit_off(typ, fld))); \
} while (0) } while (0)
#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
MLX5_SET(typ, p, fld[idx], v); \
} while (0)
#define MLX5_SET_TO_ONES(typ, p, fld) do { \ #define MLX5_SET_TO_ONES(typ, p, fld) do { \
BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
......
...@@ -1066,7 +1066,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -1066,7 +1066,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_5f8[0x3]; u8 reserved_at_5f8[0x3];
u8 log_max_xrq[0x5]; u8 log_max_xrq[0x5];
u8 reserved_at_600[0x200]; u8 reserved_at_600[0x1e];
u8 sw_owner_id;
u8 reserved_at_61f[0x1e1];
}; };
enum mlx5_flow_destination_type { enum mlx5_flow_destination_type {
...@@ -5531,6 +5533,7 @@ struct mlx5_ifc_init_hca_in_bits { ...@@ -5531,6 +5533,7 @@ struct mlx5_ifc_init_hca_in_bits {
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 reserved_at_40[0x40];
u8 sw_owner_id[4][0x20];
}; };
struct mlx5_ifc_init2rtr_qp_out_bits { struct mlx5_ifc_init2rtr_qp_out_bits {
......
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