drm/arm/hdlcd: Allow a bit of clock tolerance
[ Upstream commit 1c810739097fdeb31b393b67a0a1e3d7ffdd9f63 ] On the Arm Juno platform, the HDLCD pixel clock is constrained to 250KHz resolution in order to avoid the tiny System Control Processor spending aeons trying to calculate exact PLL coefficients. This means that modes like my oddball 1600x1200 with 130.89MHz clock get rejected since the rate cannot be matched exactly. In practice, though, this mode works quite happily with the clock at 131MHz, so let's relax the check to allow a little bit of slop. Signed-off-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NLiviu Dudau <liviu.dudau@arm.com> Signed-off-by: NSasha Levin <sashal@kernel.org>
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