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832ca2ac
编写于
11月 01, 2017
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau: pass handle of vmm object to channel allocation ioctls
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
3c502639
变更
17
隐藏空白更改
内联
并排
Showing
17 changed file
with
54 addition
and
41 deletion
+54
-41
drivers/gpu/drm/nouveau/include/nvif/cl506e.h
drivers/gpu/drm/nouveau/include/nvif/cl506e.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/cl506f.h
drivers/gpu/drm/nouveau/include/nvif/cl506f.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
+1
-1
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
+1
-1
drivers/gpu/drm/nouveau/nouveau_chan.c
drivers/gpu/drm/nouveau/nouveau_chan.c
+4
-3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
+7
-5
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
+5
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
+5
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
+2
-2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
+5
-3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
+8
-6
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c
+3
-3
未找到文件。
drivers/gpu/drm/nouveau/include/nvif/cl506e.h
浏览文件 @
832ca2ac
...
...
@@ -5,7 +5,7 @@ struct nv50_channel_dma_v0 {
__u8
version
;
__u8
chid
;
__u8
pad02
[
6
];
__u64
vm
;
__u64
vm
m
;
__u64
pushbuf
;
__u64
offset
;
};
...
...
drivers/gpu/drm/nouveau/include/nvif/cl506f.h
浏览文件 @
832ca2ac
...
...
@@ -8,6 +8,6 @@ struct nv50_channel_gpfifo_v0 {
__u32
ilength
;
__u64
ioffset
;
__u64
pushbuf
;
__u64
vm
;
__u64
vm
m
;
};
#endif
drivers/gpu/drm/nouveau/include/nvif/cl826e.h
浏览文件 @
832ca2ac
...
...
@@ -5,7 +5,7 @@ struct g82_channel_dma_v0 {
__u8
version
;
__u8
chid
;
__u8
pad02
[
6
];
__u64
vm
;
__u64
vm
m
;
__u64
pushbuf
;
__u64
offset
;
};
...
...
drivers/gpu/drm/nouveau/include/nvif/cl826f.h
浏览文件 @
832ca2ac
...
...
@@ -8,7 +8,7 @@ struct g82_channel_gpfifo_v0 {
__u32
ilength
;
__u64
ioffset
;
__u64
pushbuf
;
__u64
vm
;
__u64
vm
m
;
};
#define NV826F_V0_NTFY_NON_STALL_INTERRUPT 0x00
...
...
drivers/gpu/drm/nouveau/include/nvif/cl906f.h
浏览文件 @
832ca2ac
...
...
@@ -7,7 +7,7 @@ struct fermi_channel_gpfifo_v0 {
__u8
pad02
[
2
];
__u32
ilength
;
__u64
ioffset
;
__u64
vm
;
__u64
vm
m
;
};
#define NV906F_V0_NTFY_NON_STALL_INTERRUPT 0x00
...
...
drivers/gpu/drm/nouveau/include/nvif/cla06f.h
浏览文件 @
832ca2ac
...
...
@@ -22,7 +22,7 @@ struct kepler_channel_gpfifo_a_v0 {
__u32
engines
;
__u32
ilength
;
__u64
ioffset
;
__u64
vm
;
__u64
vm
m
;
};
#define NVA06F_V0_NTFY_NON_STALL_INTERRUPT 0x00
...
...
drivers/gpu/drm/nouveau/nouveau_chan.c
浏览文件 @
832ca2ac
...
...
@@ -205,6 +205,7 @@ static int
nouveau_channel_ind
(
struct
nouveau_drm
*
drm
,
struct
nvif_device
*
device
,
u32
engine
,
struct
nouveau_channel
**
pchan
)
{
struct
nouveau_cli
*
cli
=
(
void
*
)
device
->
object
.
client
;
static
const
u16
oclasses
[]
=
{
PASCAL_CHANNEL_GPFIFO_A
,
MAXWELL_CHANNEL_GPFIFO_A
,
KEPLER_CHANNEL_GPFIFO_B
,
...
...
@@ -236,21 +237,21 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
args
.
kepler
.
engines
=
engine
;
args
.
kepler
.
ilength
=
0x02000
;
args
.
kepler
.
ioffset
=
0x10000
+
chan
->
push
.
addr
;
args
.
kepler
.
vm
=
0
;
args
.
kepler
.
vm
m
=
nvif_handle
(
&
cli
->
vmm
.
vmm
.
object
)
;
size
=
sizeof
(
args
.
kepler
);
}
else
if
(
oclass
[
0
]
>=
FERMI_CHANNEL_GPFIFO
)
{
args
.
fermi
.
version
=
0
;
args
.
fermi
.
ilength
=
0x02000
;
args
.
fermi
.
ioffset
=
0x10000
+
chan
->
push
.
addr
;
args
.
fermi
.
vm
=
0
;
args
.
fermi
.
vm
m
=
nvif_handle
(
&
cli
->
vmm
.
vmm
.
object
)
;
size
=
sizeof
(
args
.
fermi
);
}
else
{
args
.
nv50
.
version
=
0
;
args
.
nv50
.
ilength
=
0x02000
;
args
.
nv50
.
ioffset
=
0x10000
+
chan
->
push
.
addr
;
args
.
nv50
.
pushbuf
=
nvif_handle
(
&
chan
->
push
.
ctxdma
);
args
.
nv50
.
vm
=
0
;
args
.
nv50
.
vm
m
=
nvif_handle
(
&
cli
->
vmm
.
vmm
.
object
)
;
size
=
sizeof
(
args
.
nv50
);
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
浏览文件 @
832ca2ac
...
...
@@ -27,7 +27,6 @@
#include <core/gpuobj.h>
#include <core/oproxy.h>
#include <subdev/mmu.h>
#include <subdev/mmu/priv.h>
#include <engine/dma.h>
struct
nvkm_fifo_chan_object
{
...
...
@@ -353,8 +352,8 @@ nvkm_fifo_chan_func = {
int
nvkm_fifo_chan_ctor
(
const
struct
nvkm_fifo_chan_func
*
func
,
struct
nvkm_fifo
*
fifo
,
u32
size
,
u32
align
,
bool
zero
,
u64
vm
,
u64
push
,
u64
engines
,
int
bar
,
u32
base
,
u32
user
,
const
struct
nvkm_oclass
*
oclass
,
u64
hvmm
,
u64
push
,
u64
engines
,
int
bar
,
u32
base
,
u32
user
,
const
struct
nvkm_oclass
*
oclass
,
struct
nvkm_fifo_chan
*
chan
)
{
struct
nvkm_client
*
client
=
oclass
->
client
;
...
...
@@ -387,8 +386,11 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func,
}
/* channel address space */
if
(
!
device
->
mmu
->
func
->
vmm
.
global
)
{
struct
nvkm_vmm
*
vmm
=
client
->
vm
;
if
(
hvmm
)
{
struct
nvkm_vmm
*
vmm
=
nvkm_uvmm_search
(
client
,
hvmm
);
if
(
IS_ERR
(
vmm
))
return
PTR_ERR
(
vmm
);
if
(
vmm
->
mmu
!=
device
->
mmu
)
return
-
EINVAL
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
浏览文件 @
832ca2ac
...
...
@@ -229,15 +229,18 @@ g84_fifo_chan_func = {
};
int
g84_fifo_chan_ctor
(
struct
nv50_fifo
*
fifo
,
u64
vm
,
u64
push
,
g84_fifo_chan_ctor
(
struct
nv50_fifo
*
fifo
,
u64
vm
m
,
u64
push
,
const
struct
nvkm_oclass
*
oclass
,
struct
nv50_fifo_chan
*
chan
)
{
struct
nvkm_device
*
device
=
fifo
->
base
.
engine
.
subdev
.
device
;
int
ret
;
if
(
!
vmm
)
return
-
EINVAL
;
ret
=
nvkm_fifo_chan_ctor
(
&
g84_fifo_chan_func
,
&
fifo
->
base
,
0x10000
,
0x1000
,
false
,
vm
,
push
,
0x10000
,
0x1000
,
false
,
vm
m
,
push
,
(
1ULL
<<
NVKM_ENGINE_BSP
)
|
(
1ULL
<<
NVKM_ENGINE_CE0
)
|
(
1ULL
<<
NVKM_ENGINE_CIPHER
)
|
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
浏览文件 @
832ca2ac
...
...
@@ -228,15 +228,18 @@ nv50_fifo_chan_func = {
};
int
nv50_fifo_chan_ctor
(
struct
nv50_fifo
*
fifo
,
u64
vm
,
u64
push
,
nv50_fifo_chan_ctor
(
struct
nv50_fifo
*
fifo
,
u64
vm
m
,
u64
push
,
const
struct
nvkm_oclass
*
oclass
,
struct
nv50_fifo_chan
*
chan
)
{
struct
nvkm_device
*
device
=
fifo
->
base
.
engine
.
subdev
.
device
;
int
ret
;
if
(
!
vmm
)
return
-
EINVAL
;
ret
=
nvkm_fifo_chan_ctor
(
&
nv50_fifo_chan_func
,
&
fifo
->
base
,
0x10000
,
0x1000
,
false
,
vm
,
push
,
0x10000
,
0x1000
,
false
,
vm
m
,
push
,
(
1ULL
<<
NVKM_ENGINE_DMAOBJ
)
|
(
1ULL
<<
NVKM_ENGINE_SW
)
|
(
1ULL
<<
NVKM_ENGINE_GR
)
|
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
浏览文件 @
832ca2ac
...
...
@@ -17,14 +17,14 @@ struct nv50_fifo_chan {
struct
nvkm_gpuobj
*
engn
[
NVKM_SUBDEV_NR
];
};
int
nv50_fifo_chan_ctor
(
struct
nv50_fifo
*
,
u64
vm
,
u64
push
,
int
nv50_fifo_chan_ctor
(
struct
nv50_fifo
*
,
u64
vm
m
,
u64
push
,
const
struct
nvkm_oclass
*
,
struct
nv50_fifo_chan
*
);
void
*
nv50_fifo_chan_dtor
(
struct
nvkm_fifo_chan
*
);
void
nv50_fifo_chan_fini
(
struct
nvkm_fifo_chan
*
);
void
nv50_fifo_chan_engine_dtor
(
struct
nvkm_fifo_chan
*
,
struct
nvkm_engine
*
);
void
nv50_fifo_chan_object_dtor
(
struct
nvkm_fifo_chan
*
,
int
);
int
g84_fifo_chan_ctor
(
struct
nv50_fifo
*
,
u64
vm
,
u64
push
,
int
g84_fifo_chan_ctor
(
struct
nv50_fifo
*
,
u64
vm
m
,
u64
push
,
const
struct
nvkm_oclass
*
,
struct
nv50_fifo_chan
*
);
extern
const
struct
nvkm_fifo_chan_oclass
nv50_fifo_dma_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
浏览文件 @
832ca2ac
...
...
@@ -44,9 +44,9 @@ g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl
(
parent
,
"create channel dma size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
false
)))
{
nvif_ioctl
(
parent
,
"create channel dma vers %d vm %llx "
nvif_ioctl
(
parent
,
"create channel dma vers %d vm
m
%llx "
"pushbuf %llx offset %016llx
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
args
->
v0
.
version
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
args
->
v0
.
offset
);
if
(
!
args
->
v0
.
pushbuf
)
return
-
EINVAL
;
...
...
@@ -57,7 +57,7 @@ g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return
-
ENOMEM
;
*
pobject
=
&
chan
->
base
.
object
;
ret
=
g84_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
ret
=
g84_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
oclass
,
chan
);
if
(
ret
)
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
浏览文件 @
832ca2ac
...
...
@@ -44,9 +44,9 @@ nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl
(
parent
,
"create channel dma size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
false
)))
{
nvif_ioctl
(
parent
,
"create channel dma vers %d vm %llx "
nvif_ioctl
(
parent
,
"create channel dma vers %d vm
m
%llx "
"pushbuf %llx offset %016llx
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
args
->
v0
.
version
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
args
->
v0
.
offset
);
if
(
!
args
->
v0
.
pushbuf
)
return
-
EINVAL
;
...
...
@@ -57,7 +57,7 @@ nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return
-
ENOMEM
;
*
pobject
=
&
chan
->
base
.
object
;
ret
=
nv50_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
ret
=
nv50_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
oclass
,
chan
);
if
(
ret
)
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c
浏览文件 @
832ca2ac
...
...
@@ -45,10 +45,10 @@ g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl
(
parent
,
"create channel gpfifo size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
false
)))
{
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm %llx "
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm
m
%llx "
"pushbuf %llx ioffset %016llx "
"ilength %08x
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
args
->
v0
.
version
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
args
->
v0
.
ioffset
,
args
->
v0
.
ilength
);
if
(
!
args
->
v0
.
pushbuf
)
return
-
EINVAL
;
...
...
@@ -59,7 +59,7 @@ g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return
-
ENOMEM
;
*
pobject
=
&
chan
->
base
.
object
;
ret
=
g84_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
ret
=
g84_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
oclass
,
chan
);
if
(
ret
)
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
浏览文件 @
832ca2ac
...
...
@@ -225,10 +225,12 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl
(
parent
,
"create channel gpfifo size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
false
)))
{
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm %llx "
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm
m
%llx "
"ioffset %016llx ilength %08x
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
vm
,
args
->
v0
.
ioffset
,
args
->
v0
.
version
,
args
->
v0
.
vm
m
,
args
->
v0
.
ioffset
,
args
->
v0
.
ilength
);
if
(
!
args
->
v0
.
vmm
)
return
-
EINVAL
;
}
else
return
ret
;
...
...
@@ -240,7 +242,7 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
INIT_LIST_HEAD
(
&
chan
->
head
);
ret
=
nvkm_fifo_chan_ctor
(
&
gf100_fifo_gpfifo_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
true
,
args
->
v0
.
vm
,
0
,
0x1000
,
0x1000
,
true
,
args
->
v0
.
vm
m
,
0
,
(
1ULL
<<
NVKM_ENGINE_CE0
)
|
(
1ULL
<<
NVKM_ENGINE_CE1
)
|
(
1ULL
<<
NVKM_ENGINE_GR
)
|
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
浏览文件 @
832ca2ac
...
...
@@ -231,7 +231,7 @@ struct gk104_fifo_chan_func {
static
int
gk104_fifo_gpfifo_new_
(
const
struct
gk104_fifo_chan_func
*
func
,
struct
gk104_fifo
*
fifo
,
u32
*
engmask
,
u16
*
chid
,
u64
vm
,
u64
ioffset
,
u64
ilength
,
u64
vm
m
,
u64
ioffset
,
u64
ilength
,
const
struct
nvkm_oclass
*
oclass
,
struct
nvkm_object
**
pobject
)
{
...
...
@@ -241,6 +241,9 @@ gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
u64
subdevs
=
0
;
u64
usermem
;
if
(
!
vmm
)
return
-
EINVAL
;
/* Determine which downstream engines are present */
for
(
i
=
0
;
i
<
fifo
->
engine_nr
;
i
++
)
{
struct
nvkm_engine
*
engine
=
fifo
->
engine
[
i
].
engine
;
...
...
@@ -286,7 +289,7 @@ gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
INIT_LIST_HEAD
(
&
chan
->
head
);
ret
=
nvkm_fifo_chan_ctor
(
&
gk104_fifo_gpfifo_func
,
&
fifo
->
base
,
0x1000
,
0x1000
,
true
,
vm
,
0
,
subdevs
,
0x1000
,
0x1000
,
true
,
vm
m
,
0
,
subdevs
,
1
,
fifo
->
user
.
bar
->
addr
,
0x200
,
oclass
,
&
chan
->
base
);
if
(
ret
)
...
...
@@ -358,18 +361,17 @@ gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl
(
parent
,
"create channel gpfifo size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
false
)))
{
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm %llx "
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm
m
%llx "
"ioffset %016llx ilength %08x engine %08x
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
vm
,
args
->
v0
.
ioffset
,
args
->
v0
.
version
,
args
->
v0
.
vm
m
,
args
->
v0
.
ioffset
,
args
->
v0
.
ilength
,
args
->
v0
.
engines
);
return
gk104_fifo_gpfifo_new_
(
gk104_fifo_gpfifo
,
fifo
,
&
args
->
v0
.
engines
,
&
args
->
v0
.
chid
,
args
->
v0
.
vm
,
args
->
v0
.
vm
m
,
args
->
v0
.
ioffset
,
args
->
v0
.
ilength
,
oclass
,
pobject
);
}
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c
浏览文件 @
832ca2ac
...
...
@@ -45,10 +45,10 @@ nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
nvif_ioctl
(
parent
,
"create channel gpfifo size %d
\n
"
,
size
);
if
(
!
(
ret
=
nvif_unpack
(
ret
,
&
data
,
&
size
,
args
->
v0
,
0
,
0
,
false
)))
{
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm %llx "
nvif_ioctl
(
parent
,
"create channel gpfifo vers %d vm
m
%llx "
"pushbuf %llx ioffset %016llx "
"ilength %08x
\n
"
,
args
->
v0
.
version
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
args
->
v0
.
version
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
args
->
v0
.
ioffset
,
args
->
v0
.
ilength
);
if
(
!
args
->
v0
.
pushbuf
)
return
-
EINVAL
;
...
...
@@ -59,7 +59,7 @@ nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
return
-
ENOMEM
;
*
pobject
=
&
chan
->
base
.
object
;
ret
=
nv50_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
,
args
->
v0
.
pushbuf
,
ret
=
nv50_fifo_chan_ctor
(
fifo
,
args
->
v0
.
vm
m
,
args
->
v0
.
pushbuf
,
oclass
,
chan
);
if
(
ret
)
return
ret
;
...
...
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