davinci_mdio: Correct bitmask for clock divider value

The CLKDIV bitfield in the MDIO Control Register is a 16 bit field,
therefore the CLKDIV value may range from 0 to 0xffff.
Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

drivers/net/ethernet/ti/davinci_mdio.c

@@ -53,7 +53,7 @@ struct davinci_mdio_regs {
 	u32	control;
 #define CONTROL_IDLE		BIT(31)
 #define CONTROL_ENABLE		BIT(30)
-#define CONTROL_MAX_DIV		(0xff)
+#define CONTROL_MAX_DIV		(0xffff)
 
 	u32	alive;
 	u32	link;