[media] v4l: of: Correct pclk-sample for BT656 bus
Current v4l2_of_parse_parallel_bus function attempts to parse the DT properties for the parallel bus as well as BT656 bus. If the pclk-sample property is defined for the BT656 bus, it is still marked as a parallel bus. Fix this by parsing the pclk after the bus_type is selected. Only when hsync or vsync properties are specified, the bus_type should be set to V4L2_MBUS_PARALLEL. Signed-off-by: NNikhil Devshatwar <nikhil.nd@ti.com> Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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