drm/amd/display: fix dc_post_update_surfaces_to_stream

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc.c

@@ -953,15 +953,6 @@ bool dc_commit_streams(
 	return (result == DC_OK);
 }
 
-bool dc_pre_update_surfaces_to_stream(
-		struct dc *dc,
-		const struct dc_surface *const *new_surfaces,
-		uint8_t new_surface_count,
-		const struct dc_stream *dc_stream)
-{
-	return true;
-}
-
 bool dc_post_update_surfaces_to_stream(struct dc *dc)
 {
 	int i;
@@ -971,14 +962,19 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 	post_surface_trace(dc);
 
 	for (i = 0; i < core_dc->res_pool->pipe_count; i++)
-		if (context->res_ctx.pipe_ctx[i].stream == NULL) {
+		if (context->res_ctx.pipe_ctx[i].stream == NULL
+				|| context->res_ctx.pipe_ctx[i].surface == NULL) {
 			context->res_ctx.pipe_ctx[i].pipe_idx = i;
 			core_dc->hwss.power_down_front_end(
 					core_dc, &context->res_ctx.pipe_ctx[i]);
 		}
 
+	/* 3rd param should be true, temp w/a for RV*/
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+	core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);
+#else
 	core_dc->hwss.set_bandwidth(core_dc, context, true);
-
+#endif
 	return true;
 }
 
@@ -1262,17 +1258,12 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 
 		if (stream_update->out_transfer_func &&
 				stream_update->out_transfer_func !=
-				dc_stream->out_transfer_func) {
-			if (stream_update->out_transfer_func->type !=
-					TF_TYPE_UNKNOWN) {
-				if (dc_stream->out_transfer_func != NULL)
-					dc_transfer_func_release
-					(dc_stream->out_transfer_func);
-				dc_transfer_func_retain(stream_update->
-					out_transfer_func);
-				stream->public.out_transfer_func =
-					stream_update->out_transfer_func;
-			}
+						dc_stream->out_transfer_func) {
+			if (dc_stream->out_transfer_func != NULL)
+				dc_transfer_func_release(dc_stream->out_transfer_func);
+			dc_transfer_func_retain(stream_update->out_transfer_func);
+			stream->public.out_transfer_func =
+				stream_update->out_transfer_func;
 		}
 	}
 

drivers/gpu/drm/amd/display/dc/dc.h

@@ -262,8 +262,7 @@ struct dc_hdr_static_metadata {
 enum dc_transfer_func_type {
 	TF_TYPE_PREDEFINED,
 	TF_TYPE_DISTRIBUTED_POINTS,
-	TF_TYPE_BYPASS,
-	TF_TYPE_UNKNOWN
+	TF_TYPE_BYPASS
 };
 
 struct dc_transfer_func_distributed_points {
@@ -411,12 +410,6 @@ bool dc_commit_surfaces_to_stream(
 		uint8_t surface_count,
 		const struct dc_stream *stream);
 
-bool dc_pre_update_surfaces_to_stream(
-		struct dc *dc,
-		const struct dc_surface *const *new_surfaces,
-		uint8_t new_surface_count,
-		const struct dc_stream *stream);
-
 bool dc_post_update_surfaces_to_stream(
 		struct dc *dc);
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

@@ -2538,17 +2538,12 @@ static void dce110_apply_ctx_for_surface(
 
 static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
 {
-	int i;
-
-	for (i = 0; i < dc->res_pool->pipe_count; i++)
-		if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe)
-			break;
-
-	if (i == dc->res_pool->pipe_count)
+	/* Do not power down fe when stream is active on dce*/
+	if (pipe->stream)
 		return;
 
 	dc->hwss.enable_display_power_gating(
-		dc, i, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
+		dc, pipe->pipe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
 	if (pipe->xfm)
 		pipe->xfm->funcs->transform_reset(pipe->xfm);
 	memset(&pipe->scl_data, 0, sizeof(struct scaler_data));