提交 782e85c5 编写于 作者: S Sergei Shtylyov 提交者: David S. Miller

sh_eth: fix *enum* {A|M}PR_BIT

The *enum* {A|M}PR_BIT were declared in the commit 86a74ff2 ("net:
sh_eth: add support for  Renesas SuperH Ethernet") adding SH771x support,
however the SH771x manual  doesn't have the APR/MPR registers described
and the code writing to them for SH7710 was later removed by the commit
380af9e3 ("net: sh_eth: CPU dependency code collect to "struct
sh_eth_cpu_data""). All the newer SoC manuals have these registers
documented as having a 16-bit TIME parameter of the PAUSE frame, not
1-bit -- update the *enum* accordingly, fixing up the APR/MPR writes...
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
上级 5092ad4d
......@@ -1521,9 +1521,9 @@ static int sh_eth_dev_init(struct net_device *ndev)
/* mask reset */
if (mdp->cd->apr)
sh_eth_write(ndev, APR_AP, APR);
sh_eth_write(ndev, 1, APR);
if (mdp->cd->mpr)
sh_eth_write(ndev, MPR_MP, MPR);
sh_eth_write(ndev, 1, MPR);
if (mdp->cd->tpauser)
sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
......
......@@ -383,12 +383,12 @@ enum ECSIPR_STATUS_MASK_BIT {
/* APR */
enum APR_BIT {
APR_AP = 0x00000001,
APR_AP = 0x0000ffff,
};
/* MPR */
enum MPR_BIT {
MPR_MP = 0x00000001,
MPR_MP = 0x0000ffff,
};
/* TRSCER */
......
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