提交 778307d3 编写于 作者: M Mike Frysinger 提交者: Bryan Wu

Blackfin arch: remove support for Anomaly 05000125 as it doesnt exist on any...

Blackfin arch: remove support for Anomaly 05000125 as it doesnt exist on any supported processor/silicon
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>
上级 d6a29891
master alk-4.19.24 alk-4.19.30 alk-4.19.34 alk-4.19.36 alk-4.19.43 alk-4.19.48 alk-4.19.57 ck-4.19.67 ck-4.19.81 ck-4.19.91 github/fork/deepanshu1422/fix-typo-in-comment github/fork/haosdent/fix-typo linux-next v4.19.91 v4.19.90 v4.19.89 v4.19.88 v4.19.87 v4.19.86 v4.19.85 v4.19.84 v4.19.83 v4.19.82 v4.19.81 v4.19.80 v4.19.79 v4.19.78 v4.19.77 v4.19.76 v4.19.75 v4.19.74 v4.19.73 v4.19.72 v4.19.71 v4.19.70 v4.19.69 v4.19.68 v4.19.67 v4.19.66 v4.19.65 v4.19.64 v4.19.63 v4.19.62 v4.19.61 v4.19.60 v4.19.59 v4.19.58 v4.19.57 v4.19.56 v4.19.55 v4.19.54 v4.19.53 v4.19.52 v4.19.51 v4.19.50 v4.19.49 v4.19.48 v4.19.47 v4.19.46 v4.19.45 v4.19.44 v4.19.43 v4.19.42 v4.19.41 v4.19.40 v4.19.39 v4.19.38 v4.19.37 v4.19.36 v4.19.35 v4.19.34 v4.19.33 v4.19.32 v4.19.31 v4.19.30 v4.19.29 v4.19.28 v4.19.27 v4.19.26 v4.19.25 v4.19.24 v4.19.23 v4.19.22 v4.19.21 v4.19.20 v4.19.19 v4.19.18 v4.19.17 v4.19.16 v4.19.15 v4.19.14 v4.19.13 v4.19.12 v4.19.11 v4.19.10 v4.19.9 v4.19.8 v4.19.7 v4.19.6 v4.19.5 v4.19.4 v4.19.3 v4.19.2 v4.19.1 v4.19 v4.19-rc8 v4.19-rc7 v4.19-rc6 v4.19-rc5 v4.19-rc4 v4.19-rc3 v4.19-rc2 v4.19-rc1 ck-release-21 ck-release-20 ck-release-19.2 ck-release-19.1 ck-release-19 ck-release-18 ck-release-17.2 ck-release-17.1 ck-release-17 ck-release-16 ck-release-15.1 ck-release-15 ck-release-14 ck-release-13.2 ck-release-13 ck-release-12 ck-release-11 ck-release-10 ck-release-9 ck-release-7 alk-release-15 alk-release-14 alk-release-13.2 alk-release-13 alk-release-12 alk-release-11 alk-release-10 alk-release-9 alk-release-7
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......@@ -105,17 +105,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Turn off the dcache */
p0.l = LO(DMEM_CONTROL);
......@@ -123,18 +114,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
#if defined(CONFIG_BF527)
p0.h = hi(EMAC_SYSTAT);
......
......@@ -116,17 +116,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Turn off the dcache */
p0.l = LO(DMEM_CONTROL);
......@@ -134,17 +125,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
......
......@@ -105,17 +105,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Turn off the dcache */
p0.l = LO(DMEM_CONTROL);
......@@ -123,48 +114,20 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Initialise General-Purpose I/O Modules on BF537 */
/* Rev 0.0 Anomaly 05000212 - PORTx_FER,
* PORT_MUX Registers Do Not accept "writes" correctly:
*/
p0.h = hi(BFIN_PORT_MUX);
p0.l = lo(BFIN_PORT_MUX);
#if ANOMALY_05000212
R0.L = W[P0]; /* Read */
SSYNC;
#endif
R0 = (PGDE_UART | PFTE_UART)(Z);
#if ANOMALY_05000212
W[P0] = R0.L; /* Write */
SSYNC;
#endif
W[P0] = R0.L; /* Enable both UARTS */
SSYNC;
/* Enable peripheral function of PORTF for UART0 and UART1 */
p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
#if ANOMALY_05000212
R0.L = W[P0]; /* Read */
SSYNC;
#endif
R0 = 0x000F(Z);
#if ANOMALY_05000212
W[P0] = R0.L; /* Write */
SSYNC;
#endif
/* Enable peripheral function of PORTF for UART0 and UART1 */
W[P0] = R0.L;
SSYNC;
......
......@@ -105,16 +105,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Turn off the dcache */
p0.l = LO(DMEM_CONTROL);
......@@ -122,17 +114,8 @@ ENTRY(__start)
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
#if ANOMALY_05000125
STI R2;
#endif
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
......
......@@ -3,7 +3,7 @@
#
obj-y := \
cache.o cacheinit.o entry.o \
cache.o entry.o \
interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
obj-$(CONFIG_PM) += pm.o dpmc_modes.o
......
/*
* File: arch/blackfin/mach-common/cacheinit.S
* Based on:
* Author: LG Soft India
*
* Created: ?
* Description: cache initialization
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This function sets up the data and instruction cache. The
* tables like icplb table, dcplb table and Page Descriptor table
* are defined in cplbtab.h. You can configure those tables for
* your suitable requirements
*/
#include <linux/linkage.h>
#include <asm/blackfin.h>
.text
#if ANOMALY_05000125
#if defined(CONFIG_BFIN_ICACHE)
ENTRY(_bfin_write_IMEM_CONTROL)
/* Enable Instruction Cache */
P0.l = LO(IMEM_CONTROL);
P0.h = HI(IMEM_CONTROL);
/* Anomaly 05000125 */
CLI R1;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P0] = R0;
SSYNC;
STI R1;
RTS;
ENDPROC(_bfin_write_IMEM_CONTROL)
#endif
#if defined(CONFIG_BFIN_DCACHE)
ENTRY(_bfin_write_DMEM_CONTROL)
P0.l = LO(DMEM_CONTROL);
P0.h = HI(DMEM_CONTROL);
CLI R1;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8;
[P0] = R0;
SSYNC;
STI R1;
RTS;
ENDPROC(_bfin_write_DMEM_CONTROL)
#endif
#endif
......@@ -39,11 +39,7 @@
#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
#if ANOMALY_05000125
extern void bfin_write_DMEM_CONTROL(unsigned int val);
#else
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
#endif
#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
......@@ -129,11 +125,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val);
#define DTEST_DATA3 0xFFE0040C
*/
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
#if ANOMALY_05000125
extern void bfin_write_IMEM_CONTROL(unsigned int val);
#else
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
#endif
#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
......
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