提交 766e3721 编写于 作者: S Scott Jiang 提交者: Mark Brown

spi: convert spi-bfin-v3.c to a multiplatform driver

Spi v3 controller is not only used on Blackfin. So rename it
and use ioread/iowrite api to make it work on other platform.
Signed-off-by: NScott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: NMark Brown <broonie@linaro.org>
上级 c9eaa447
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
#include <linux/pinctrl/machine.h> #include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_data/pinctrl-adi2.h> #include <linux/platform_data/pinctrl-adi2.h>
#include <asm/bfin_spi3.h> #include <linux/spi/adi_spi3.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/nand.h> #include <asm/nand.h>
...@@ -767,13 +767,13 @@ static struct flash_platform_data bfin_spi_flash_data = { ...@@ -767,13 +767,13 @@ static struct flash_platform_data bfin_spi_flash_data = {
.type = "w25q32", .type = "w25q32",
}; };
static struct bfin_spi3_chip spi_flash_chip_info = { static struct adi_spi3_chip spi_flash_chip_info = {
.enable_dma = true, /* use dma transfer with this chip*/ .enable_dma = true, /* use dma transfer with this chip*/
}; };
#endif #endif
#if IS_ENABLED(CONFIG_SPI_SPIDEV) #if IS_ENABLED(CONFIG_SPI_SPIDEV)
static struct bfin_spi3_chip spidev_chip_info = { static struct adi_spi3_chip spidev_chip_info = {
.enable_dma = true, .enable_dma = true,
}; };
#endif #endif
...@@ -1736,7 +1736,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -1736,7 +1736,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
}, },
#endif #endif
}; };
#if IS_ENABLED(CONFIG_SPI_BFIN_V3) #if IS_ENABLED(CONFIG_SPI_ADI_V3)
/* SPI (0) */ /* SPI (0) */
static struct resource bfin_spi0_resource[] = { static struct resource bfin_spi0_resource[] = {
{ {
...@@ -1777,13 +1777,13 @@ static struct resource bfin_spi1_resource[] = { ...@@ -1777,13 +1777,13 @@ static struct resource bfin_spi1_resource[] = {
}; };
/* SPI controller data */ /* SPI controller data */
static struct bfin_spi3_master bf60x_spi_master_info0 = { static struct adi_spi3_master bf60x_spi_master_info0 = {
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
}; };
static struct platform_device bf60x_spi_master0 = { static struct platform_device bf60x_spi_master0 = {
.name = "bfin-spi3", .name = "adi-spi3",
.id = 0, /* Bus number */ .id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource), .num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource, .resource = bfin_spi0_resource,
...@@ -1792,13 +1792,13 @@ static struct platform_device bf60x_spi_master0 = { ...@@ -1792,13 +1792,13 @@ static struct platform_device bf60x_spi_master0 = {
}, },
}; };
static struct bfin_spi3_master bf60x_spi_master_info1 = { static struct adi_spi3_master bf60x_spi_master_info1 = {
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
}; };
static struct platform_device bf60x_spi_master1 = { static struct platform_device bf60x_spi_master1 = {
.name = "bfin-spi3", .name = "adi-spi3",
.id = 1, /* Bus number */ .id = 1, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi1_resource), .num_resources = ARRAY_SIZE(bfin_spi1_resource),
.resource = bfin_spi1_resource, .resource = bfin_spi1_resource,
...@@ -1990,7 +1990,7 @@ static struct platform_device *ezkit_devices[] __initdata = { ...@@ -1990,7 +1990,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
&bfin_sdh_device, &bfin_sdh_device,
#endif #endif
#if IS_ENABLED(CONFIG_SPI_BFIN_V3) #if IS_ENABLED(CONFIG_SPI_ADI_V3)
&bf60x_spi_master0, &bf60x_spi_master0,
&bf60x_spi_master1, &bf60x_spi_master1,
#endif #endif
...@@ -2051,8 +2051,8 @@ static struct pinctrl_map __initdata bfin_pinmux_map[] = { ...@@ -2051,8 +2051,8 @@ static struct pinctrl_map __initdata bfin_pinmux_map[] = {
PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"), PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"), PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"), PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
......
...@@ -91,8 +91,8 @@ config SPI_BFIN5XX ...@@ -91,8 +91,8 @@ config SPI_BFIN5XX
help help
This is the SPI controller master driver for Blackfin 5xx processor. This is the SPI controller master driver for Blackfin 5xx processor.
config SPI_BFIN_V3 config SPI_ADI_V3
tristate "SPI controller v3 for Blackfin" tristate "SPI controller v3 for ADI"
depends on BF60x depends on BF60x
help help
This is the SPI controller v3 master driver This is the SPI controller v3 master driver
......
...@@ -18,7 +18,7 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o ...@@ -18,7 +18,7 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
......
/* /*
* Analog Devices SPI3 controller driver * Analog Devices SPI3 controller driver
* *
* Copyright (c) 2011 Analog Devices Inc. * Copyright (c) 2014 Analog Devices Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -11,14 +11,10 @@ ...@@ -11,14 +11,10 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef _SPI_CHANNEL_H_ #ifndef _ADI_SPI3_H_
#define _SPI_CHANNEL_H_ #define _ADI_SPI3_H_
#include <linux/types.h> #include <linux/types.h>
...@@ -209,9 +205,9 @@ ...@@ -209,9 +205,9 @@
#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ #define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
/* /*
* bfin spi3 registers layout * adi spi3 registers layout
*/ */
struct bfin_spi_regs { struct adi_spi_regs {
u32 revid; u32 revid;
u32 control; u32 control;
u32 rx_control; u32 rx_control;
...@@ -240,7 +236,7 @@ struct bfin_spi_regs { ...@@ -240,7 +236,7 @@ struct bfin_spi_regs {
#define MAX_CTRL_CS 8 /* cs in spi controller */ #define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */ /* device.platform_data for SSP controller devices */
struct bfin_spi3_master { struct adi_spi3_master {
u16 num_chipselect; u16 num_chipselect;
u16 pin_req[7]; u16 pin_req[7];
}; };
...@@ -248,11 +244,11 @@ struct bfin_spi3_master { ...@@ -248,11 +244,11 @@ struct bfin_spi3_master {
/* spi_board_info.controller_data for SPI slave devices, /* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning * copied to spi_device.platform_data ... mostly for dma tuning
*/ */
struct bfin_spi3_chip { struct adi_spi3_chip {
u32 control; u32 control;
u16 cs_chg_udelay; /* Some devices require 16-bit delays */ u16 cs_chg_udelay; /* Some devices require 16-bit delays */
u32 tx_dummy_val; /* tx value for rx only transfer */ u32 tx_dummy_val; /* tx value for rx only transfer */
bool enable_dma; bool enable_dma;
}; };
#endif /* _SPI_CHANNEL_H_ */ #endif /* _ADI_SPI3_H_ */
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