drm/nouveau/gr/gf100-: split out per-gpc address calculation macro

There's a few places where we need to access a GPC register from ucode,
but outside of the falcon's io address space.  To do this we need to
calculate the offset based on which GPC we're executing on.

This used to be done manually, but we've since found a "base" offset
that can be added by the hardware.  To use this, an extra bit needs to
be set in the register address, which is what this macro achieves.

There should be no functional change from this commit.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc

@@ -52,10 +52,12 @@ mmio_list_base:
 #endif
 
 #ifdef INCLUDE_CODE
+#define gpc_addr(reg,addr)                                                    /*
+*/	imm32(reg,addr)                                                       /*
+*/	or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
 #define gpc_wr32(addr,reg)                                                    /*
+*/	gpc_addr($r14,addr)                                                   /*
 */	mov b32 $r15 reg                                                      /*
-*/	imm32($r14, addr)                                                     /*
-*/	or $r14 NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE                    /*
 */	call(nv_wr32)
 
 // reports an exception to the host

drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h

@@ -356,33 +356,33 @@ uint32_t gm107_grgpc_code[] = {
 	0x02687e2f,
 	0x002fbb00,
 	0x0f003fbb,
-	0x8effb23f,
-	0xf0501d60,
-	0x8f7e01e5,
+	0x1d608e3f,
+	0x01e5f050,
+	0x8f7effb2,
 	0x0c0f0000,
-	0xa88effb2,
-	0xe5f0501d,
-	0x008f7e01,
+	0x501da88e,
+	0xb201e5f0,
+	0x008f7eff,
 	0x03147e00,
-	0xb23f0f00,
-	0x1d608eff,
-	0x01e5f050,
+	0x8e3f0f00,
+	0xf0501d60,
+	0xffb201e5,
 	0x00008f7e,
-	0xffb2000f,
-	0x501d9c8e,
-	0x7e01e5f0,
+	0x9c8e000f,
+	0xe5f0501d,
+	0x7effb201,
 	0x0f00008f,
 	0x03147e01,
-	0x8effb200,
-	0xf0501da8,
-	0x8f7e01e5,
-	0xff0f0000,
-	0x988effb2,
-	0xe5f0501d,
-	0x008f7e01,
-	0xb2020f00,
-	0x1da88eff,
+	0x1da88e00,
 	0x01e5f050,
+	0x8f7effb2,
+	0xff0f0000,
+	0x501d988e,
+	0xb201e5f0,
+	0x008f7eff,
+	0x8e020f00,
+	0xf0501da8,
+	0xffb201e5,
 	0x00008f7e,
 	0x0003147e,
 	0x85050498,
@@ -414,13 +414,13 @@ uint32_t gm107_grgpc_code[] = {
 	0x0050b7bf,
 	0x0142b608,
 	0x0fa81bf4,
-	0x8effb23f,
-	0xf0501d60,
-	0x8f7e01e5,
+	0x1d608e3f,
+	0x01e5f050,
+	0x8f7effb2,
 	0x0d0f0000,
-	0xa88effb2,
-	0xe5f0501d,
-	0x008f7e01,
+	0x501da88e,
+	0xb201e5f0,
+	0x008f7eff,
 	0x03147e00,
 	0x01008000,
 	0x0003f602,
@@ -491,9 +491,9 @@ uint32_t gm107_grgpc_code[] = {
 	0x8000f804,
 	0xf6028100,
 	0x04bd000f,
-	0xc48effb2,
-	0xe5f0501d,
-	0x008f7e01,
+	0x501dc48e,
+	0xb201e5f0,
+	0x008f7eff,
 	0x0711f400,
 	0x0006217e,
 /* 0x0664: ctx_xfer_not_load */
@@ -505,23 +505,23 @@ uint32_t gm107_grgpc_code[] = {
 	0x4afc8003,
 	0x0002f602,
 	0x0c0f04bd,
-	0xa88effb2,
-	0xe5f0501d,
-	0x008f7e01,
+	0x501da88e,
+	0xb201e5f0,
+	0x008f7eff,
 	0x03147e00,
-	0xb23f0f00,
-	0x1d608eff,
-	0x01e5f050,
+	0x8e3f0f00,
+	0xf0501d60,
+	0xffb201e5,
 	0x00008f7e,
-	0xffb2000f,
-	0x501d9c8e,
-	0x7e01e5f0,
+	0x9c8e000f,
+	0xe5f0501d,
+	0x7effb201,
 	0x0f00008f,
 	0x03147e01,
 	0x01fcf000,
-	0xb203f0b6,
-	0x1da88eff,
-	0x01e5f050,
+	0x8e03f0b6,
+	0xf0501da8,
+	0xffb201e5,
 	0x00008f7e,
 	0xf001acf0,
 	0x008b02a5,
@@ -553,9 +553,9 @@ uint32_t gm107_grgpc_code[] = {
 	0x1a12f406,
 /* 0x073c: ctx_xfer_post */
 	0x0002277e,
-	0xffb20d0f,
-	0x501da88e,
-	0x7e01e5f0,
+	0xa88e0d0f,
+	0xe5f0501d,
+	0x7effb201,
 	0x7e00008f,
 /* 0x0753: ctx_xfer_done */
 	0x7e000314,