提交 6ae8c86e 编写于 作者: T Thomas Petazzoni 提交者: Greg Kroah-Hartman

mtd: rawnand: marvell: use regmap_update_bits() for syscon access

[ Upstream commit 88aa3bbfc020d14b13d67af3f5c08aa992d82cd8 ]

The marvell_nfc_init() function fiddles with some bits of a system
controller on Armada 7K/8K. However, it does a read/modify/write
sequence on GENCONF_CLK_GATING_CTRL and GENCONF_ND_CLK_CTRL, which
isn't safe from a concurrency point of view, as the regmap lock isn't
taken accross the read/modify/write sequence. To solve this issue, use
regmap_update_bits().

While at it, since the "reg" variable is no longer needed for the
read/modify/write sequences, get rid of it for the regmap_write() to
GENCONF_SOC_DEVICE_MUX, and directly pass the value to be written as
argument.

Fixes: 02f26ecf ("mtd: nand: add reworked Marvell NAND controller driver")
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NSasha Levin <sashal@kernel.org>
上级 6c7644ad
......@@ -2710,24 +2710,23 @@ static int marvell_nfc_init(struct marvell_nfc *nfc)
struct regmap *sysctrl_base =
syscon_regmap_lookup_by_phandle(np,
"marvell,system-controller");
u32 reg;
if (IS_ERR(sysctrl_base))
return PTR_ERR(sysctrl_base);
reg = GENCONF_SOC_DEVICE_MUX_NFC_EN |
GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
GENCONF_SOC_DEVICE_MUX_NFC_INT_EN;
regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg);
regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX,
GENCONF_SOC_DEVICE_MUX_NFC_EN |
GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
GENCONF_SOC_DEVICE_MUX_NFC_INT_EN);
regmap_read(sysctrl_base, GENCONF_CLK_GATING_CTRL, &reg);
reg |= GENCONF_CLK_GATING_CTRL_ND_GATE;
regmap_write(sysctrl_base, GENCONF_CLK_GATING_CTRL, reg);
regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL,
GENCONF_CLK_GATING_CTRL_ND_GATE,
GENCONF_CLK_GATING_CTRL_ND_GATE);
regmap_read(sysctrl_base, GENCONF_ND_CLK_CTRL, &reg);
reg |= GENCONF_ND_CLK_CTRL_EN;
regmap_write(sysctrl_base, GENCONF_ND_CLK_CTRL, reg);
regmap_update_bits(sysctrl_base, GENCONF_ND_CLK_CTRL,
GENCONF_ND_CLK_CTRL_EN,
GENCONF_ND_CLK_CTRL_EN);
}
/* Configure the DMA if appropriate */
......
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