提交 6a62e5ef 编写于 作者: J Josef Bacik 提交者: John W. Linville

rt2800: do not enable tbtt unless we are in a beacon mode

Please be gentle, I'm a fs developer and this is my first foray into drivers, as
I'm tired of building ralinks driver everytime I update my kernel.  Whenever I
load the rt2800pci driver my box bogs down, and a few printk's later I
discovered its because I was getting 10's of thousands of TBTT interrupts a
second.  I discovered this was because we were setting the beacon timer to 0,
which is apparently what TBTT keys off of.  It seems to me that we should only
be enabling TBTT when we are in a beacon transmitting mode, which from what I
can tell is in AD-HOC and other such modes where the mac80211 layer would have
given us a proper beacon_int to set the beacon timer to instead of 0.  So this
is my fix, only enable TBTT if our sync mode is for beacon.  This makes it so my
box doesn't die everytime I load the rt2800pci driver.  Let me know if this is
acceptable, I just learned all these terms about 15 minutes ago via wikipedia,
so I really am not familiar with how this stuff is supposed to work.  Thanks,
Signed-off-by: NJosef Bacik <josef@redhat.com>
Acked-by: NIvo van Doorn <IvDoorn@gmail.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 dd6ae4f8
...@@ -561,7 +561,8 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, ...@@ -561,7 +561,8 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync); rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
(conf->sync == TSF_SYNC_BEACON));
rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
} }
......
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