ASoC: tlv320aic3x: Clear BIT_CLK_MASTER and WORD_CLK_MASTER bits for for slave mode

According to the datasheet:

Page0 / Register8: Audio Serial Data interface Control Register A
BIT 7: Bit Clock Directional Control
        0: Bit clock is an input (slave mode)
        1: Bit clock is an output (master mode)

BIT 6: Word Clock Directional Control
        0: Word clock is an input (slave mode)
        1: Word clock is an output (master mode)

Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode,
but does not clear these bits for slave mode.
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

sound/soc/codecs/tlv320aic3x.c

@@ -1023,6 +1023,7 @@ static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
 		break;
 	case SND_SOC_DAIFMT_CBS_CFS:
 		aic3x->master = 0;
+		iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
 		break;
 	default:
 		return -EINVAL;