提交 65bdc43d 编写于 作者: D David S. Miller

Merge branch 'xgene_txrx_delay'

Iyappan Subramanian says:

====================
drivers: xgene: Add support RGMII TX/RX delay configuration

X-Gene RGMII ethernet controller has a RGMII bridge that performs the
task of converting the RGMII signal {RX_CLK,RX_CTL, RX_DATA[3:0]} from
PHY to GMII signal {RX_DV,RX_ER,RX_DATA[7:0]} and vice versa.  This
RGMII bridge has a provision to internally delay the input RX_CLK and
the output TX_CLK using configuration registers. This will help in
maintain the CLK-CTL delay relationship in various operating
conditions.

This patch adds support RGMII TX/RX delay configuration.
====================
Signed-off-by: NIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
......@@ -37,6 +37,14 @@ Required properties for ethernet interfaces that have external PHY:
Optional properties:
- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
- tx-delay: Delay value for RGMII bridge TX clock.
Valid values are between 0 to 7, that maps to
417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
Default value is 4, which corresponds to 1611 ps
- rx-delay: Delay value for RGMII bridge RX clock.
Valid values are between 0 to 7, that maps to
273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
Default value is 2, which corresponds to 899 ps
Example:
menetclk: menetclk {
......@@ -72,5 +80,7 @@ Example:
/* Board-specific peripheral configurations */
&menet {
tx-delay = <4>;
rx-delay = <2>;
status = "ok";
};
......@@ -461,6 +461,7 @@ static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
{
struct device *dev = &pdata->pdev->dev;
u32 value, mc2;
u32 intf_ctl, rgmii;
u32 icm0, icm2;
......@@ -490,7 +491,12 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
default:
ENET_INTERFACE_MODE2_SET(&mc2, 2);
intf_ctl |= ENET_GHD_MODE;
CFG_TXCLK_MUXSEL0_SET(&rgmii, 4);
if (dev->of_node) {
CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay);
CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay);
}
xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
......
......@@ -144,6 +144,7 @@ enum xgene_enet_rm {
#define CFG_BYPASS_UNISEC_RX BIT(1)
#define CFG_CLE_BYPASS_EN0 BIT(31)
#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3)
#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
......
......@@ -1118,6 +1118,47 @@ static int xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pda
return ret;
}
static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
{
struct device *dev = &pdata->pdev->dev;
int delay, ret;
ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
if (ret) {
pdata->tx_delay = 4;
return 0;
}
if (delay < 0 || delay > 7) {
dev_err(dev, "Invalid tx-delay specified\n");
return -EINVAL;
}
pdata->tx_delay = delay;
return 0;
}
static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
{
struct device *dev = &pdata->pdev->dev;
int delay, ret;
ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
if (ret) {
pdata->rx_delay = 2;
return 0;
}
if (delay < 0 || delay > 7) {
dev_err(dev, "Invalid rx-delay specified\n");
return -EINVAL;
}
pdata->rx_delay = delay;
return 0;
}
static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
{
......@@ -1194,6 +1235,14 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
return -ENODEV;
}
ret = xgene_get_tx_delay(pdata);
if (ret)
return ret;
ret = xgene_get_rx_delay(pdata);
if (ret)
return ret;
ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
dev_err(dev, "Unable to get ENET Rx IRQ\n");
......
......@@ -184,6 +184,8 @@ struct xgene_enet_pdata {
u8 bp_bufnum;
u16 ring_num;
u32 mss;
u8 tx_delay;
u8 rx_delay;
};
struct xgene_indirect_ctl {
......
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