drm/msm/mdp5: Add a CAP for Source Split

Some of the newer MDP5 versions support Source Split of SSPPs. It is a
feature that allows us to route the output of a hwpipe to 2 Layer
Mixers. This is required to achieve the following use cases:

- Dual DSI: For high res DSI panels (such as 2560x1600 etc), a single
  DSI interface doesn't have the bandwidth to drive the required pixel
  clock. We use 2 DSI interfaces to drive the left and right halves
  of the panel (i.e, 1280x1600 each). The MDP5 pipeline here would look
  like:

         LM0 -- DSPP0 -- INTF1 -- DSI1
        /
hwpipe--
        \
         LM1 -- DSPP1 -- INTF2 -- DSI2

  A single hwpipe is used to scan out the left and right halves to DSI1
  and DSI2 respectively. In order to do this, we need to configure the
  2 Layer Mixers in Source Split mode.

- HDMI 4K: In order to support resolutions with width higher than the
  max width supported by a hwpipe, we club 2 hwpipes together:

hwpipe1 --- LM0 -- DSPP0
       -   -             \
         -                -- 3D Mux -- INTF0 -- HDMI
       -   -             /
hwpipe2 --- LM1 -- DSPP1

  hwpipe1 is staged on the 'left' Layer Mixer, and hwpipe2 is staged on
  the 'right' Layer Mixer. An additional block called the '3D Mux' is
  used to merge the output of the 2 DSPPs to a single interface.
  In this use case, it is possible that a 4K surface is downscaled and
  placed completely within one of the halves. In order to support such
  scenarios (and keep the programming simple), Layer Mixers with Source
  Split can be assigned 2 hw pipes per stage. While scanning out, the HW
  takes care of fetching the pixels fom the correct pipe.

Add a MDP cap to tell whether the HW supports source split or not.
Add a MDP LM cap that tells whether a LM instance can operate in
source split mode (and generate the 'left' part of the display
output).
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NRob Clark <robdclark@gmail.com>

drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c

@@ -191,6 +191,7 @@ const struct mdp5_cfg_hw apq8084_config = {
 	.mdp = {
 		.count = 1,
 		.caps = MDP_CAP_SMP |
+			MDP_CAP_SRC_SPLIT |
 			0,
 	},
 	.smp = {
@@ -237,11 +238,13 @@ const struct mdp5_cfg_hw apq8084_config = {
 		.base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
 		.instances = {
 				{ .id = 0, .pp = 0, .dspp = 0,
-				  .caps = MDP_LM_CAP_DISPLAY, },
+				  .caps = MDP_LM_CAP_DISPLAY |
+					  MDP_LM_CAP_PAIR, },
 				{ .id = 1, .pp = 1, .dspp = 1,
 				  .caps = MDP_LM_CAP_DISPLAY, },
 				{ .id = 2, .pp = 2, .dspp = 2,
-				  .caps = MDP_LM_CAP_DISPLAY, },
+				  .caps = MDP_LM_CAP_DISPLAY |
+					  MDP_LM_CAP_PAIR, },
 				{ .id = 3, .pp = -1, .dspp = -1,
 				  .caps = MDP_LM_CAP_WB, },
 				{ .id = 4, .pp = -1, .dspp = -1,
@@ -350,6 +353,7 @@ const struct mdp5_cfg_hw msm8x94_config = {
 	.mdp = {
 		.count = 1,
 		.caps = MDP_CAP_SMP |
+			MDP_CAP_SRC_SPLIT |
 			0,
 	},
 	.smp = {
@@ -396,11 +400,13 @@ const struct mdp5_cfg_hw msm8x94_config = {
 		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 		.instances = {
 				{ .id = 0, .pp = 0, .dspp = 0,
-				  .caps = MDP_LM_CAP_DISPLAY, },
+				  .caps = MDP_LM_CAP_DISPLAY |
+					  MDP_LM_CAP_PAIR, },
 				{ .id = 1, .pp = 1, .dspp = 1,
 				  .caps = MDP_LM_CAP_DISPLAY, },
 				{ .id = 2, .pp = 2, .dspp = 2,
-				  .caps = MDP_LM_CAP_DISPLAY, },
+				  .caps = MDP_LM_CAP_DISPLAY |
+					  MDP_LM_CAP_PAIR, },
 				{ .id = 3, .pp = -1, .dspp = -1,
 				  .caps = MDP_LM_CAP_WB, },
 				{ .id = 4, .pp = -1, .dspp = -1,
@@ -443,6 +449,7 @@ const struct mdp5_cfg_hw msm8x96_config = {
 		.count = 1,
 		.caps = MDP_CAP_DSC |
 			MDP_CAP_CDM |
+			MDP_CAP_SRC_SPLIT |
 			0,
 	},
 	.ctl = {
@@ -494,11 +501,13 @@ const struct mdp5_cfg_hw msm8x96_config = {
 		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 		.instances = {
 				{ .id = 0, .pp = 0, .dspp = 0,
-				  .caps = MDP_LM_CAP_DISPLAY },
+				  .caps = MDP_LM_CAP_DISPLAY |
+					  MDP_LM_CAP_PAIR, },
 				{ .id = 1, .pp = 1, .dspp = 1,
 				  .caps = MDP_LM_CAP_DISPLAY, },
 				{ .id = 2, .pp = 2, .dspp = -1,
-				  .caps = MDP_LM_CAP_DISPLAY },
+				  .caps = MDP_LM_CAP_DISPLAY |
+					  MDP_LM_CAP_PAIR, },
 				{ .id = 3, .pp = -1, .dspp = -1,
 				  .caps = MDP_LM_CAP_WB, },
 				{ .id = 4, .pp = -1, .dspp = -1,

drivers/gpu/drm/msm/mdp/mdp_kms.h

@@ -104,6 +104,7 @@ const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
 #define MDP_CAP_SMP		BIT(0)	/* Shared Memory Pool                 */
 #define MDP_CAP_DSC		BIT(1)	/* VESA Display Stream Compression    */
 #define MDP_CAP_CDM		BIT(2)	/* Chroma Down Module (HDMI 2.0 YUV)  */
+#define MDP_CAP_SRC_SPLIT	BIT(3)	/* Source Split of SSPPs */
 
 /* MDP pipe capabilities */
 #define MDP_PIPE_CAP_HFLIP			BIT(0)
@@ -117,6 +118,7 @@ const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
 /* MDP layer mixer caps */
 #define MDP_LM_CAP_DISPLAY			BIT(0)
 #define MDP_LM_CAP_WB				BIT(1)
+#define MDP_LM_CAP_PAIR				BIT(2)
 
 static inline bool pipe_supports_yuv(uint32_t pipe_caps)
 {