drm/amd/display: separate scl functions out from dcn10_dpp

Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

@@ -3,7 +3,8 @@
 
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
 		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
-		dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o
+		dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o \
+		dcn10_dpp_dscl.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

@@ -1386,6 +1386,11 @@ struct dcn10_dpp {
 	int lb_bits_per_entry;
 	bool is_write_to_ram_a_safe;
 };
+
+void dcn10_dpp_set_scaler_manual_scale(
+	struct transform *xfm_base,
+	const struct scaler_data *scl_data);
+
 bool dcn10_dpp_construct(struct dcn10_dpp *xfm110,
 	struct dc_context *ctx,
 	uint32_t inst,