MIPS: Loongson 2 needs no hazard barriers.

Quoting from Loongson2FUserGuide.pdf:

5.22.1 Hazards
The processor detects most of the pipeline hazards in hardware, including
CP0 hazards and load hazards. No NOP instructions are required to correct
instruction sequences.
Signed-off-by: NZhang Le <r0bertz@gentoo.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

arch/mips/include/asm/hazards.h

@@ -138,8 +138,9 @@ do {									\
 		__instruction_hazard();					\
 } while (0)
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-      defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
+#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
+      defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.