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5b8f0be0
cloud-kernel
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5b8f0be0
编写于
15年前
作者:
E
Eric Anholt
浏览文件
操作
浏览文件
下载
差异文件
Merge remote branch 'airlied/drm-next' into drm-intel-next
上级
43bcd61f
4fe9676d
无相关合并请求
变更
41
隐藏空白更改
内联
并排
Showing
41 changed file
with
1118 addition
and
619 deletion
+1118
-619
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/drm_fb_helper.c
+1
-1
drivers/gpu/drm/drm_fops.c
drivers/gpu/drm/drm_fops.c
+96
-2
drivers/gpu/drm/drm_irq.c
drivers/gpu/drm/drm_irq.c
+95
-0
drivers/gpu/drm/drm_stub.c
drivers/gpu/drm/drm_stub.c
+2
-0
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.c
+1
-0
drivers/gpu/drm/radeon/atombios.h
drivers/gpu/drm/radeon/atombios.h
+1
-1
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/atombios_crtc.c
+182
-175
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r100.c
+31
-11
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r300.c
+1
-1
drivers/gpu/drm/radeon/r500_reg.h
drivers/gpu/drm/radeon/r500_reg.h
+9
-0
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600.c
+42
-45
drivers/gpu/drm/radeon/r600_blit.c
drivers/gpu/drm/radeon/r600_blit.c
+35
-23
drivers/gpu/drm/radeon/r600_blit_kms.c
drivers/gpu/drm/radeon/r600_blit_kms.c
+1
-2
drivers/gpu/drm/radeon/r600d.h
drivers/gpu/drm/radeon/r600d.h
+4
-0
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon.h
+3
-0
drivers/gpu/drm/radeon/radeon_atombios.c
drivers/gpu/drm/radeon/radeon_atombios.c
+135
-50
drivers/gpu/drm/radeon/radeon_benchmark.c
drivers/gpu/drm/radeon/radeon_benchmark.c
+2
-2
drivers/gpu/drm/radeon/radeon_bios.c
drivers/gpu/drm/radeon/radeon_bios.c
+0
-3
drivers/gpu/drm/radeon/radeon_combios.c
drivers/gpu/drm/radeon/radeon_combios.c
+82
-47
drivers/gpu/drm/radeon/radeon_connectors.c
drivers/gpu/drm/radeon/radeon_connectors.c
+100
-43
drivers/gpu/drm/radeon/radeon_cp.c
drivers/gpu/drm/radeon/radeon_cp.c
+4
-41
drivers/gpu/drm/radeon/radeon_cursor.c
drivers/gpu/drm/radeon/radeon_cursor.c
+8
-2
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_device.c
+17
-12
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_display.c
+8
-20
drivers/gpu/drm/radeon/radeon_encoders.c
drivers/gpu/drm/radeon/radeon_encoders.c
+44
-62
drivers/gpu/drm/radeon/radeon_gart.c
drivers/gpu/drm/radeon/radeon_gart.c
+10
-10
drivers/gpu/drm/radeon/radeon_irq_kms.c
drivers/gpu/drm/radeon/radeon_irq_kms.c
+9
-0
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+22
-18
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+17
-10
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/radeon_mode.h
+18
-15
drivers/gpu/drm/radeon/radeon_reg.h
drivers/gpu/drm/radeon/radeon_reg.h
+6
-0
drivers/gpu/drm/radeon/radeon_test.c
drivers/gpu/drm/radeon/radeon_test.c
+3
-3
drivers/gpu/drm/radeon/radeon_ttm.c
drivers/gpu/drm/radeon/radeon_ttm.c
+6
-0
drivers/gpu/drm/radeon/rs400.c
drivers/gpu/drm/radeon/rs400.c
+2
-0
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rs600.c
+17
-1
drivers/gpu/drm/radeon/rv515.c
drivers/gpu/drm/radeon/rv515.c
+2
-0
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/rv770.c
+39
-17
drivers/gpu/drm/radeon/rv770d.h
drivers/gpu/drm/radeon/rv770d.h
+5
-0
drivers/gpu/drm/ttm/ttm_tt.c
drivers/gpu/drm/ttm/ttm_tt.c
+1
-0
include/drm/drm.h
include/drm/drm.h
+31
-2
include/drm/drmP.h
include/drm/drmP.h
+26
-0
未找到文件。
drivers/gpu/drm/drm_fb_helper.c
浏览文件 @
5b8f0be0
...
...
@@ -707,7 +707,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
if
(
crtc
->
fb
==
fb_helper
->
crtc_info
[
i
].
mode_set
.
fb
)
{
mutex_lock
(
&
dev
->
mode_config
.
mutex
);
ret
=
crtc
->
funcs
->
set_config
(
&
fb_helper
->
crtc_info
->
mode_set
);
ret
=
crtc
->
funcs
->
set_config
(
&
fb_helper
->
crtc_info
[
i
].
mode_set
);
mutex_unlock
(
&
dev
->
mode_config
.
mutex
);
if
(
ret
)
return
ret
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/drm_fops.c
浏览文件 @
5b8f0be0
...
...
@@ -257,6 +257,9 @@ static int drm_open_helper(struct inode *inode, struct file *filp,
INIT_LIST_HEAD
(
&
priv
->
lhead
);
INIT_LIST_HEAD
(
&
priv
->
fbs
);
INIT_LIST_HEAD
(
&
priv
->
event_list
);
init_waitqueue_head
(
&
priv
->
event_wait
);
priv
->
event_space
=
4096
;
/* set aside 4k for event buffer */
if
(
dev
->
driver
->
driver_features
&
DRIVER_GEM
)
drm_gem_open
(
dev
,
priv
);
...
...
@@ -413,6 +416,30 @@ static void drm_master_release(struct drm_device *dev, struct file *filp)
}
}
static
void
drm_events_release
(
struct
drm_file
*
file_priv
)
{
struct
drm_device
*
dev
=
file_priv
->
minor
->
dev
;
struct
drm_pending_event
*
e
,
*
et
;
struct
drm_pending_vblank_event
*
v
,
*
vt
;
unsigned
long
flags
;
spin_lock_irqsave
(
&
dev
->
event_lock
,
flags
);
/* Remove pending flips */
list_for_each_entry_safe
(
v
,
vt
,
&
dev
->
vblank_event_list
,
base
.
link
)
if
(
v
->
base
.
file_priv
==
file_priv
)
{
list_del
(
&
v
->
base
.
link
);
drm_vblank_put
(
dev
,
v
->
pipe
);
v
->
base
.
destroy
(
&
v
->
base
);
}
/* Remove unconsumed events */
list_for_each_entry_safe
(
e
,
et
,
&
file_priv
->
event_list
,
link
)
e
->
destroy
(
e
);
spin_unlock_irqrestore
(
&
dev
->
event_lock
,
flags
);
}
/**
* Release file.
*
...
...
@@ -451,6 +478,8 @@ int drm_release(struct inode *inode, struct file *filp)
if
(
file_priv
->
minor
->
master
)
drm_master_release
(
dev
,
filp
);
drm_events_release
(
file_priv
);
if
(
dev
->
driver
->
driver_features
&
DRIVER_GEM
)
drm_gem_release
(
dev
,
file_priv
);
...
...
@@ -544,9 +573,74 @@ int drm_release(struct inode *inode, struct file *filp)
}
EXPORT_SYMBOL
(
drm_release
);
/** No-op. */
static
bool
drm_dequeue_event
(
struct
drm_file
*
file_priv
,
size_t
total
,
size_t
max
,
struct
drm_pending_event
**
out
)
{
struct
drm_device
*
dev
=
file_priv
->
minor
->
dev
;
struct
drm_pending_event
*
e
;
unsigned
long
flags
;
bool
ret
=
false
;
spin_lock_irqsave
(
&
dev
->
event_lock
,
flags
);
*
out
=
NULL
;
if
(
list_empty
(
&
file_priv
->
event_list
))
goto
out
;
e
=
list_first_entry
(
&
file_priv
->
event_list
,
struct
drm_pending_event
,
link
);
if
(
e
->
event
->
length
+
total
>
max
)
goto
out
;
file_priv
->
event_space
+=
e
->
event
->
length
;
list_del
(
&
e
->
link
);
*
out
=
e
;
ret
=
true
;
out:
spin_unlock_irqrestore
(
&
dev
->
event_lock
,
flags
);
return
ret
;
}
ssize_t
drm_read
(
struct
file
*
filp
,
char
__user
*
buffer
,
size_t
count
,
loff_t
*
offset
)
{
struct
drm_file
*
file_priv
=
filp
->
private_data
;
struct
drm_pending_event
*
e
;
size_t
total
;
ssize_t
ret
;
ret
=
wait_event_interruptible
(
file_priv
->
event_wait
,
!
list_empty
(
&
file_priv
->
event_list
));
if
(
ret
<
0
)
return
ret
;
total
=
0
;
while
(
drm_dequeue_event
(
file_priv
,
total
,
count
,
&
e
))
{
if
(
copy_to_user
(
buffer
+
total
,
e
->
event
,
e
->
event
->
length
))
{
total
=
-
EFAULT
;
break
;
}
total
+=
e
->
event
->
length
;
e
->
destroy
(
e
);
}
return
total
;
}
EXPORT_SYMBOL
(
drm_read
);
unsigned
int
drm_poll
(
struct
file
*
filp
,
struct
poll_table_struct
*
wait
)
{
return
0
;
struct
drm_file
*
file_priv
=
filp
->
private_data
;
unsigned
int
mask
=
0
;
poll_wait
(
filp
,
&
file_priv
->
event_wait
,
wait
);
if
(
!
list_empty
(
&
file_priv
->
event_list
))
mask
|=
POLLIN
|
POLLRDNORM
;
return
mask
;
}
EXPORT_SYMBOL
(
drm_poll
);
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/drm_irq.c
浏览文件 @
5b8f0be0
...
...
@@ -550,6 +550,62 @@ int drm_modeset_ctl(struct drm_device *dev, void *data,
return
ret
;
}
static
int
drm_queue_vblank_event
(
struct
drm_device
*
dev
,
int
pipe
,
union
drm_wait_vblank
*
vblwait
,
struct
drm_file
*
file_priv
)
{
struct
drm_pending_vblank_event
*
e
;
struct
timeval
now
;
unsigned
long
flags
;
unsigned
int
seq
;
e
=
kzalloc
(
sizeof
*
e
,
GFP_KERNEL
);
if
(
e
==
NULL
)
return
-
ENOMEM
;
e
->
pipe
=
pipe
;
e
->
event
.
base
.
type
=
DRM_EVENT_VBLANK
;
e
->
event
.
base
.
length
=
sizeof
e
->
event
;
e
->
event
.
user_data
=
vblwait
->
request
.
signal
;
e
->
base
.
event
=
&
e
->
event
.
base
;
e
->
base
.
file_priv
=
file_priv
;
e
->
base
.
destroy
=
(
void
(
*
)
(
struct
drm_pending_event
*
))
kfree
;
do_gettimeofday
(
&
now
);
spin_lock_irqsave
(
&
dev
->
event_lock
,
flags
);
if
(
file_priv
->
event_space
<
sizeof
e
->
event
)
{
spin_unlock_irqrestore
(
&
dev
->
event_lock
,
flags
);
kfree
(
e
);
return
-
ENOMEM
;
}
file_priv
->
event_space
-=
sizeof
e
->
event
;
seq
=
drm_vblank_count
(
dev
,
pipe
);
if
((
vblwait
->
request
.
type
&
_DRM_VBLANK_NEXTONMISS
)
&&
(
seq
-
vblwait
->
request
.
sequence
)
<=
(
1
<<
23
))
{
vblwait
->
request
.
sequence
=
seq
+
1
;
}
DRM_DEBUG
(
"event on vblank count %d, current %d, crtc %d
\n
"
,
vblwait
->
request
.
sequence
,
seq
,
pipe
);
e
->
event
.
sequence
=
vblwait
->
request
.
sequence
;
if
((
seq
-
vblwait
->
request
.
sequence
)
<=
(
1
<<
23
))
{
e
->
event
.
tv_sec
=
now
.
tv_sec
;
e
->
event
.
tv_usec
=
now
.
tv_usec
;
drm_vblank_put
(
dev
,
e
->
pipe
);
list_add_tail
(
&
e
->
base
.
link
,
&
e
->
base
.
file_priv
->
event_list
);
wake_up_interruptible
(
&
e
->
base
.
file_priv
->
event_wait
);
}
else
{
list_add_tail
(
&
e
->
base
.
link
,
&
dev
->
vblank_event_list
);
}
spin_unlock_irqrestore
(
&
dev
->
event_lock
,
flags
);
return
0
;
}
/**
* Wait for VBLANK.
*
...
...
@@ -609,6 +665,9 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
goto
done
;
}
if
(
flags
&
_DRM_VBLANK_EVENT
)
return
drm_queue_vblank_event
(
dev
,
crtc
,
vblwait
,
file_priv
);
if
((
flags
&
_DRM_VBLANK_NEXTONMISS
)
&&
(
seq
-
vblwait
->
request
.
sequence
)
<=
(
1
<<
23
))
{
vblwait
->
request
.
sequence
=
seq
+
1
;
...
...
@@ -641,6 +700,38 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
return
ret
;
}
void
drm_handle_vblank_events
(
struct
drm_device
*
dev
,
int
crtc
)
{
struct
drm_pending_vblank_event
*
e
,
*
t
;
struct
timeval
now
;
unsigned
long
flags
;
unsigned
int
seq
;
do_gettimeofday
(
&
now
);
seq
=
drm_vblank_count
(
dev
,
crtc
);
spin_lock_irqsave
(
&
dev
->
event_lock
,
flags
);
list_for_each_entry_safe
(
e
,
t
,
&
dev
->
vblank_event_list
,
base
.
link
)
{
if
(
e
->
pipe
!=
crtc
)
continue
;
if
((
seq
-
e
->
event
.
sequence
)
>
(
1
<<
23
))
continue
;
DRM_DEBUG
(
"vblank event on %d, current %d
\n
"
,
e
->
event
.
sequence
,
seq
);
e
->
event
.
sequence
=
seq
;
e
->
event
.
tv_sec
=
now
.
tv_sec
;
e
->
event
.
tv_usec
=
now
.
tv_usec
;
drm_vblank_put
(
dev
,
e
->
pipe
);
list_move_tail
(
&
e
->
base
.
link
,
&
e
->
base
.
file_priv
->
event_list
);
wake_up_interruptible
(
&
e
->
base
.
file_priv
->
event_wait
);
}
spin_unlock_irqrestore
(
&
dev
->
event_lock
,
flags
);
}
/**
* drm_handle_vblank - handle a vblank event
* @dev: DRM device
...
...
@@ -651,7 +742,11 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
*/
void
drm_handle_vblank
(
struct
drm_device
*
dev
,
int
crtc
)
{
if
(
!
dev
->
num_crtcs
)
return
;
atomic_inc
(
&
dev
->
_vblank_count
[
crtc
]);
DRM_WAKEUP
(
&
dev
->
vbl_queue
[
crtc
]);
drm_handle_vblank_events
(
dev
,
crtc
);
}
EXPORT_SYMBOL
(
drm_handle_vblank
);
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/drm_stub.c
浏览文件 @
5b8f0be0
...
...
@@ -220,9 +220,11 @@ static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev,
INIT_LIST_HEAD
(
&
dev
->
ctxlist
);
INIT_LIST_HEAD
(
&
dev
->
vmalist
);
INIT_LIST_HEAD
(
&
dev
->
maplist
);
INIT_LIST_HEAD
(
&
dev
->
vblank_event_list
);
spin_lock_init
(
&
dev
->
count_lock
);
spin_lock_init
(
&
dev
->
drw_lock
);
spin_lock_init
(
&
dev
->
event_lock
);
init_timer
(
&
dev
->
timer
);
mutex_init
(
&
dev
->
struct_mutex
);
mutex_init
(
&
dev
->
ctxlist_mutex
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/i915/i915_drv.c
浏览文件 @
5b8f0be0
...
...
@@ -333,6 +333,7 @@ static struct drm_driver driver = {
.
mmap
=
drm_gem_mmap
,
.
poll
=
drm_poll
,
.
fasync
=
drm_fasync
,
.
read
=
drm_read
,
#ifdef CONFIG_COMPAT
.
compat_ioctl
=
i915_compat_ioctl
,
#endif
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/atombios.h
浏览文件 @
5b8f0be0
...
...
@@ -2314,7 +2314,7 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT {
UCHAR
ucSS_Step
;
UCHAR
ucSS_Delay
;
UCHAR
ucSS_Id
;
UCHAR
ucRecomm
a
ndedRef_Div
;
UCHAR
ucRecomm
e
ndedRef_Div
;
UCHAR
ucSS_Range
;
/* it was reserved for V11 */
}
ATOM_SPREAD_SPECTRUM_ASSIGNMENT
;
...
...
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Click to expand it.
drivers/gpu/drm/radeon/atombios_crtc.c
浏览文件 @
5b8f0be0
...
...
@@ -31,10 +31,6 @@
#include "atom.h"
#include "atom-bits.h"
/* evil but including atombios.h is much worse */
bool
radeon_atom_get_tv_timings
(
struct
radeon_device
*
rdev
,
int
index
,
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION
*
crtc_timing
,
int32_t
*
pixel_clock
);
static
void
atombios_overscan_setup
(
struct
drm_crtc
*
crtc
,
struct
drm_display_mode
*
mode
,
struct
drm_display_mode
*
adjusted_mode
)
...
...
@@ -248,18 +244,18 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
switch
(
mode
)
{
case
DRM_MODE_DPMS_ON
:
atombios_enable_crtc
(
crtc
,
1
);
if
(
ASIC_IS_DCE3
(
rdev
))
atombios_enable_crtc_memreq
(
crtc
,
1
);
atombios_enable_crtc
(
crtc
,
1
);
atombios_blank_crtc
(
crtc
,
0
);
break
;
case
DRM_MODE_DPMS_STANDBY
:
case
DRM_MODE_DPMS_SUSPEND
:
case
DRM_MODE_DPMS_OFF
:
atombios_blank_crtc
(
crtc
,
1
);
atombios_enable_crtc
(
crtc
,
0
);
if
(
ASIC_IS_DCE3
(
rdev
))
atombios_enable_crtc_memreq
(
crtc
,
0
);
atombios_enable_crtc
(
crtc
,
0
);
break
;
}
...
...
@@ -270,59 +266,147 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
static
void
atombios_set_crtc_dtd_timing
(
struct
drm_crtc
*
crtc
,
SET_CRTC_USING_DTD_TIMING_PARAMETERS
*
crtc_param
)
struct
drm_display_mode
*
mode
)
{
struct
radeon_crtc
*
radeon_crtc
=
to_radeon_crtc
(
crtc
);
struct
drm_device
*
dev
=
crtc
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
SET_CRTC_USING_DTD_TIMING_PARAMETERS
conv_param
;
SET_CRTC_USING_DTD_TIMING_PARAMETERS
args
;
int
index
=
GetIndexIntoMasterTable
(
COMMAND
,
SetCRTC_UsingDTDTiming
);
u16
misc
=
0
;
conv_param
.
usH_Size
=
cpu_to_le16
(
crtc_param
->
usH_Size
);
conv_param
.
usH_Blanking_Time
=
cpu_to_le16
(
crtc_param
->
usH_Blanking_Time
);
conv_param
.
usV_Size
=
cpu_to_le16
(
crtc_param
->
usV_Size
);
conv_param
.
usV_Blanking_Time
=
cpu_to_le16
(
crtc_param
->
usV_Blanking_Time
);
conv_param
.
usH_SyncOffset
=
cpu_to_le16
(
crtc_param
->
usH_SyncOffset
);
conv_param
.
usH_SyncWidth
=
cpu_to_le16
(
crtc_param
->
usH_SyncWidth
);
conv_param
.
usV_SyncOffset
=
cpu_to_le16
(
crtc_param
->
usV_SyncOffset
);
conv_param
.
usV_SyncWidth
=
cpu_to_le16
(
crtc_param
->
usV_SyncWidth
);
conv_param
.
susModeMiscInfo
.
usAccess
=
cpu_to_le16
(
crtc_param
->
susModeMiscInfo
.
usAccess
);
conv_param
.
ucCRTC
=
crtc_param
->
ucCRTC
;
memset
(
&
args
,
0
,
sizeof
(
args
));
args
.
usH_Size
=
cpu_to_le16
(
mode
->
crtc_hdisplay
);
args
.
usH_Blanking_Time
=
cpu_to_le16
(
mode
->
crtc_hblank_end
-
mode
->
crtc_hdisplay
);
args
.
usV_Size
=
cpu_to_le16
(
mode
->
crtc_vdisplay
);
args
.
usV_Blanking_Time
=
cpu_to_le16
(
mode
->
crtc_vblank_end
-
mode
->
crtc_vdisplay
);
args
.
usH_SyncOffset
=
cpu_to_le16
(
mode
->
crtc_hsync_start
-
mode
->
crtc_hdisplay
);
args
.
usH_SyncWidth
=
cpu_to_le16
(
mode
->
crtc_hsync_end
-
mode
->
crtc_hsync_start
);
args
.
usV_SyncOffset
=
cpu_to_le16
(
mode
->
crtc_vsync_start
-
mode
->
crtc_vdisplay
);
args
.
usV_SyncWidth
=
cpu_to_le16
(
mode
->
crtc_vsync_end
-
mode
->
crtc_vsync_start
);
/*args.ucH_Border = mode->hborder;*/
/*args.ucV_Border = mode->vborder;*/
if
(
mode
->
flags
&
DRM_MODE_FLAG_NVSYNC
)
misc
|=
ATOM_VSYNC_POLARITY
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_NHSYNC
)
misc
|=
ATOM_HSYNC_POLARITY
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_CSYNC
)
misc
|=
ATOM_COMPOSITESYNC
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_INTERLACE
)
misc
|=
ATOM_INTERLACE
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_DBLSCAN
)
misc
|=
ATOM_DOUBLE_CLOCK_MODE
;
args
.
susModeMiscInfo
.
usAccess
=
cpu_to_le16
(
misc
);
args
.
ucCRTC
=
radeon_crtc
->
crtc_id
;
printk
(
"executing set crtc dtd timing
\n
"
);
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
conv_param
);
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
args
);
}
void
atombios_crtc_set_timing
(
struct
drm_crtc
*
crtc
,
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION
*
crtc_param
)
static
void
atombios_crtc_set_timing
(
struct
drm_crtc
*
crtc
,
struct
drm_display_mode
*
mode
)
{
struct
radeon_crtc
*
radeon_crtc
=
to_radeon_crtc
(
crtc
);
struct
drm_device
*
dev
=
crtc
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION
conv_param
;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION
args
;
int
index
=
GetIndexIntoMasterTable
(
COMMAND
,
SetCRTC_Timing
);
u16
misc
=
0
;
conv_param
.
usH_Total
=
cpu_to_le16
(
crtc_param
->
usH_Total
);
conv_param
.
usH_Disp
=
cpu_to_le16
(
crtc_param
->
usH_Disp
);
conv_param
.
usH_SyncStart
=
cpu_to_le16
(
crtc_param
->
usH_SyncStart
);
conv_param
.
usH_SyncWidth
=
cpu_to_le16
(
crtc_param
->
usH_SyncWidth
);
conv_param
.
usV_Total
=
cpu_to_le16
(
crtc_param
->
usV_Total
);
conv_param
.
usV_Disp
=
cpu_to_le16
(
crtc_param
->
usV_Disp
);
conv_param
.
usV_SyncStart
=
cpu_to_le16
(
crtc_param
->
usV_SyncStart
);
conv_param
.
usV_SyncWidth
=
cpu_to_le16
(
crtc_param
->
usV_SyncWidth
);
conv_param
.
susModeMiscInfo
.
usAccess
=
cpu_to_le16
(
crtc_param
->
susModeMiscInfo
.
usAccess
);
conv_param
.
ucCRTC
=
crtc_param
->
ucCRTC
;
conv_param
.
ucOverscanRight
=
crtc_param
->
ucOverscanRight
;
conv_param
.
ucOverscanLeft
=
crtc_param
->
ucOverscanLeft
;
conv_param
.
ucOverscanBottom
=
crtc_param
->
ucOverscanBottom
;
conv_param
.
ucOverscanTop
=
crtc_param
->
ucOverscanTop
;
conv_param
.
ucReserved
=
crtc_param
->
ucReserved
;
memset
(
&
args
,
0
,
sizeof
(
args
));
args
.
usH_Total
=
cpu_to_le16
(
mode
->
crtc_htotal
);
args
.
usH_Disp
=
cpu_to_le16
(
mode
->
crtc_hdisplay
);
args
.
usH_SyncStart
=
cpu_to_le16
(
mode
->
crtc_hsync_start
);
args
.
usH_SyncWidth
=
cpu_to_le16
(
mode
->
crtc_hsync_end
-
mode
->
crtc_hsync_start
);
args
.
usV_Total
=
cpu_to_le16
(
mode
->
crtc_vtotal
);
args
.
usV_Disp
=
cpu_to_le16
(
mode
->
crtc_vdisplay
);
args
.
usV_SyncStart
=
cpu_to_le16
(
mode
->
crtc_vsync_start
);
args
.
usV_SyncWidth
=
cpu_to_le16
(
mode
->
crtc_vsync_end
-
mode
->
crtc_vsync_start
);
if
(
mode
->
flags
&
DRM_MODE_FLAG_NVSYNC
)
misc
|=
ATOM_VSYNC_POLARITY
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_NHSYNC
)
misc
|=
ATOM_HSYNC_POLARITY
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_CSYNC
)
misc
|=
ATOM_COMPOSITESYNC
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_INTERLACE
)
misc
|=
ATOM_INTERLACE
;
if
(
mode
->
flags
&
DRM_MODE_FLAG_DBLSCAN
)
misc
|=
ATOM_DOUBLE_CLOCK_MODE
;
args
.
susModeMiscInfo
.
usAccess
=
cpu_to_le16
(
misc
);
args
.
ucCRTC
=
radeon_crtc
->
crtc_id
;
printk
(
"executing set crtc timing
\n
"
);
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
conv_param
);
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
args
);
}
static
void
atombios_set_ss
(
struct
drm_crtc
*
crtc
,
int
enable
)
{
struct
radeon_crtc
*
radeon_crtc
=
to_radeon_crtc
(
crtc
);
struct
drm_device
*
dev
=
crtc
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
struct
drm_encoder
*
encoder
=
NULL
;
struct
radeon_encoder
*
radeon_encoder
=
NULL
;
struct
radeon_encoder_atom_dig
*
dig
=
NULL
;
int
index
=
GetIndexIntoMasterTable
(
COMMAND
,
EnableSpreadSpectrumOnPPLL
);
ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION
args
;
ENABLE_LVDS_SS_PARAMETERS
legacy_args
;
uint16_t
percentage
=
0
;
uint8_t
type
=
0
,
step
=
0
,
delay
=
0
,
range
=
0
;
list_for_each_entry
(
encoder
,
&
dev
->
mode_config
.
encoder_list
,
head
)
{
if
(
encoder
->
crtc
==
crtc
)
{
radeon_encoder
=
to_radeon_encoder
(
encoder
);
/* only enable spread spectrum on LVDS */
if
(
radeon_encoder
->
devices
&
(
ATOM_DEVICE_LCD_SUPPORT
))
{
dig
=
radeon_encoder
->
enc_priv
;
if
(
dig
&&
dig
->
ss
)
{
percentage
=
dig
->
ss
->
percentage
;
type
=
dig
->
ss
->
type
;
step
=
dig
->
ss
->
step
;
delay
=
dig
->
ss
->
delay
;
range
=
dig
->
ss
->
range
;
}
else
if
(
enable
)
return
;
}
else
if
(
enable
)
return
;
break
;
}
}
if
(
!
radeon_encoder
)
return
;
if
(
ASIC_IS_AVIVO
(
rdev
))
{
memset
(
&
args
,
0
,
sizeof
(
args
));
args
.
usSpreadSpectrumPercentage
=
cpu_to_le16
(
percentage
);
args
.
ucSpreadSpectrumType
=
type
;
args
.
ucSpreadSpectrumStep
=
step
;
args
.
ucSpreadSpectrumDelay
=
delay
;
args
.
ucSpreadSpectrumRange
=
range
;
args
.
ucPpll
=
radeon_crtc
->
crtc_id
?
ATOM_PPLL2
:
ATOM_PPLL1
;
args
.
ucEnable
=
enable
;
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
args
);
}
else
{
memset
(
&
legacy_args
,
0
,
sizeof
(
legacy_args
));
legacy_args
.
usSpreadSpectrumPercentage
=
cpu_to_le16
(
percentage
);
legacy_args
.
ucSpreadSpectrumType
=
type
;
legacy_args
.
ucSpreadSpectrumStepSize_Delay
=
(
step
&
3
)
<<
2
;
legacy_args
.
ucSpreadSpectrumStepSize_Delay
|=
(
delay
&
7
)
<<
4
;
legacy_args
.
ucEnable
=
enable
;
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
legacy_args
);
}
}
void
atombios_crtc_set_pll
(
struct
drm_crtc
*
crtc
,
struct
drm_display_mode
*
mode
)
...
...
@@ -333,12 +417,13 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
struct
drm_encoder
*
encoder
=
NULL
;
struct
radeon_encoder
*
radeon_encoder
=
NULL
;
uint8_t
frev
,
crev
;
int
index
=
GetIndexIntoMasterTable
(
COMMAND
,
SetPixelClock
)
;
int
index
;
SET_PIXEL_CLOCK_PS_ALLOCATION
args
;
PIXEL_CLOCK_PARAMETERS
*
spc1_ptr
;
PIXEL_CLOCK_PARAMETERS_V2
*
spc2_ptr
;
PIXEL_CLOCK_PARAMETERS_V3
*
spc3_ptr
;
uint32_t
sclock
=
mode
->
clock
;
uint32_t
pll_clock
=
mode
->
clock
;
uint32_t
adjusted_clock
;
uint32_t
ref_div
=
0
,
fb_div
=
0
,
frac_fb_div
=
0
,
post_div
=
0
;
struct
radeon_pll
*
pll
;
int
pll_flags
=
0
;
...
...
@@ -346,8 +431,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
memset
(
&
args
,
0
,
sizeof
(
args
));
if
(
ASIC_IS_AVIVO
(
rdev
))
{
uint32_t
ss_cntl
;
if
((
rdev
->
family
==
CHIP_RS600
)
||
(
rdev
->
family
==
CHIP_RS690
)
||
(
rdev
->
family
==
CHIP_RS740
))
...
...
@@ -358,15 +441,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
pll_flags
|=
RADEON_PLL_PREFER_HIGH_FB_DIV
;
else
pll_flags
|=
RADEON_PLL_PREFER_LOW_REF_DIV
;
/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
if
(
radeon_crtc
->
crtc_id
==
0
)
{
ss_cntl
=
RREG32
(
AVIVO_P1PLL_INT_SS_CNTL
);
WREG32
(
AVIVO_P1PLL_INT_SS_CNTL
,
ss_cntl
&
~
1
);
}
else
{
ss_cntl
=
RREG32
(
AVIVO_P2PLL_INT_SS_CNTL
);
WREG32
(
AVIVO_P2PLL_INT_SS_CNTL
,
ss_cntl
&
~
1
);
}
}
else
{
pll_flags
|=
RADEON_PLL_LEGACY
;
...
...
@@ -393,14 +467,43 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
}
}
/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
* accordingly based on the encoder/transmitter to work around
* special hw requirements.
*/
if
(
ASIC_IS_DCE3
(
rdev
))
{
ADJUST_DISPLAY_PLL_PS_ALLOCATION
adjust_pll_args
;
if
(
!
encoder
)
return
;
memset
(
&
adjust_pll_args
,
0
,
sizeof
(
adjust_pll_args
));
adjust_pll_args
.
usPixelClock
=
cpu_to_le16
(
mode
->
clock
/
10
);
adjust_pll_args
.
ucTransmitterID
=
radeon_encoder
->
encoder_id
;
adjust_pll_args
.
ucEncodeMode
=
atombios_get_encoder_mode
(
encoder
);
index
=
GetIndexIntoMasterTable
(
COMMAND
,
AdjustDisplayPll
);
atom_execute_table
(
rdev
->
mode_info
.
atom_context
,
index
,
(
uint32_t
*
)
&
adjust_pll_args
);
adjusted_clock
=
le16_to_cpu
(
adjust_pll_args
.
usPixelClock
)
*
10
;
}
else
{
/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
if
(
ASIC_IS_AVIVO
(
rdev
)
&&
(
radeon_encoder
->
encoder_id
==
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
))
adjusted_clock
=
mode
->
clock
*
2
;
else
adjusted_clock
=
mode
->
clock
;
}
if
(
radeon_crtc
->
crtc_id
==
0
)
pll
=
&
rdev
->
clock
.
p1pll
;
else
pll
=
&
rdev
->
clock
.
p2pll
;
radeon_compute_pll
(
pll
,
mode
->
clock
,
&
s
clock
,
&
fb_div
,
&
frac_fb_div
,
radeon_compute_pll
(
pll
,
adjusted_clock
,
&
pll_
clock
,
&
fb_div
,
&
frac_fb_div
,
&
ref_div
,
&
post_div
,
pll_flags
);
index
=
GetIndexIntoMasterTable
(
COMMAND
,
SetPixelClock
);
atom_parse_cmd_header
(
rdev
->
mode_info
.
atom_context
,
index
,
&
frev
,
&
crev
);
...
...
@@ -409,7 +512,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
switch
(
crev
)
{
case
1
:
spc1_ptr
=
(
PIXEL_CLOCK_PARAMETERS
*
)
&
args
.
sPCLKInput
;
spc1_ptr
->
usPixelClock
=
cpu_to_le16
(
sclock
);
spc1_ptr
->
usPixelClock
=
cpu_to_le16
(
mode
->
clock
/
10
);
spc1_ptr
->
usRefDiv
=
cpu_to_le16
(
ref_div
);
spc1_ptr
->
usFbDiv
=
cpu_to_le16
(
fb_div
);
spc1_ptr
->
ucFracFbDiv
=
frac_fb_div
;
...
...
@@ -422,7 +525,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
case
2
:
spc2_ptr
=
(
PIXEL_CLOCK_PARAMETERS_V2
*
)
&
args
.
sPCLKInput
;
spc2_ptr
->
usPixelClock
=
cpu_to_le16
(
sclock
);
spc2_ptr
->
usPixelClock
=
cpu_to_le16
(
mode
->
clock
/
10
);
spc2_ptr
->
usRefDiv
=
cpu_to_le16
(
ref_div
);
spc2_ptr
->
usFbDiv
=
cpu_to_le16
(
fb_div
);
spc2_ptr
->
ucFracFbDiv
=
frac_fb_div
;
...
...
@@ -437,7 +540,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
return
;
spc3_ptr
=
(
PIXEL_CLOCK_PARAMETERS_V3
*
)
&
args
.
sPCLKInput
;
spc3_ptr
->
usPixelClock
=
cpu_to_le16
(
sclock
);
spc3_ptr
->
usPixelClock
=
cpu_to_le16
(
mode
->
clock
/
10
);
spc3_ptr
->
usRefDiv
=
cpu_to_le16
(
ref_div
);
spc3_ptr
->
usFbDiv
=
cpu_to_le16
(
fb_div
);
spc3_ptr
->
ucFracFbDiv
=
frac_fb_div
;
...
...
@@ -527,6 +630,16 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
WREG32
(
AVIVO_D1VGA_CONTROL
,
0
);
else
WREG32
(
AVIVO_D2VGA_CONTROL
,
0
);
if
(
rdev
->
family
>=
CHIP_RV770
)
{
if
(
radeon_crtc
->
crtc_id
)
{
WREG32
(
R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
,
0
);
WREG32
(
R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
,
0
);
}
else
{
WREG32
(
R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
,
0
);
WREG32
(
R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
,
0
);
}
}
WREG32
(
AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
+
radeon_crtc
->
crtc_offset
,
(
u32
)
fb_location
);
WREG32
(
AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
+
...
...
@@ -563,6 +676,10 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
radeon_fb
=
to_radeon_framebuffer
(
old_fb
);
radeon_gem_object_unpin
(
radeon_fb
->
obj
);
}
/* Bytes per pixel may have changed */
radeon_bandwidth_update
(
rdev
);
return
0
;
}
...
...
@@ -574,134 +691,24 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
struct
radeon_crtc
*
radeon_crtc
=
to_radeon_crtc
(
crtc
);
struct
drm_device
*
dev
=
crtc
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
struct
drm_encoder
*
encoder
;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION
crtc_timing
;
int
need_tv_timings
=
0
;
bool
ret
;
/* TODO color tiling */
memset
(
&
crtc_timing
,
0
,
sizeof
(
crtc_timing
));
list_for_each_entry
(
encoder
,
&
dev
->
mode_config
.
encoder_list
,
head
)
{
/* find tv std */
if
(
encoder
->
crtc
==
crtc
)
{
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
if
(
radeon_encoder
->
active_device
&
ATOM_DEVICE_TV_SUPPORT
)
{
struct
radeon_encoder_atom_dac
*
tv_dac
=
radeon_encoder
->
enc_priv
;
if
(
tv_dac
)
{
if
(
tv_dac
->
tv_std
==
TV_STD_NTSC
||
tv_dac
->
tv_std
==
TV_STD_NTSC_J
||
tv_dac
->
tv_std
==
TV_STD_PAL_M
)
need_tv_timings
=
1
;
else
need_tv_timings
=
2
;
break
;
}
}
}
}
crtc_timing
.
ucCRTC
=
radeon_crtc
->
crtc_id
;
if
(
need_tv_timings
)
{
ret
=
radeon_atom_get_tv_timings
(
rdev
,
need_tv_timings
-
1
,
&
crtc_timing
,
&
adjusted_mode
->
clock
);
if
(
ret
==
false
)
need_tv_timings
=
0
;
}
if
(
!
need_tv_timings
)
{
crtc_timing
.
usH_Total
=
adjusted_mode
->
crtc_htotal
;
crtc_timing
.
usH_Disp
=
adjusted_mode
->
crtc_hdisplay
;
crtc_timing
.
usH_SyncStart
=
adjusted_mode
->
crtc_hsync_start
;
crtc_timing
.
usH_SyncWidth
=
adjusted_mode
->
crtc_hsync_end
-
adjusted_mode
->
crtc_hsync_start
;
crtc_timing
.
usV_Total
=
adjusted_mode
->
crtc_vtotal
;
crtc_timing
.
usV_Disp
=
adjusted_mode
->
crtc_vdisplay
;
crtc_timing
.
usV_SyncStart
=
adjusted_mode
->
crtc_vsync_start
;
crtc_timing
.
usV_SyncWidth
=
adjusted_mode
->
crtc_vsync_end
-
adjusted_mode
->
crtc_vsync_start
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_NVSYNC
)
crtc_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_VSYNC_POLARITY
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_NHSYNC
)
crtc_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_HSYNC_POLARITY
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_CSYNC
)
crtc_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_COMPOSITESYNC
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_INTERLACE
)
crtc_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_INTERLACE
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_DBLSCAN
)
crtc_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_DOUBLE_CLOCK_MODE
;
}
atombios_set_ss
(
crtc
,
0
);
atombios_crtc_set_pll
(
crtc
,
adjusted_mode
);
atombios_crtc_set_timing
(
crtc
,
&
crtc_timing
);
atombios_set_ss
(
crtc
,
1
);
atombios_crtc_set_timing
(
crtc
,
adjusted_mode
);
if
(
ASIC_IS_AVIVO
(
rdev
))
atombios_crtc_set_base
(
crtc
,
x
,
y
,
old_fb
);
else
{
if
(
radeon_crtc
->
crtc_id
==
0
)
{
SET_CRTC_USING_DTD_TIMING_PARAMETERS
crtc_dtd_timing
;
memset
(
&
crtc_dtd_timing
,
0
,
sizeof
(
crtc_dtd_timing
));
/* setup FP shadow regs on R4xx */
crtc_dtd_timing
.
ucCRTC
=
radeon_crtc
->
crtc_id
;
crtc_dtd_timing
.
usH_Size
=
adjusted_mode
->
crtc_hdisplay
;
crtc_dtd_timing
.
usV_Size
=
adjusted_mode
->
crtc_vdisplay
;
crtc_dtd_timing
.
usH_Blanking_Time
=
adjusted_mode
->
crtc_hblank_end
-
adjusted_mode
->
crtc_hdisplay
;
crtc_dtd_timing
.
usV_Blanking_Time
=
adjusted_mode
->
crtc_vblank_end
-
adjusted_mode
->
crtc_vdisplay
;
crtc_dtd_timing
.
usH_SyncOffset
=
adjusted_mode
->
crtc_hsync_start
-
adjusted_mode
->
crtc_hdisplay
;
crtc_dtd_timing
.
usV_SyncOffset
=
adjusted_mode
->
crtc_vsync_start
-
adjusted_mode
->
crtc_vdisplay
;
crtc_dtd_timing
.
usH_SyncWidth
=
adjusted_mode
->
crtc_hsync_end
-
adjusted_mode
->
crtc_hsync_start
;
crtc_dtd_timing
.
usV_SyncWidth
=
adjusted_mode
->
crtc_vsync_end
-
adjusted_mode
->
crtc_vsync_start
;
/* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
/* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_NVSYNC
)
crtc_dtd_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_VSYNC_POLARITY
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_NHSYNC
)
crtc_dtd_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_HSYNC_POLARITY
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_CSYNC
)
crtc_dtd_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_COMPOSITESYNC
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_INTERLACE
)
crtc_dtd_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_INTERLACE
;
if
(
adjusted_mode
->
flags
&
DRM_MODE_FLAG_DBLSCAN
)
crtc_dtd_timing
.
susModeMiscInfo
.
usAccess
|=
ATOM_DOUBLE_CLOCK_MODE
;
atombios_set_crtc_dtd_timing
(
crtc
,
&
crtc_dtd_timing
);
}
if
(
radeon_crtc
->
crtc_id
==
0
)
atombios_set_crtc_dtd_timing
(
crtc
,
adjusted_mode
);
radeon_crtc_set_base
(
crtc
,
x
,
y
,
old_fb
);
radeon_legacy_atom_set_surface
(
crtc
);
}
atombios_overscan_setup
(
crtc
,
mode
,
adjusted_mode
);
atombios_scaler_setup
(
crtc
);
radeon_bandwidth_update
(
rdev
);
return
0
;
}
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r100.c
浏览文件 @
5b8f0be0
...
...
@@ -186,7 +186,7 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
int
r100_irq_process
(
struct
radeon_device
*
rdev
)
{
uint32_t
status
;
uint32_t
status
,
msi_rearm
;
status
=
r100_irq_ack
(
rdev
);
if
(
!
status
)
{
...
...
@@ -209,6 +209,21 @@ int r100_irq_process(struct radeon_device *rdev)
}
status
=
r100_irq_ack
(
rdev
);
}
if
(
rdev
->
msi_enabled
)
{
switch
(
rdev
->
family
)
{
case
CHIP_RS400
:
case
CHIP_RS480
:
msi_rearm
=
RREG32
(
RADEON_AIC_CNTL
)
&
~
RS400_MSI_REARM
;
WREG32
(
RADEON_AIC_CNTL
,
msi_rearm
);
WREG32
(
RADEON_AIC_CNTL
,
msi_rearm
|
RS400_MSI_REARM
);
break
;
default:
msi_rearm
=
RREG32
(
RADEON_MSI_REARM_EN
)
&
~
RV370_MSI_REARM_EN
;
WREG32
(
RADEON_MSI_REARM_EN
,
msi_rearm
);
WREG32
(
RADEON_MSI_REARM_EN
,
msi_rearm
|
RV370_MSI_REARM_EN
);
break
;
}
}
return
IRQ_HANDLED
;
}
...
...
@@ -240,7 +255,7 @@ int r100_wb_init(struct radeon_device *rdev)
int
r
;
if
(
rdev
->
wb
.
wb_obj
==
NULL
)
{
r
=
radeon_object_create
(
rdev
,
NULL
,
4096
,
r
=
radeon_object_create
(
rdev
,
NULL
,
RADEON_GPU_PAGE_SIZE
,
true
,
RADEON_GEM_DOMAIN_GTT
,
false
,
&
rdev
->
wb
.
wb_obj
);
...
...
@@ -563,19 +578,19 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
indirect1_start
=
16
;
/* cp setup */
WREG32
(
0x718
,
pre_write_timer
|
(
pre_write_limit
<<
28
));
WREG32
(
RADEON_CP_RB_CNTL
,
#ifdef __BIG_ENDIAN
RADEON_BUF_SWAP_32BIT
|
#endif
REG_SET
(
RADEON_RB_BUFSZ
,
rb_bufsz
)
|
tmp
=
(
REG_SET
(
RADEON_RB_BUFSZ
,
rb_bufsz
)
|
REG_SET
(
RADEON_RB_BLKSZ
,
rb_blksz
)
|
REG_SET
(
RADEON_MAX_FETCH
,
max_fetch
)
|
RADEON_RB_NO_UPDATE
);
#ifdef __BIG_ENDIAN
tmp
|=
RADEON_BUF_SWAP_32BIT
;
#endif
WREG32
(
RADEON_CP_RB_CNTL
,
tmp
);
/* Set ring address */
DRM_INFO
(
"radeon: ring at 0x%016lX
\n
"
,
(
unsigned
long
)
rdev
->
cp
.
gpu_addr
);
WREG32
(
RADEON_CP_RB_BASE
,
rdev
->
cp
.
gpu_addr
);
/* Force read & write ptr to 0 */
tmp
=
RREG32
(
RADEON_CP_RB_CNTL
);
WREG32
(
RADEON_CP_RB_CNTL
,
tmp
|
RADEON_RB_RPTR_WR_ENA
);
WREG32
(
RADEON_CP_RB_RPTR_WR
,
0
);
WREG32
(
RADEON_CP_RB_WPTR
,
0
);
...
...
@@ -2364,7 +2379,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
/*
Find the total latency for the display data.
*/
disp_latency_overhead
.
full
=
rfixed_const
(
8
0
);
disp_latency_overhead
.
full
=
rfixed_const
(
8
);
disp_latency_overhead
.
full
=
rfixed_div
(
disp_latency_overhead
,
sclk_ff
);
mc_latency_mclk
.
full
+=
disp_latency_overhead
.
full
+
cur_latency_mclk
.
full
;
mc_latency_sclk
.
full
+=
disp_latency_overhead
.
full
+
cur_latency_sclk
.
full
;
...
...
@@ -2562,8 +2577,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
static
inline
void
r100_cs_track_texture_print
(
struct
r100_cs_track_texture
*
t
)
{
DRM_ERROR
(
"pitch %d
\n
"
,
t
->
pitch
);
DRM_ERROR
(
"use_pitch %d
\n
"
,
t
->
use_pitch
);
DRM_ERROR
(
"width %d
\n
"
,
t
->
width
);
DRM_ERROR
(
"width_11 %d
\n
"
,
t
->
width_11
);
DRM_ERROR
(
"height %d
\n
"
,
t
->
height
);
DRM_ERROR
(
"height_11 %d
\n
"
,
t
->
height_11
);
DRM_ERROR
(
"num levels %d
\n
"
,
t
->
num_levels
);
DRM_ERROR
(
"depth %d
\n
"
,
t
->
txdepth
);
DRM_ERROR
(
"bpp %d
\n
"
,
t
->
cpp
);
...
...
@@ -2623,15 +2641,17 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
else
w
=
track
->
textures
[
u
].
pitch
/
(
1
<<
i
);
}
else
{
w
=
track
->
textures
[
u
].
width
/
(
1
<<
i
)
;
w
=
track
->
textures
[
u
].
width
;
if
(
rdev
->
family
>=
CHIP_RV515
)
w
|=
track
->
textures
[
u
].
width_11
;
w
=
w
/
(
1
<<
i
);
if
(
track
->
textures
[
u
].
roundup_w
)
w
=
roundup_pow_of_two
(
w
);
}
h
=
track
->
textures
[
u
].
height
/
(
1
<<
i
)
;
h
=
track
->
textures
[
u
].
height
;
if
(
rdev
->
family
>=
CHIP_RV515
)
h
|=
track
->
textures
[
u
].
height_11
;
h
=
h
/
(
1
<<
i
);
if
(
track
->
textures
[
u
].
roundup_h
)
h
=
roundup_pow_of_two
(
h
);
size
+=
w
*
h
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r300.c
浏览文件 @
5b8f0be0
...
...
@@ -113,7 +113,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
tmp
=
RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
WREG32_PCIE
(
RADEON_PCIE_TX_GART_CNTL
,
tmp
);
WREG32_PCIE
(
RADEON_PCIE_TX_GART_START_LO
,
rdev
->
mc
.
gtt_location
);
tmp
=
rdev
->
mc
.
gtt_location
+
rdev
->
mc
.
gtt_size
-
4096
;
tmp
=
rdev
->
mc
.
gtt_location
+
rdev
->
mc
.
gtt_size
-
RADEON_GPU_PAGE_SIZE
;
WREG32_PCIE
(
RADEON_PCIE_TX_GART_END_LO
,
tmp
);
WREG32_PCIE
(
RADEON_PCIE_TX_GART_START_HI
,
0
);
WREG32_PCIE
(
RADEON_PCIE_TX_GART_END_HI
,
0
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r500_reg.h
浏览文件 @
5b8f0be0
...
...
@@ -384,9 +384,16 @@
# define AVIVO_D1GRPH_TILED (1 << 20)
# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
* block and vice versa. This applies to GRPH, CUR, etc.
*/
#define AVIVO_D1GRPH_LUT_SEL 0x6108
#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
#define AVIVO_D1GRPH_PITCH 0x6120
#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
...
...
@@ -404,6 +411,8 @@
# define AVIVO_D1CURSOR_MODE_MASK (3 << 8)
# define AVIVO_D1CURSOR_MODE_24BPP 2
#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
#define AVIVO_D1CUR_SIZE 0x6410
#define AVIVO_D1CUR_POSITION 0x6414
#define AVIVO_D1CUR_HOT_SPOT 0x6418
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r600.c
浏览文件 @
5b8f0be0
...
...
@@ -339,11 +339,10 @@ int r600_mc_init(struct radeon_device *rdev)
{
fixed20_12
a
;
u32
tmp
;
int
chansize
;
int
chansize
,
numchan
;
int
r
;
/* Get VRAM informations */
rdev
->
mc
.
vram_width
=
128
;
rdev
->
mc
.
vram_is_ddr
=
true
;
tmp
=
RREG32
(
RAMCFG
);
if
(
tmp
&
CHANSIZE_OVERRIDE
)
{
...
...
@@ -353,17 +352,23 @@ int r600_mc_init(struct radeon_device *rdev)
}
else
{
chansize
=
32
;
}
if
(
rdev
->
family
==
CHIP_R600
)
{
rdev
->
mc
.
vram_width
=
8
*
chansize
;
}
else
if
(
rdev
->
family
==
CHIP_RV670
)
{
rdev
->
mc
.
vram_width
=
4
*
chansize
;
}
else
if
((
rdev
->
family
==
CHIP_RV610
)
||
(
rdev
->
family
==
CHIP_RV620
))
{
rdev
->
mc
.
vram_width
=
chansize
;
}
else
if
((
rdev
->
family
==
CHIP_RV630
)
||
(
rdev
->
family
==
CHIP_RV635
))
{
rdev
->
mc
.
vram_width
=
2
*
chansize
;
tmp
=
RREG32
(
CHMAP
);
switch
((
tmp
&
NOOFCHAN_MASK
)
>>
NOOFCHAN_SHIFT
)
{
case
0
:
default:
numchan
=
1
;
break
;
case
1
:
numchan
=
2
;
break
;
case
2
:
numchan
=
4
;
break
;
case
3
:
numchan
=
8
;
break
;
}
rdev
->
mc
.
vram_width
=
numchan
*
chansize
;
/* Could aper size report 0 ? */
rdev
->
mc
.
aper_base
=
drm_get_resource_start
(
rdev
->
ddev
,
0
);
rdev
->
mc
.
aper_size
=
drm_get_resource_len
(
rdev
->
ddev
,
0
);
...
...
@@ -404,35 +409,29 @@ int r600_mc_init(struct radeon_device *rdev)
rdev
->
mc
.
gtt_location
=
rdev
->
mc
.
mc_vram_size
;
}
}
else
{
if
(
rdev
->
family
==
CHIP_RS780
||
rdev
->
family
==
CHIP_RS880
)
{
rdev
->
mc
.
vram_location
=
(
RREG32
(
MC_VM_FB_LOCATION
)
&
0xFFFF
)
<<
24
;
rdev
->
mc
.
gtt_size
=
radeon_gart_size
*
1024
*
1024
;
tmp
=
rdev
->
mc
.
vram_location
+
rdev
->
mc
.
mc_vram_size
;
if
((
0xFFFFFFFFUL
-
tmp
)
>=
rdev
->
mc
.
gtt_size
)
{
/* Enough place after vram */
rdev
->
mc
.
gtt_location
=
tmp
;
}
else
if
(
rdev
->
mc
.
vram_location
>=
rdev
->
mc
.
gtt_size
)
{
/* Enough place before vram */
rdev
->
mc
.
gtt_size
=
radeon_gart_size
*
1024
*
1024
;
rdev
->
mc
.
vram_location
=
(
RREG32
(
MC_VM_FB_LOCATION
)
&
0xFFFF
)
<<
24
;
tmp
=
rdev
->
mc
.
vram_location
+
rdev
->
mc
.
mc_vram_size
;
if
((
0xFFFFFFFFUL
-
tmp
)
>=
rdev
->
mc
.
gtt_size
)
{
/* Enough place after vram */
rdev
->
mc
.
gtt_location
=
tmp
;
}
else
if
(
rdev
->
mc
.
vram_location
>=
rdev
->
mc
.
gtt_size
)
{
/* Enough place before vram */
rdev
->
mc
.
gtt_location
=
0
;
}
else
{
/* Not enough place after or before shrink
* gart size
*/
if
(
rdev
->
mc
.
vram_location
>
(
0xFFFFFFFFUL
-
tmp
))
{
rdev
->
mc
.
gtt_location
=
0
;
rdev
->
mc
.
gtt_size
=
rdev
->
mc
.
vram_location
;
}
else
{
/* Not enough place after or before shrink
* gart size
*/
if
(
rdev
->
mc
.
vram_location
>
(
0xFFFFFFFFUL
-
tmp
))
{
rdev
->
mc
.
gtt_location
=
0
;
rdev
->
mc
.
gtt_size
=
rdev
->
mc
.
vram_location
;
}
else
{
rdev
->
mc
.
gtt_location
=
tmp
;
rdev
->
mc
.
gtt_size
=
0xFFFFFFFFUL
-
tmp
;
}
rdev
->
mc
.
gtt_location
=
tmp
;
rdev
->
mc
.
gtt_size
=
0xFFFFFFFFUL
-
tmp
;
}
rdev
->
mc
.
gtt_location
=
rdev
->
mc
.
mc_vram_size
;
}
else
{
rdev
->
mc
.
vram_location
=
0x00000000UL
;
rdev
->
mc
.
gtt_location
=
rdev
->
mc
.
mc_vram_size
;
rdev
->
mc
.
gtt_size
=
radeon_gart_size
*
1024
*
1024
;
}
rdev
->
mc
.
gtt_location
=
rdev
->
mc
.
mc_vram_size
;
}
rdev
->
mc
.
vram_start
=
rdev
->
mc
.
vram_location
;
rdev
->
mc
.
vram_end
=
rdev
->
mc
.
vram_location
+
rdev
->
mc
.
mc_vram_size
-
1
;
...
...
@@ -1267,19 +1266,17 @@ int r600_cp_resume(struct radeon_device *rdev)
/* Set ring buffer size */
rb_bufsz
=
drm_order
(
rdev
->
cp
.
ring_size
/
8
);
tmp
=
RB_NO_UPDATE
|
(
drm_order
(
RADEON_GPU_PAGE_SIZE
/
8
)
<<
8
)
|
rb_bufsz
;
#ifdef __BIG_ENDIAN
WREG32
(
CP_RB_CNTL
,
BUF_SWAP_32BIT
|
RB_NO_UPDATE
|
(
drm_order
(
4096
/
8
)
<<
8
)
|
rb_bufsz
);
#else
WREG32
(
CP_RB_CNTL
,
RB_NO_UPDATE
|
(
drm_order
(
4096
/
8
)
<<
8
)
|
rb_bufsz
);
tmp
|=
BUF_SWAP_32BIT
;
#endif
WREG32
(
CP_RB_CNTL
,
tmp
);
WREG32
(
CP_SEM_WAIT_TIMER
,
0x4
);
/* Set the write pointer delay */
WREG32
(
CP_RB_WPTR_DELAY
,
0
);
/* Initialize the ring buffer's read and write pointers */
tmp
=
RREG32
(
CP_RB_CNTL
);
WREG32
(
CP_RB_CNTL
,
tmp
|
RB_RPTR_WR_ENA
);
WREG32
(
CP_RB_RPTR_WR
,
0
);
WREG32
(
CP_RB_WPTR
,
0
);
...
...
@@ -1400,7 +1397,7 @@ int r600_wb_enable(struct radeon_device *rdev)
int
r
;
if
(
rdev
->
wb
.
wb_obj
==
NULL
)
{
r
=
radeon_object_create
(
rdev
,
NULL
,
4096
,
true
,
r
=
radeon_object_create
(
rdev
,
NULL
,
RADEON_GPU_PAGE_SIZE
,
true
,
RADEON_GEM_DOMAIN_GTT
,
false
,
&
rdev
->
wb
.
wb_obj
);
if
(
r
)
{
dev_warn
(
rdev
->
dev
,
"failed to create WB buffer (%d).
\n
"
,
r
);
...
...
@@ -1450,8 +1447,8 @@ int r600_copy_blit(struct radeon_device *rdev,
uint64_t
src_offset
,
uint64_t
dst_offset
,
unsigned
num_pages
,
struct
radeon_fence
*
fence
)
{
r600_blit_prepare_copy
(
rdev
,
num_pages
*
4096
);
r600_kms_blit_copy
(
rdev
,
src_offset
,
dst_offset
,
num_pages
*
4096
);
r600_blit_prepare_copy
(
rdev
,
num_pages
*
RADEON_GPU_PAGE_SIZE
);
r600_kms_blit_copy
(
rdev
,
src_offset
,
dst_offset
,
num_pages
*
RADEON_GPU_PAGE_SIZE
);
r600_blit_done_copy
(
rdev
,
fence
);
return
0
;
}
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r600_blit.c
浏览文件 @
5b8f0be0
...
...
@@ -582,6 +582,8 @@ r600_blit_copy(struct drm_device *dev,
u64
vb_addr
;
u32
*
vb
;
vb
=
r600_nomm_get_vb_ptr
(
dev
);
if
((
size_bytes
&
3
)
||
(
src_gpu_addr
&
3
)
||
(
dst_gpu_addr
&
3
))
{
max_bytes
=
8192
;
...
...
@@ -617,8 +619,8 @@ r600_blit_copy(struct drm_device *dev,
if
(
!
dev_priv
->
blit_vb
)
return
;
set_shaders
(
dev
);
vb
=
r600_nomm_get_vb_ptr
(
dev
);
}
vb
=
r600_nomm_get_vb_ptr
(
dev
);
vb
[
0
]
=
i2f
(
dst_x
);
vb
[
1
]
=
0
;
...
...
@@ -706,8 +708,8 @@ r600_blit_copy(struct drm_device *dev,
return
;
set_shaders
(
dev
);
vb
=
r600_nomm_get_vb_ptr
(
dev
);
}
vb
=
r600_nomm_get_vb_ptr
(
dev
);
vb
[
0
]
=
i2f
(
dst_x
/
4
);
vb
[
1
]
=
0
;
...
...
@@ -772,6 +774,7 @@ r600_blit_swap(struct drm_device *dev,
{
drm_radeon_private_t
*
dev_priv
=
dev
->
dev_private
;
int
cb_format
,
tex_format
;
int
sx2
,
sy2
,
dx2
,
dy2
;
u64
vb_addr
;
u32
*
vb
;
...
...
@@ -786,16 +789,10 @@ r600_blit_swap(struct drm_device *dev,
}
vb
=
r600_nomm_get_vb_ptr
(
dev
);
if
(
cpp
==
4
)
{
cb_format
=
COLOR_8_8_8_8
;
tex_format
=
FMT_8_8_8_8
;
}
else
if
(
cpp
==
2
)
{
cb_format
=
COLOR_5_6_5
;
tex_format
=
FMT_5_6_5
;
}
else
{
cb_format
=
COLOR_8
;
tex_format
=
FMT_8
;
}
sx2
=
sx
+
w
;
sy2
=
sy
+
h
;
dx2
=
dx
+
w
;
dy2
=
dy
+
h
;
vb
[
0
]
=
i2f
(
dx
);
vb
[
1
]
=
i2f
(
dy
);
...
...
@@ -803,31 +800,46 @@ r600_blit_swap(struct drm_device *dev,
vb
[
3
]
=
i2f
(
sy
);
vb
[
4
]
=
i2f
(
dx
);
vb
[
5
]
=
i2f
(
dy
+
h
);
vb
[
5
]
=
i2f
(
dy
2
);
vb
[
6
]
=
i2f
(
sx
);
vb
[
7
]
=
i2f
(
sy
+
h
);
vb
[
7
]
=
i2f
(
sy2
);
vb
[
8
]
=
i2f
(
dx2
);
vb
[
9
]
=
i2f
(
dy2
);
vb
[
10
]
=
i2f
(
sx2
);
vb
[
11
]
=
i2f
(
sy2
);
vb
[
8
]
=
i2f
(
dx
+
w
);
vb
[
9
]
=
i2f
(
dy
+
h
);
vb
[
10
]
=
i2f
(
sx
+
w
);
vb
[
11
]
=
i2f
(
sy
+
h
);
switch
(
cpp
)
{
case
4
:
cb_format
=
COLOR_8_8_8_8
;
tex_format
=
FMT_8_8_8_8
;
break
;
case
2
:
cb_format
=
COLOR_5_6_5
;
tex_format
=
FMT_5_6_5
;
break
;
default:
cb_format
=
COLOR_8
;
tex_format
=
FMT_8
;
break
;
}
/* src */
set_tex_resource
(
dev_priv
,
tex_format
,
src_pitch
/
cpp
,
sy
+
h
,
src_pitch
/
cpp
,
sy
2
,
src_pitch
/
cpp
,
src_gpu_addr
);
cp_set_surface_sync
(
dev_priv
,
R600_TC_ACTION_ENA
,
(
src_pitch
*
(
sy
+
h
))
,
src_gpu_addr
);
R600_TC_ACTION_ENA
,
src_pitch
*
sy2
,
src_gpu_addr
);
/* dst */
set_render_target
(
dev_priv
,
cb_format
,
dst_pitch
/
cpp
,
dy
+
h
,
dst_pitch
/
cpp
,
dy
2
,
dst_gpu_addr
);
/* scissors */
set_scissors
(
dev_priv
,
dx
,
dy
,
dx
+
w
,
dy
+
h
);
set_scissors
(
dev_priv
,
dx
,
dy
,
dx
2
,
dy2
);
/* Vertex buffer setup */
vb_addr
=
dev_priv
->
gart_buffers_offset
+
...
...
@@ -840,7 +852,7 @@ r600_blit_swap(struct drm_device *dev,
cp_set_surface_sync
(
dev_priv
,
R600_CB_ACTION_ENA
|
R600_CB0_DEST_BASE_ENA
,
dst_pitch
*
(
dy
+
h
)
,
dst_gpu_addr
);
dst_pitch
*
dy2
,
dst_gpu_addr
);
dev_priv
->
blit_vb
->
used
+=
12
*
4
;
}
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r600_blit_kms.c
浏览文件 @
5b8f0be0
...
...
@@ -610,6 +610,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
DRM_DEBUG
(
"emitting copy %16llx %16llx %d %d
\n
"
,
src_gpu_addr
,
dst_gpu_addr
,
size_bytes
,
rdev
->
r600_blit
.
vb_used
);
vb
=
(
u32
*
)(
rdev
->
r600_blit
.
vb_ib
->
ptr
+
rdev
->
r600_blit
.
vb_used
);
if
((
size_bytes
&
3
)
||
(
src_gpu_addr
&
3
)
||
(
dst_gpu_addr
&
3
))
{
max_bytes
=
8192
;
...
...
@@ -652,7 +653,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
vb = r600_nomm_get_vb_ptr(dev);
#endif
}
vb
=
(
u32
*
)(
rdev
->
r600_blit
.
vb_ib
->
ptr
+
rdev
->
r600_blit
.
vb_used
);
vb
[
0
]
=
i2f
(
dst_x
);
vb
[
1
]
=
0
;
...
...
@@ -747,7 +747,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
vb = r600_nomm_get_vb_ptr(dev);
}
#endif
vb
=
(
u32
*
)(
rdev
->
r600_blit
.
vb_ib
->
ptr
+
rdev
->
r600_blit
.
vb_used
);
vb
[
0
]
=
i2f
(
dst_x
/
4
);
vb
[
1
]
=
0
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/r600d.h
浏览文件 @
5b8f0be0
...
...
@@ -271,6 +271,10 @@
#define PCIE_PORT_INDEX 0x0038
#define PCIE_PORT_DATA 0x003C
#define CHMAP 0x2004
#define NOOFCHAN_SHIFT 12
#define NOOFCHAN_MASK 0x00003000
#define RAMCFG 0x2408
#define NOOFBANK_SHIFT 0
#define NOOFBANK_MASK 0x00000001
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon.h
浏览文件 @
5b8f0be0
...
...
@@ -276,6 +276,8 @@ union radeon_gart_table {
struct
radeon_gart_table_vram
vram
;
};
#define RADEON_GPU_PAGE_SIZE 4096
struct
radeon_gart
{
dma_addr_t
table_addr
;
unsigned
num_gpu_pages
;
...
...
@@ -783,6 +785,7 @@ struct radeon_device {
const
struct
firmware
*
me_fw
;
/* all family ME firmware */
const
struct
firmware
*
pfp_fw
;
/* r6/700 PFP firmware */
struct
r600_blit
r600_blit
;
int
msi_enabled
;
/* msi enabled */
};
int
radeon_device_init
(
struct
radeon_device
*
rdev
,
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_atombios.c
浏览文件 @
5b8f0be0
...
...
@@ -641,8 +641,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
le16_to_cpu
(
firmware_info
->
info
.
usReferenceClock
);
p1pll
->
reference_div
=
0
;
p1pll
->
pll_out_min
=
le16_to_cpu
(
firmware_info
->
info
.
usMinPixelClockPLL_Output
);
if
(
crev
<
2
)
p1pll
->
pll_out_min
=
le16_to_cpu
(
firmware_info
->
info
.
usMinPixelClockPLL_Output
);
else
p1pll
->
pll_out_min
=
le32_to_cpu
(
firmware_info
->
info_12
.
ulMinPixelClockPLL_Output
);
p1pll
->
pll_out_max
=
le32_to_cpu
(
firmware_info
->
info
.
ulMaxPixelClockPLL_Output
);
...
...
@@ -651,6 +655,16 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
p1pll
->
pll_out_min
=
64800
;
else
p1pll
->
pll_out_min
=
20000
;
}
else
if
(
p1pll
->
pll_out_min
>
64800
)
{
/* Limiting the pll output range is a good thing generally as
* it limits the number of possible pll combinations for a given
* frequency presumably to the ones that work best on each card.
* However, certain duallink DVI monitors seem to like
* pll combinations that would be limited by this at least on
* pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
* family.
*/
p1pll
->
pll_out_min
=
64800
;
}
p1pll
->
pll_in_min
=
...
...
@@ -767,6 +781,46 @@ bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
return
false
;
}
static
struct
radeon_atom_ss
*
radeon_atombios_get_ss_info
(
struct
radeon_encoder
*
encoder
,
int
id
)
{
struct
drm_device
*
dev
=
encoder
->
base
.
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
struct
radeon_mode_info
*
mode_info
=
&
rdev
->
mode_info
;
int
index
=
GetIndexIntoMasterTable
(
DATA
,
PPLL_SS_Info
);
uint16_t
data_offset
;
struct
_ATOM_SPREAD_SPECTRUM_INFO
*
ss_info
;
uint8_t
frev
,
crev
;
struct
radeon_atom_ss
*
ss
=
NULL
;
if
(
id
>
ATOM_MAX_SS_ENTRY
)
return
NULL
;
atom_parse_data_header
(
mode_info
->
atom_context
,
index
,
NULL
,
&
frev
,
&
crev
,
&
data_offset
);
ss_info
=
(
struct
_ATOM_SPREAD_SPECTRUM_INFO
*
)(
mode_info
->
atom_context
->
bios
+
data_offset
);
if
(
ss_info
)
{
ss
=
kzalloc
(
sizeof
(
struct
radeon_atom_ss
),
GFP_KERNEL
);
if
(
!
ss
)
return
NULL
;
ss
->
percentage
=
le16_to_cpu
(
ss_info
->
asSS_Info
[
id
].
usSpreadSpectrumPercentage
);
ss
->
type
=
ss_info
->
asSS_Info
[
id
].
ucSpreadSpectrumType
;
ss
->
step
=
ss_info
->
asSS_Info
[
id
].
ucSS_Step
;
ss
->
delay
=
ss_info
->
asSS_Info
[
id
].
ucSS_Delay
;
ss
->
range
=
ss_info
->
asSS_Info
[
id
].
ucSS_Range
;
ss
->
refdiv
=
ss_info
->
asSS_Info
[
id
].
ucRecommendedRef_Div
;
}
return
ss
;
}
union
lvds_info
{
struct
_ATOM_LVDS_INFO
info
;
struct
_ATOM_LVDS_INFO_V12
info_12
;
...
...
@@ -798,27 +852,31 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
if
(
!
lvds
)
return
NULL
;
lvds
->
native_mode
.
dot
clock
=
lvds
->
native_mode
.
clock
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usPixClk
)
*
10
;
lvds
->
native_mode
.
panel_xres
=
lvds
->
native_mode
.
hdisplay
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHActive
);
lvds
->
native_mode
.
panel_yres
=
lvds
->
native_mode
.
vdisplay
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVActive
);
lvds
->
native_mode
.
h
blank
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHBlanking_Time
);
lvds
->
native_mode
.
h
overplus
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHSyncOffset
);
lvds
->
native_mode
.
hsync_
width
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHSyncWidth
);
lvds
->
native_mode
.
v
blank
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVBlanking_Time
);
lvds
->
native_mode
.
v
overplus
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVSyncOffset
);
lvds
->
native_mode
.
vsync_
width
=
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVSyncWidth
);
lvds
->
native_mode
.
h
total
=
lvds
->
native_mode
.
hdisplay
+
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHBlanking_Time
);
lvds
->
native_mode
.
h
sync_start
=
lvds
->
native_mode
.
hdisplay
+
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHSyncOffset
);
lvds
->
native_mode
.
hsync_
end
=
lvds
->
native_mode
.
hsync_start
+
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usHSyncWidth
);
lvds
->
native_mode
.
v
total
=
lvds
->
native_mode
.
vdisplay
+
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVBlanking_Time
);
lvds
->
native_mode
.
v
sync_start
=
lvds
->
native_mode
.
vdisplay
+
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVSyncWidth
);
lvds
->
native_mode
.
vsync_
end
=
lvds
->
native_mode
.
vsync_start
+
le16_to_cpu
(
lvds_info
->
info
.
sLCDTiming
.
usVSyncWidth
);
lvds
->
panel_pwr_delay
=
le16_to_cpu
(
lvds_info
->
info
.
usOffDelayInMs
);
lvds
->
lvds_misc
=
lvds_info
->
info
.
ucLVDS_Misc
;
/* set crtc values */
drm_mode_set_crtcinfo
(
&
lvds
->
native_mode
,
CRTC_INTERLACE_HALVE_V
);
lvds
->
ss
=
radeon_atombios_get_ss_info
(
encoder
,
lvds_info
->
info
.
ucSS_Id
);
encoder
->
native_mode
=
lvds
->
native_mode
;
}
...
...
@@ -857,8 +915,7 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
}
bool
radeon_atom_get_tv_timings
(
struct
radeon_device
*
rdev
,
int
index
,
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION
*
crtc_timing
,
int32_t
*
pixel_clock
)
struct
drm_display_mode
*
mode
)
{
struct
radeon_mode_info
*
mode_info
=
&
rdev
->
mode_info
;
ATOM_ANALOG_TV_INFO
*
tv_info
;
...
...
@@ -866,7 +923,7 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
ATOM_DTD_FORMAT
*
dtd_timings
;
int
data_index
=
GetIndexIntoMasterTable
(
DATA
,
AnalogTV_Info
);
u8
frev
,
crev
;
u
int16_t
data_offset
;
u
16
data_offset
,
misc
;
atom_parse_data_header
(
mode_info
->
atom_context
,
data_index
,
NULL
,
&
frev
,
&
crev
,
&
data_offset
);
...
...
@@ -876,28 +933,37 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
if
(
index
>
MAX_SUPPORTED_TV_TIMING
)
return
false
;
crtc_timing
->
usH_Total
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_Total
);
crtc_timing
->
usH_Disp
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_Disp
);
crtc_timing
->
usH_SyncStart
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_SyncStart
);
crtc_timing
->
usH_SyncWidth
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_SyncWidth
);
crtc_timing
->
usV_Total
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_Total
);
crtc_timing
->
usV_Disp
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_Disp
);
crtc_timing
->
usV_SyncStart
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_SyncStart
);
crtc_timing
->
usV_SyncWidth
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_SyncWidth
);
crtc_timing
->
susModeMiscInfo
=
tv_info
->
aModeTimings
[
index
].
susModeMiscInfo
;
crtc_timing
->
ucOverscanRight
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_OverscanRight
);
crtc_timing
->
ucOverscanLeft
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_OverscanLeft
);
crtc_timing
->
ucOverscanBottom
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_OverscanBottom
);
crtc_timing
->
ucOverscanTop
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_OverscanTop
);
*
pixel_clock
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usPixelClock
)
*
10
;
mode
->
crtc_htotal
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_Total
);
mode
->
crtc_hdisplay
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_Disp
);
mode
->
crtc_hsync_start
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_SyncStart
);
mode
->
crtc_hsync_end
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_SyncStart
)
+
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_H_SyncWidth
);
mode
->
crtc_vtotal
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_Total
);
mode
->
crtc_vdisplay
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_Disp
);
mode
->
crtc_vsync_start
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_SyncStart
);
mode
->
crtc_vsync_end
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_SyncStart
)
+
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usCRTC_V_SyncWidth
);
mode
->
flags
=
0
;
misc
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
susModeMiscInfo
.
usAccess
);
if
(
misc
&
ATOM_VSYNC_POLARITY
)
mode
->
flags
|=
DRM_MODE_FLAG_NVSYNC
;
if
(
misc
&
ATOM_HSYNC_POLARITY
)
mode
->
flags
|=
DRM_MODE_FLAG_NHSYNC
;
if
(
misc
&
ATOM_COMPOSITESYNC
)
mode
->
flags
|=
DRM_MODE_FLAG_CSYNC
;
if
(
misc
&
ATOM_INTERLACE
)
mode
->
flags
|=
DRM_MODE_FLAG_INTERLACE
;
if
(
misc
&
ATOM_DOUBLE_CLOCK_MODE
)
mode
->
flags
|=
DRM_MODE_FLAG_DBLSCAN
;
mode
->
clock
=
le16_to_cpu
(
tv_info
->
aModeTimings
[
index
].
usPixelClock
)
*
10
;
if
(
index
==
1
)
{
/* PAL timings appear to have wrong values for totals */
crtc_timing
->
usH_T
otal
-=
1
;
crtc_timing
->
usV_T
otal
-=
1
;
mode
->
crtc_ht
otal
-=
1
;
mode
->
crtc_vt
otal
-=
1
;
}
break
;
case
2
:
...
...
@@ -906,17 +972,36 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
return
false
;
dtd_timings
=
&
tv_info_v1_2
->
aModeTimings
[
index
];
crtc_timing
->
usH_Total
=
le16_to_cpu
(
dtd_timings
->
usHActive
)
+
le16_to_cpu
(
dtd_timings
->
usHBlanking_Time
);
crtc_timing
->
usH_Disp
=
le16_to_cpu
(
dtd_timings
->
usHActive
);
crtc_timing
->
usH_SyncStart
=
le16_to_cpu
(
dtd_timings
->
usHActive
)
+
le16_to_cpu
(
dtd_timings
->
usHSyncOffset
);
crtc_timing
->
usH_SyncWidth
=
le16_to_cpu
(
dtd_timings
->
usHSyncWidth
);
crtc_timing
->
usV_Total
=
le16_to_cpu
(
dtd_timings
->
usVActive
)
+
le16_to_cpu
(
dtd_timings
->
usVBlanking_Time
);
crtc_timing
->
usV_Disp
=
le16_to_cpu
(
dtd_timings
->
usVActive
);
crtc_timing
->
usV_SyncStart
=
le16_to_cpu
(
dtd_timings
->
usVActive
)
+
le16_to_cpu
(
dtd_timings
->
usVSyncOffset
);
crtc_timing
->
usV_SyncWidth
=
le16_to_cpu
(
dtd_timings
->
usVSyncWidth
);
crtc_timing
->
susModeMiscInfo
.
usAccess
=
le16_to_cpu
(
dtd_timings
->
susModeMiscInfo
.
usAccess
);
*
pixel_clock
=
le16_to_cpu
(
dtd_timings
->
usPixClk
)
*
10
;
mode
->
crtc_htotal
=
le16_to_cpu
(
dtd_timings
->
usHActive
)
+
le16_to_cpu
(
dtd_timings
->
usHBlanking_Time
);
mode
->
crtc_hdisplay
=
le16_to_cpu
(
dtd_timings
->
usHActive
);
mode
->
crtc_hsync_start
=
le16_to_cpu
(
dtd_timings
->
usHActive
)
+
le16_to_cpu
(
dtd_timings
->
usHSyncOffset
);
mode
->
crtc_hsync_end
=
mode
->
crtc_hsync_start
+
le16_to_cpu
(
dtd_timings
->
usHSyncWidth
);
mode
->
crtc_vtotal
=
le16_to_cpu
(
dtd_timings
->
usVActive
)
+
le16_to_cpu
(
dtd_timings
->
usVBlanking_Time
);
mode
->
crtc_vdisplay
=
le16_to_cpu
(
dtd_timings
->
usVActive
);
mode
->
crtc_vsync_start
=
le16_to_cpu
(
dtd_timings
->
usVActive
)
+
le16_to_cpu
(
dtd_timings
->
usVSyncOffset
);
mode
->
crtc_vsync_end
=
mode
->
crtc_vsync_start
+
le16_to_cpu
(
dtd_timings
->
usVSyncWidth
);
mode
->
flags
=
0
;
misc
=
le16_to_cpu
(
dtd_timings
->
susModeMiscInfo
.
usAccess
);
if
(
misc
&
ATOM_VSYNC_POLARITY
)
mode
->
flags
|=
DRM_MODE_FLAG_NVSYNC
;
if
(
misc
&
ATOM_HSYNC_POLARITY
)
mode
->
flags
|=
DRM_MODE_FLAG_NHSYNC
;
if
(
misc
&
ATOM_COMPOSITESYNC
)
mode
->
flags
|=
DRM_MODE_FLAG_CSYNC
;
if
(
misc
&
ATOM_INTERLACE
)
mode
->
flags
|=
DRM_MODE_FLAG_INTERLACE
;
if
(
misc
&
ATOM_DOUBLE_CLOCK_MODE
)
mode
->
flags
|=
DRM_MODE_FLAG_DBLSCAN
;
mode
->
clock
=
le16_to_cpu
(
dtd_timings
->
usPixClk
)
*
10
;
break
;
}
return
true
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_benchmark.c
浏览文件 @
5b8f0be0
...
...
@@ -63,7 +63,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
if
(
r
)
{
goto
out_cleanup
;
}
r
=
radeon_copy_dma
(
rdev
,
saddr
,
daddr
,
size
/
4096
,
fence
);
r
=
radeon_copy_dma
(
rdev
,
saddr
,
daddr
,
size
/
RADEON_GPU_PAGE_SIZE
,
fence
);
if
(
r
)
{
goto
out_cleanup
;
}
...
...
@@ -88,7 +88,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
if
(
r
)
{
goto
out_cleanup
;
}
r
=
radeon_copy_blit
(
rdev
,
saddr
,
daddr
,
size
/
4096
,
fence
);
r
=
radeon_copy_blit
(
rdev
,
saddr
,
daddr
,
size
/
RADEON_GPU_PAGE_SIZE
,
fence
);
if
(
r
)
{
goto
out_cleanup
;
}
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_bios.c
浏览文件 @
5b8f0be0
...
...
@@ -50,19 +50,16 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
vram_base
=
drm_get_resource_start
(
rdev
->
ddev
,
0
);
bios
=
ioremap
(
vram_base
,
size
);
if
(
!
bios
)
{
DRM_ERROR
(
"Unable to mmap vram
\n
"
);
return
false
;
}
if
(
size
==
0
||
bios
[
0
]
!=
0x55
||
bios
[
1
]
!=
0xaa
)
{
iounmap
(
bios
);
DRM_ERROR
(
"bad rom signature
\n
"
);
return
false
;
}
rdev
->
bios
=
kmalloc
(
size
,
GFP_KERNEL
);
if
(
rdev
->
bios
==
NULL
)
{
iounmap
(
bios
);
DRM_ERROR
(
"kmalloc failed
\n
"
);
return
false
;
}
memcpy
(
rdev
->
bios
,
bios
,
size
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_combios.c
浏览文件 @
5b8f0be0
...
...
@@ -808,25 +808,25 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
lvds
->
panel_blon_delay
=
(
lvds_ss_gen_cntl
>>
RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
)
&
0xf
;
if
(
fp_vert_stretch
&
RADEON_VERT_STRETCH_ENABLE
)
lvds
->
native_mode
.
panel_yres
=
lvds
->
native_mode
.
vdisplay
=
((
fp_vert_stretch
&
RADEON_VERT_PANEL_SIZE
)
>>
RADEON_VERT_PANEL_SHIFT
)
+
1
;
else
lvds
->
native_mode
.
panel_yres
=
lvds
->
native_mode
.
vdisplay
=
(
RREG32
(
RADEON_CRTC_V_TOTAL_DISP
)
>>
16
)
+
1
;
if
(
fp_horz_stretch
&
RADEON_HORZ_STRETCH_ENABLE
)
lvds
->
native_mode
.
panel_xres
=
lvds
->
native_mode
.
hdisplay
=
(((
fp_horz_stretch
&
RADEON_HORZ_PANEL_SIZE
)
>>
RADEON_HORZ_PANEL_SHIFT
)
+
1
)
*
8
;
else
lvds
->
native_mode
.
panel_xres
=
lvds
->
native_mode
.
hdisplay
=
((
RREG32
(
RADEON_CRTC_H_TOTAL_DISP
)
>>
16
)
+
1
)
*
8
;
if
((
lvds
->
native_mode
.
panel_xres
<
640
)
||
(
lvds
->
native_mode
.
panel_yres
<
480
))
{
lvds
->
native_mode
.
panel_xres
=
640
;
lvds
->
native_mode
.
panel_yres
=
480
;
if
((
lvds
->
native_mode
.
hdisplay
<
640
)
||
(
lvds
->
native_mode
.
vdisplay
<
480
))
{
lvds
->
native_mode
.
hdisplay
=
640
;
lvds
->
native_mode
.
vdisplay
=
480
;
}
ppll_div_sel
=
RREG8
(
RADEON_CLOCK_CNTL_INDEX
+
1
)
&
0x3
;
...
...
@@ -846,8 +846,8 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
lvds
->
panel_vcc_delay
=
200
;
DRM_INFO
(
"Panel info derived from registers
\n
"
);
DRM_INFO
(
"Panel Size %dx%d
\n
"
,
lvds
->
native_mode
.
panel_xres
,
lvds
->
native_mode
.
panel_yres
);
DRM_INFO
(
"Panel Size %dx%d
\n
"
,
lvds
->
native_mode
.
hdisplay
,
lvds
->
native_mode
.
vdisplay
);
return
lvds
;
}
...
...
@@ -882,11 +882,11 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
DRM_INFO
(
"Panel ID String: %s
\n
"
,
stmp
);
lvds
->
native_mode
.
panel_xres
=
RBIOS16
(
lcd_info
+
0x19
);
lvds
->
native_mode
.
panel_yres
=
RBIOS16
(
lcd_info
+
0x1b
);
lvds
->
native_mode
.
hdisplay
=
RBIOS16
(
lcd_info
+
0x19
);
lvds
->
native_mode
.
vdisplay
=
RBIOS16
(
lcd_info
+
0x1b
);
DRM_INFO
(
"Panel Size %dx%d
\n
"
,
lvds
->
native_mode
.
panel_xres
,
lvds
->
native_mode
.
panel_yres
);
DRM_INFO
(
"Panel Size %dx%d
\n
"
,
lvds
->
native_mode
.
hdisplay
,
lvds
->
native_mode
.
vdisplay
);
lvds
->
panel_vcc_delay
=
RBIOS16
(
lcd_info
+
0x2c
);
if
(
lvds
->
panel_vcc_delay
>
2000
||
lvds
->
panel_vcc_delay
<
0
)
...
...
@@ -944,27 +944,25 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
if
(
tmp
==
0
)
break
;
if
((
RBIOS16
(
tmp
)
==
lvds
->
native_mode
.
panel_xres
)
&&
if
((
RBIOS16
(
tmp
)
==
lvds
->
native_mode
.
hdisplay
)
&&
(
RBIOS16
(
tmp
+
2
)
==
lvds
->
native_mode
.
panel_yres
))
{
lvds
->
native_mode
.
hblank
=
(
RBIOS16
(
tmp
+
17
)
-
RBIOS16
(
tmp
+
19
))
*
8
;
lvds
->
native_mode
.
hoverplus
=
(
RBIOS16
(
tmp
+
21
)
-
RBIOS16
(
tmp
+
19
)
-
1
)
*
8
;
lvds
->
native_mode
.
hsync_width
=
RBIOS8
(
tmp
+
23
)
*
8
;
lvds
->
native_mode
.
vblank
=
(
RBIOS16
(
tmp
+
24
)
-
RBIOS16
(
tmp
+
26
));
lvds
->
native_mode
.
voverplus
=
((
RBIOS16
(
tmp
+
28
)
&
0x7ff
)
-
RBIOS16
(
tmp
+
26
));
lvds
->
native_mode
.
vsync_width
=
((
RBIOS16
(
tmp
+
28
)
&
0xf800
)
>>
11
);
lvds
->
native_mode
.
dotclock
=
RBIOS16
(
tmp
+
9
)
*
10
;
lvds
->
native_mode
.
vdisplay
))
{
lvds
->
native_mode
.
htotal
=
RBIOS16
(
tmp
+
17
)
*
8
;
lvds
->
native_mode
.
hsync_start
=
RBIOS16
(
tmp
+
21
)
*
8
;
lvds
->
native_mode
.
hsync_end
=
(
RBIOS8
(
tmp
+
23
)
+
RBIOS16
(
tmp
+
21
))
*
8
;
lvds
->
native_mode
.
vtotal
=
RBIOS16
(
tmp
+
24
);
lvds
->
native_mode
.
vsync_start
=
RBIOS16
(
tmp
+
28
)
&
0x7ff
;
lvds
->
native_mode
.
vsync_end
=
((
RBIOS16
(
tmp
+
28
)
&
0xf800
)
>>
11
)
+
(
RBIOS16
(
tmp
+
28
)
&
0x7ff
);
lvds
->
native_mode
.
clock
=
RBIOS16
(
tmp
+
9
)
*
10
;
lvds
->
native_mode
.
flags
=
0
;
/* set crtc values */
drm_mode_set_crtcinfo
(
&
lvds
->
native_mode
,
CRTC_INTERLACE_HALVE_V
);
}
}
}
else
{
...
...
@@ -1581,6 +1579,23 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
return
true
;
}
static
bool
radeon_apply_legacy_tv_quirks
(
struct
drm_device
*
dev
)
{
/* Acer 5102 has non-existent TV port */
if
(
dev
->
pdev
->
device
==
0x5975
&&
dev
->
pdev
->
subsystem_vendor
==
0x1025
&&
dev
->
pdev
->
subsystem_device
==
0x009f
)
return
false
;
/* HP dc5750 has non-existent TV port */
if
(
dev
->
pdev
->
device
==
0x5974
&&
dev
->
pdev
->
subsystem_vendor
==
0x103c
&&
dev
->
pdev
->
subsystem_device
==
0x280a
)
return
false
;
return
true
;
}
bool
radeon_get_legacy_connector_info_from_bios
(
struct
drm_device
*
dev
)
{
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
...
...
@@ -1628,8 +1643,9 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
break
;
}
radeon_apply_legacy_quirks
(
dev
,
i
,
&
connector
,
&
ddc_i2c
);
if
(
!
radeon_apply_legacy_quirks
(
dev
,
i
,
&
connector
,
&
ddc_i2c
))
continue
;
switch
(
connector
)
{
case
CONNECTOR_PROPRIETARY_LEGACY
:
...
...
@@ -1774,8 +1790,25 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
DRM_MODE_CONNECTOR_DVII
,
&
ddc_i2c
);
}
else
{
DRM_DEBUG
(
"No connector info found
\n
"
);
return
false
;
uint16_t
crt_info
=
combios_get_table_offset
(
dev
,
COMBIOS_CRT_INFO_TABLE
);
DRM_DEBUG
(
"Found CRT table, assuming VGA connector
\n
"
);
if
(
crt_info
)
{
radeon_add_legacy_encoder
(
dev
,
radeon_get_encoder_id
(
dev
,
ATOM_DEVICE_CRT1_SUPPORT
,
1
),
ATOM_DEVICE_CRT1_SUPPORT
);
ddc_i2c
=
combios_setup_i2c_bus
(
RADEON_GPIO_VGA_DDC
);
radeon_add_legacy_connector
(
dev
,
0
,
ATOM_DEVICE_CRT1_SUPPORT
,
DRM_MODE_CONNECTOR_VGA
,
&
ddc_i2c
);
}
else
{
DRM_DEBUG
(
"No connector info found
\n
"
);
return
false
;
}
}
}
...
...
@@ -1880,16 +1913,18 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
combios_get_table_offset
(
dev
,
COMBIOS_TV_INFO_TABLE
);
if
(
tv_info
)
{
if
(
RBIOS8
(
tv_info
+
6
)
==
'T'
)
{
radeon_add_legacy_encoder
(
dev
,
radeon_get_encoder_id
(
dev
,
ATOM_DEVICE_TV1_SUPPORT
,
2
),
ATOM_DEVICE_TV1_SUPPORT
);
radeon_add_legacy_connector
(
dev
,
6
,
ATOM_DEVICE_TV1_SUPPORT
,
DRM_MODE_CONNECTOR_SVIDEO
,
&
ddc_i2c
);
if
(
radeon_apply_legacy_tv_quirks
(
dev
))
{
radeon_add_legacy_encoder
(
dev
,
radeon_get_encoder_id
(
dev
,
ATOM_DEVICE_TV1_SUPPORT
,
2
),
ATOM_DEVICE_TV1_SUPPORT
);
radeon_add_legacy_connector
(
dev
,
6
,
ATOM_DEVICE_TV1_SUPPORT
,
DRM_MODE_CONNECTOR_SVIDEO
,
&
ddc_i2c
);
}
}
}
}
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_connectors.c
浏览文件 @
5b8f0be0
...
...
@@ -178,25 +178,12 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
struct
drm_device
*
dev
=
encoder
->
dev
;
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
struct
drm_display_mode
*
mode
=
NULL
;
struct
radeon_native_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
if
(
native_mode
->
panel_xres
!=
0
&&
native_mode
->
panel_yres
!=
0
&&
native_mode
->
dotclock
!=
0
)
{
mode
=
drm_mode_create
(
dev
);
mode
->
hdisplay
=
native_mode
->
panel_xres
;
mode
->
vdisplay
=
native_mode
->
panel_yres
;
mode
->
htotal
=
mode
->
hdisplay
+
native_mode
->
hblank
;
mode
->
hsync_start
=
mode
->
hdisplay
+
native_mode
->
hoverplus
;
mode
->
hsync_end
=
mode
->
hsync_start
+
native_mode
->
hsync_width
;
mode
->
vtotal
=
mode
->
vdisplay
+
native_mode
->
vblank
;
mode
->
vsync_start
=
mode
->
vdisplay
+
native_mode
->
voverplus
;
mode
->
vsync_end
=
mode
->
vsync_start
+
native_mode
->
vsync_width
;
mode
->
clock
=
native_mode
->
dotclock
;
mode
->
flags
=
0
;
struct
drm_display_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
if
(
native_mode
->
hdisplay
!=
0
&&
native_mode
->
vdisplay
!=
0
&&
native_mode
->
clock
!=
0
)
{
mode
=
drm_mode_duplicate
(
dev
,
native_mode
);
mode
->
type
=
DRM_MODE_TYPE_PREFERRED
|
DRM_MODE_TYPE_DRIVER
;
drm_mode_set_name
(
mode
);
...
...
@@ -210,7 +197,7 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
struct
drm_device
*
dev
=
encoder
->
dev
;
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
struct
drm_display_mode
*
mode
=
NULL
;
struct
radeon_native
_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
struct
drm_display
_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
int
i
;
struct
mode_size
{
int
w
;
...
...
@@ -236,11 +223,16 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
};
for
(
i
=
0
;
i
<
17
;
i
++
)
{
if
(
radeon_encoder
->
devices
&
(
ATOM_DEVICE_TV_SUPPORT
))
{
if
(
common_modes
[
i
].
w
>
1024
||
common_modes
[
i
].
h
>
768
)
continue
;
}
if
(
radeon_encoder
->
devices
&
(
ATOM_DEVICE_LCD_SUPPORT
))
{
if
(
common_modes
[
i
].
w
>
native_mode
->
panel_xres
||
common_modes
[
i
].
h
>
native_mode
->
panel_yres
||
(
common_modes
[
i
].
w
==
native_mode
->
panel_xres
&&
common_modes
[
i
].
h
==
native_mode
->
panel_yres
))
if
(
common_modes
[
i
].
w
>
native_mode
->
hdisplay
||
common_modes
[
i
].
h
>
native_mode
->
vdisplay
||
(
common_modes
[
i
].
w
==
native_mode
->
hdisplay
&&
common_modes
[
i
].
h
==
native_mode
->
vdisplay
))
continue
;
}
if
(
common_modes
[
i
].
w
<
320
||
common_modes
[
i
].
h
<
200
)
...
...
@@ -344,28 +336,23 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
struct
drm_connector
*
connector
)
{
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
struct
radeon_native
_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
struct
drm_display
_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
/* Try to get native mode details from EDID if necessary */
if
(
!
native_mode
->
dot
clock
)
{
if
(
!
native_mode
->
clock
)
{
struct
drm_display_mode
*
t
,
*
mode
;
list_for_each_entry_safe
(
mode
,
t
,
&
connector
->
probed_modes
,
head
)
{
if
(
mode
->
hdisplay
==
native_mode
->
panel_xres
&&
mode
->
vdisplay
==
native_mode
->
panel_yres
)
{
native_mode
->
hblank
=
mode
->
htotal
-
mode
->
hdisplay
;
native_mode
->
hoverplus
=
mode
->
hsync_start
-
mode
->
hdisplay
;
native_mode
->
hsync_width
=
mode
->
hsync_end
-
mode
->
hsync_start
;
native_mode
->
vblank
=
mode
->
vtotal
-
mode
->
vdisplay
;
native_mode
->
voverplus
=
mode
->
vsync_start
-
mode
->
vdisplay
;
native_mode
->
vsync_width
=
mode
->
vsync_end
-
mode
->
vsync_start
;
native_mode
->
dotclock
=
mode
->
clock
;
if
(
mode
->
hdisplay
==
native_mode
->
hdisplay
&&
mode
->
vdisplay
==
native_mode
->
vdisplay
)
{
*
native_mode
=
*
mode
;
drm_mode_set_crtcinfo
(
native_mode
,
CRTC_INTERLACE_HALVE_V
);
DRM_INFO
(
"Determined LVDS native mode details from EDID
\n
"
);
break
;
}
}
}
if
(
!
native_mode
->
dot
clock
)
{
if
(
!
native_mode
->
clock
)
{
DRM_INFO
(
"No LVDS native mode details, disabling RMX
\n
"
);
radeon_encoder
->
rmx_type
=
RMX_OFF
;
}
...
...
@@ -415,8 +402,35 @@ static int radeon_lvds_mode_valid(struct drm_connector *connector,
static
enum
drm_connector_status
radeon_lvds_detect
(
struct
drm_connector
*
connector
)
{
enum
drm_connector_status
ret
=
connector_status_connected
;
struct
radeon_connector
*
radeon_connector
=
to_radeon_connector
(
connector
);
struct
drm_encoder
*
encoder
=
radeon_best_single_encoder
(
connector
);
enum
drm_connector_status
ret
=
connector_status_disconnected
;
if
(
encoder
)
{
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
struct
drm_display_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
/* check if panel is valid */
if
(
native_mode
->
hdisplay
>=
320
&&
native_mode
->
vdisplay
>=
240
)
ret
=
connector_status_connected
;
}
/* check for edid as well */
if
(
radeon_connector
->
edid
)
ret
=
connector_status_connected
;
else
{
if
(
radeon_connector
->
ddc_bus
)
{
radeon_i2c_do_lock
(
radeon_connector
,
1
);
radeon_connector
->
edid
=
drm_get_edid
(
&
radeon_connector
->
base
,
&
radeon_connector
->
ddc_bus
->
adapter
);
radeon_i2c_do_lock
(
radeon_connector
,
0
);
if
(
radeon_connector
->
edid
)
ret
=
connector_status_connected
;
}
}
/* check acpi lid status ??? */
radeon_connector_update_scratch_regs
(
connector
,
ret
);
return
ret
;
}
...
...
@@ -427,6 +441,8 @@ static void radeon_connector_destroy(struct drm_connector *connector)
if
(
radeon_connector
->
ddc_bus
)
radeon_i2c_destroy
(
radeon_connector
->
ddc_bus
);
if
(
radeon_connector
->
edid
)
kfree
(
radeon_connector
->
edid
);
kfree
(
radeon_connector
->
con_priv
);
drm_sysfs_connector_remove
(
connector
);
drm_connector_cleanup
(
connector
);
...
...
@@ -514,9 +530,32 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
radeon_i2c_do_lock
(
radeon_connector
,
1
);
dret
=
radeon_ddc_probe
(
radeon_connector
);
radeon_i2c_do_lock
(
radeon_connector
,
0
);
if
(
dret
)
ret
=
connector_status_connected
;
else
{
if
(
dret
)
{
if
(
radeon_connector
->
edid
)
{
kfree
(
radeon_connector
->
edid
);
radeon_connector
->
edid
=
NULL
;
}
radeon_i2c_do_lock
(
radeon_connector
,
1
);
radeon_connector
->
edid
=
drm_get_edid
(
&
radeon_connector
->
base
,
&
radeon_connector
->
ddc_bus
->
adapter
);
radeon_i2c_do_lock
(
radeon_connector
,
0
);
if
(
!
radeon_connector
->
edid
)
{
DRM_ERROR
(
"DDC responded but not EDID found for %s
\n
"
,
drm_get_connector_name
(
connector
));
}
else
{
radeon_connector
->
use_digital
=
!!
(
radeon_connector
->
edid
->
input
&
DRM_EDID_INPUT_DIGITAL
);
/* some oems have boards with separate digital and analog connectors
* with a shared ddc line (often vga + hdmi)
*/
if
(
radeon_connector
->
use_digital
&&
radeon_connector
->
shared_ddc
)
{
kfree
(
radeon_connector
->
edid
);
radeon_connector
->
edid
=
NULL
;
ret
=
connector_status_disconnected
;
}
else
ret
=
connector_status_connected
;
}
}
else
{
if
(
radeon_connector
->
dac_load_detect
)
{
encoder_funcs
=
encoder
->
helper_private
;
ret
=
encoder_funcs
->
detect
(
encoder
,
connector
);
...
...
@@ -644,6 +683,10 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
dret
=
radeon_ddc_probe
(
radeon_connector
);
radeon_i2c_do_lock
(
radeon_connector
,
0
);
if
(
dret
)
{
if
(
radeon_connector
->
edid
)
{
kfree
(
radeon_connector
->
edid
);
radeon_connector
->
edid
=
NULL
;
}
radeon_i2c_do_lock
(
radeon_connector
,
1
);
radeon_connector
->
edid
=
drm_get_edid
(
&
radeon_connector
->
base
,
&
radeon_connector
->
ddc_bus
->
adapter
);
radeon_i2c_do_lock
(
radeon_connector
,
0
);
...
...
@@ -654,10 +697,15 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
}
else
{
radeon_connector
->
use_digital
=
!!
(
radeon_connector
->
edid
->
input
&
DRM_EDID_INPUT_DIGITAL
);
/* if this isn't a digital monitor
then we need to make sure we don't have any
TV conflicts */
ret
=
connector_status_connected
;
/* some oems have boards with separate digital and analog connectors
* with a shared ddc line (often vga + hdmi)
*/
if
((
!
radeon_connector
->
use_digital
)
&&
radeon_connector
->
shared_ddc
)
{
kfree
(
radeon_connector
->
edid
);
radeon_connector
->
edid
=
NULL
;
ret
=
connector_status_disconnected
;
}
else
ret
=
connector_status_connected
;
}
}
...
...
@@ -782,6 +830,7 @@ radeon_add_atom_connector(struct drm_device *dev,
struct
radeon_connector
*
radeon_connector
;
struct
radeon_connector_atom_dig
*
radeon_dig_connector
;
uint32_t
subpixel_order
=
SubPixelNone
;
bool
shared_ddc
=
false
;
int
ret
;
/* fixme - tv/cv/din */
...
...
@@ -795,6 +844,13 @@ radeon_add_atom_connector(struct drm_device *dev,
radeon_connector
->
devices
|=
supported_device
;
return
;
}
if
(
radeon_connector
->
ddc_bus
&&
i2c_bus
->
valid
)
{
if
(
memcmp
(
&
radeon_connector
->
ddc_bus
->
rec
,
i2c_bus
,
sizeof
(
struct
radeon_i2c_bus_rec
))
==
0
)
{
radeon_connector
->
shared_ddc
=
true
;
shared_ddc
=
true
;
}
}
}
radeon_connector
=
kzalloc
(
sizeof
(
struct
radeon_connector
),
GFP_KERNEL
);
...
...
@@ -805,6 +861,7 @@ radeon_add_atom_connector(struct drm_device *dev,
radeon_connector
->
connector_id
=
connector_id
;
radeon_connector
->
devices
=
supported_device
;
radeon_connector
->
shared_ddc
=
shared_ddc
;
switch
(
connector_type
)
{
case
DRM_MODE_CONNECTOR_VGA
:
drm_connector_init
(
dev
,
&
radeon_connector
->
base
,
&
radeon_vga_connector_funcs
,
connector_type
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_cp.c
浏览文件 @
5b8f0be0
...
...
@@ -1941,8 +1941,8 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
for
(
t
=
0
;
t
<
dev_priv
->
usec_timeout
;
t
++
)
{
u32
done_age
=
GET_SCRATCH
(
dev_priv
,
1
);
DRM_DEBUG
(
"done_age = %d
\n
"
,
done_age
);
for
(
i
=
start
;
i
<
dma
->
buf_count
;
i
++
)
{
buf
=
dma
->
buflist
[
i
];
for
(
i
=
0
;
i
<
dma
->
buf_count
;
i
++
)
{
buf
=
dma
->
buflist
[
start
];
buf_priv
=
buf
->
dev_private
;
if
(
buf
->
file_priv
==
NULL
||
(
buf
->
pending
&&
buf_priv
->
age
<=
...
...
@@ -1951,7 +1951,8 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
buf
->
pending
=
0
;
return
buf
;
}
start
=
0
;
if
(
++
start
>=
dma
->
buf_count
)
start
=
0
;
}
if
(
t
)
{
...
...
@@ -1960,47 +1961,9 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
}
}
DRM_DEBUG
(
"returning NULL!
\n
"
);
return
NULL
;
}
#if 0
struct drm_buf *radeon_freelist_get(struct drm_device * dev)
{
struct drm_device_dma *dma = dev->dma;
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_buf_priv_t *buf_priv;
struct drm_buf *buf;
int i, t;
int start;
u32 done_age;
done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
if (++dev_priv->last_buf >= dma->buf_count)
dev_priv->last_buf = 0;
start = dev_priv->last_buf;
dev_priv->stats.freelist_loops++;
for (t = 0; t < 2; t++) {
for (i = start; i < dma->buf_count; i++) {
buf = dma->buflist[i];
buf_priv = buf->dev_private;
if (buf->file_priv == 0 || (buf->pending &&
buf_priv->age <=
done_age)) {
dev_priv->stats.requested_bufs++;
buf->pending = 0;
return buf;
}
}
start = 0;
}
return NULL;
}
#endif
void
radeon_freelist_reset
(
struct
drm_device
*
dev
)
{
struct
drm_device_dma
*
dma
=
dev
->
dma
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_cursor.c
浏览文件 @
5b8f0be0
...
...
@@ -109,9 +109,15 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
struct
radeon_crtc
*
radeon_crtc
=
to_radeon_crtc
(
crtc
);
struct
radeon_device
*
rdev
=
crtc
->
dev
->
dev_private
;
if
(
ASIC_IS_AVIVO
(
rdev
))
if
(
ASIC_IS_AVIVO
(
rdev
))
{
if
(
rdev
->
family
>=
CHIP_RV770
)
{
if
(
radeon_crtc
->
crtc_id
)
WREG32
(
R700_D2CUR_SURFACE_ADDRESS_HIGH
,
0
);
else
WREG32
(
R700_D1CUR_SURFACE_ADDRESS_HIGH
,
0
);
}
WREG32
(
AVIVO_D1CUR_SURFACE_ADDRESS
+
radeon_crtc
->
crtc_offset
,
gpu_addr
);
else
{
}
else
{
radeon_crtc
->
legacy_cursor_offset
=
gpu_addr
-
radeon_crtc
->
legacy_display_base_addr
;
/* offset is from DISP(2)_BASE_ADDRESS */
WREG32
(
RADEON_CUR_OFFSET
+
radeon_crtc
->
crtc_offset
,
radeon_crtc
->
legacy_cursor_offset
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_device.c
浏览文件 @
5b8f0be0
...
...
@@ -444,20 +444,24 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
return
r
;
}
static
struct
card_info
atom_card_info
=
{
.
dev
=
NULL
,
.
reg_read
=
cail_reg_read
,
.
reg_write
=
cail_reg_write
,
.
mc_read
=
cail_mc_read
,
.
mc_write
=
cail_mc_write
,
.
pll_read
=
cail_pll_read
,
.
pll_write
=
cail_pll_write
,
};
int
radeon_atombios_init
(
struct
radeon_device
*
rdev
)
{
atom_card_info
.
dev
=
rdev
->
ddev
;
rdev
->
mode_info
.
atom_context
=
atom_parse
(
&
atom_card_info
,
rdev
->
bios
);
struct
card_info
*
atom_card_info
=
kzalloc
(
sizeof
(
struct
card_info
),
GFP_KERNEL
);
if
(
!
atom_card_info
)
return
-
ENOMEM
;
rdev
->
mode_info
.
atom_card_info
=
atom_card_info
;
atom_card_info
->
dev
=
rdev
->
ddev
;
atom_card_info
->
reg_read
=
cail_reg_read
;
atom_card_info
->
reg_write
=
cail_reg_write
;
atom_card_info
->
mc_read
=
cail_mc_read
;
atom_card_info
->
mc_write
=
cail_mc_write
;
atom_card_info
->
pll_read
=
cail_pll_read
;
atom_card_info
->
pll_write
=
cail_pll_write
;
rdev
->
mode_info
.
atom_context
=
atom_parse
(
atom_card_info
,
rdev
->
bios
);
radeon_atom_initialize_bios_scratch_regs
(
rdev
->
ddev
);
return
0
;
}
...
...
@@ -465,6 +469,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
void
radeon_atombios_fini
(
struct
radeon_device
*
rdev
)
{
kfree
(
rdev
->
mode_info
.
atom_context
);
kfree
(
rdev
->
mode_info
.
atom_card_info
);
}
int
radeon_combios_init
(
struct
radeon_device
*
rdev
)
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_display.c
浏览文件 @
5b8f0be0
...
...
@@ -137,9 +137,6 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
if
(
size
!=
256
)
{
return
;
}
if
(
crtc
->
fb
==
NULL
)
{
return
;
}
/* userspace palettes are always correct as is */
for
(
i
=
0
;
i
<
256
;
i
++
)
{
...
...
@@ -147,7 +144,6 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
radeon_crtc
->
lut_g
[
i
]
=
green
[
i
]
>>
6
;
radeon_crtc
->
lut_b
[
i
]
=
blue
[
i
]
>>
6
;
}
radeon_crtc_load_lut
(
crtc
);
}
...
...
@@ -338,27 +334,19 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
int
radeon_ddc_get_modes
(
struct
radeon_connector
*
radeon_connector
)
{
struct
edid
*
edid
;
int
ret
=
0
;
if
(
!
radeon_connector
->
ddc_bus
)
return
-
1
;
if
(
!
radeon_connector
->
edid
)
{
radeon_i2c_do_lock
(
radeon_connector
,
1
);
edid
=
drm_get_edid
(
&
radeon_connector
->
base
,
&
radeon_connector
->
ddc_bus
->
adapter
);
radeon_connector
->
edid
=
drm_get_edid
(
&
radeon_connector
->
base
,
&
radeon_connector
->
ddc_bus
->
adapter
);
radeon_i2c_do_lock
(
radeon_connector
,
0
);
}
else
edid
=
radeon_connector
->
edid
;
}
if
(
edid
)
{
/* update digital bits here */
if
(
edid
->
input
&
DRM_EDID_INPUT_DIGITAL
)
radeon_connector
->
use_digital
=
1
;
else
radeon_connector
->
use_digital
=
0
;
drm_mode_connector_update_edid_property
(
&
radeon_connector
->
base
,
edid
);
ret
=
drm_add_edid_modes
(
&
radeon_connector
->
base
,
edid
);
kfree
(
edid
);
if
(
radeon_connector
->
edid
)
{
drm_mode_connector_update_edid_property
(
&
radeon_connector
->
base
,
radeon_connector
->
edid
);
ret
=
drm_add_edid_modes
(
&
radeon_connector
->
base
,
radeon_connector
->
edid
);
return
ret
;
}
drm_mode_connector_update_edid_property
(
&
radeon_connector
->
base
,
NULL
);
...
...
@@ -765,7 +753,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
radeon_crtc
->
rmx_type
=
radeon_encoder
->
rmx_type
;
memcpy
(
&
radeon_crtc
->
native_mode
,
&
radeon_encoder
->
native_mode
,
sizeof
(
struct
radeon_native
_mode
));
sizeof
(
struct
drm_display
_mode
));
first
=
false
;
}
else
{
if
(
radeon_crtc
->
rmx_type
!=
radeon_encoder
->
rmx_type
)
{
...
...
@@ -783,10 +771,10 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
if
(
radeon_crtc
->
rmx_type
!=
RMX_OFF
)
{
fixed20_12
a
,
b
;
a
.
full
=
rfixed_const
(
crtc
->
mode
.
vdisplay
);
b
.
full
=
rfixed_const
(
radeon_crtc
->
native_mode
.
panel_xres
);
b
.
full
=
rfixed_const
(
radeon_crtc
->
native_mode
.
hdisplay
);
radeon_crtc
->
vsc
.
full
=
rfixed_div
(
a
,
b
);
a
.
full
=
rfixed_const
(
crtc
->
mode
.
hdisplay
);
b
.
full
=
rfixed_const
(
radeon_crtc
->
native_mode
.
panel_yres
);
b
.
full
=
rfixed_const
(
radeon_crtc
->
native_mode
.
vdisplay
);
radeon_crtc
->
hsc
.
full
=
rfixed_div
(
a
,
b
);
}
else
{
radeon_crtc
->
vsc
.
full
=
rfixed_const
(
1
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_encoders.c
浏览文件 @
5b8f0be0
...
...
@@ -31,6 +31,10 @@
extern
int
atom_debug
;
/* evil but including atombios.h is much worse */
bool
radeon_atom_get_tv_timings
(
struct
radeon_device
*
rdev
,
int
index
,
struct
drm_display_mode
*
mode
);
uint32_t
radeon_get_encoder_id
(
struct
drm_device
*
dev
,
uint32_t
supported_device
,
uint8_t
dac
)
{
...
...
@@ -167,49 +171,17 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
struct
drm_device
*
dev
=
encoder
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
struct
radeon_native_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
if
(
mode
->
hdisplay
<
native_mode
->
panel_xres
||
mode
->
vdisplay
<
native_mode
->
panel_yres
)
{
if
(
ASIC_IS_AVIVO
(
rdev
))
{
adjusted_mode
->
hdisplay
=
native_mode
->
panel_xres
;
adjusted_mode
->
vdisplay
=
native_mode
->
panel_yres
;
adjusted_mode
->
htotal
=
native_mode
->
panel_xres
+
native_mode
->
hblank
;
adjusted_mode
->
hsync_start
=
native_mode
->
panel_xres
+
native_mode
->
hoverplus
;
adjusted_mode
->
hsync_end
=
adjusted_mode
->
hsync_start
+
native_mode
->
hsync_width
;
adjusted_mode
->
vtotal
=
native_mode
->
panel_yres
+
native_mode
->
vblank
;
adjusted_mode
->
vsync_start
=
native_mode
->
panel_yres
+
native_mode
->
voverplus
;
adjusted_mode
->
vsync_end
=
adjusted_mode
->
vsync_start
+
native_mode
->
vsync_width
;
/* update crtc values */
drm_mode_set_crtcinfo
(
adjusted_mode
,
CRTC_INTERLACE_HALVE_V
);
/* adjust crtc values */
adjusted_mode
->
crtc_hdisplay
=
native_mode
->
panel_xres
;
adjusted_mode
->
crtc_vdisplay
=
native_mode
->
panel_yres
;
adjusted_mode
->
crtc_htotal
=
adjusted_mode
->
crtc_hdisplay
+
native_mode
->
hblank
;
adjusted_mode
->
crtc_hsync_start
=
adjusted_mode
->
crtc_hdisplay
+
native_mode
->
hoverplus
;
adjusted_mode
->
crtc_hsync_end
=
adjusted_mode
->
crtc_hsync_start
+
native_mode
->
hsync_width
;
adjusted_mode
->
crtc_vtotal
=
adjusted_mode
->
crtc_vdisplay
+
native_mode
->
vblank
;
adjusted_mode
->
crtc_vsync_start
=
adjusted_mode
->
crtc_vdisplay
+
native_mode
->
voverplus
;
adjusted_mode
->
crtc_vsync_end
=
adjusted_mode
->
crtc_vsync_start
+
native_mode
->
vsync_width
;
}
else
{
adjusted_mode
->
htotal
=
native_mode
->
panel_xres
+
native_mode
->
hblank
;
adjusted_mode
->
hsync_start
=
native_mode
->
panel_xres
+
native_mode
->
hoverplus
;
adjusted_mode
->
hsync_end
=
adjusted_mode
->
hsync_start
+
native_mode
->
hsync_width
;
adjusted_mode
->
vtotal
=
native_mode
->
panel_yres
+
native_mode
->
vblank
;
adjusted_mode
->
vsync_start
=
native_mode
->
panel_yres
+
native_mode
->
voverplus
;
adjusted_mode
->
vsync_end
=
adjusted_mode
->
vsync_start
+
native_mode
->
vsync_width
;
/* update crtc values */
drm_mode_set_crtcinfo
(
adjusted_mode
,
CRTC_INTERLACE_HALVE_V
);
/* adjust crtc values */
adjusted_mode
->
crtc_htotal
=
adjusted_mode
->
crtc_hdisplay
+
native_mode
->
hblank
;
adjusted_mode
->
crtc_hsync_start
=
adjusted_mode
->
crtc_hdisplay
+
native_mode
->
hoverplus
;
adjusted_mode
->
crtc_hsync_end
=
adjusted_mode
->
crtc_hsync_start
+
native_mode
->
hsync_width
;
adjusted_mode
->
crtc_vtotal
=
adjusted_mode
->
crtc_vdisplay
+
native_mode
->
vblank
;
adjusted_mode
->
crtc_vsync_start
=
adjusted_mode
->
crtc_vdisplay
+
native_mode
->
voverplus
;
adjusted_mode
->
crtc_vsync_end
=
adjusted_mode
->
crtc_vsync_start
+
native_mode
->
vsync_width
;
struct
drm_display_mode
*
native_mode
=
&
radeon_encoder
->
native_mode
;
if
(
mode
->
hdisplay
<
native_mode
->
hdisplay
||
mode
->
vdisplay
<
native_mode
->
vdisplay
)
{
int
mode_id
=
adjusted_mode
->
base
.
id
;
*
adjusted_mode
=
*
native_mode
;
if
(
!
ASIC_IS_AVIVO
(
rdev
))
{
adjusted_mode
->
hdisplay
=
mode
->
hdisplay
;
adjusted_mode
->
vdisplay
=
mode
->
vdisplay
;
}
adjusted_mode
->
flags
=
native_mode
->
flags
;
adjusted_mode
->
clock
=
native_mode
->
dotclock
;
adjusted_mode
->
base
.
id
=
mode_id
;
}
}
...
...
@@ -219,7 +191,11 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
struct
drm_display_mode
*
adjusted_mode
)
{
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
struct
drm_device
*
dev
=
encoder
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
/* set the active encoder to connector routing */
radeon_encoder_set_active_device
(
encoder
);
drm_mode_set_crtcinfo
(
adjusted_mode
,
0
);
if
(
radeon_encoder
->
rmx_type
!=
RMX_OFF
)
...
...
@@ -230,6 +206,18 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
&&
(
mode
->
crtc_vsync_start
<
(
mode
->
crtc_vdisplay
+
2
)))
adjusted_mode
->
crtc_vsync_start
=
adjusted_mode
->
crtc_vdisplay
+
2
;
if
(
radeon_encoder
->
active_device
&
(
ATOM_DEVICE_TV_SUPPORT
))
{
struct
radeon_encoder_atom_dac
*
tv_dac
=
radeon_encoder
->
enc_priv
;
if
(
tv_dac
)
{
if
(
tv_dac
->
tv_std
==
TV_STD_NTSC
||
tv_dac
->
tv_std
==
TV_STD_NTSC_J
||
tv_dac
->
tv_std
==
TV_STD_PAL_M
)
radeon_atom_get_tv_timings
(
rdev
,
0
,
adjusted_mode
);
else
radeon_atom_get_tv_timings
(
rdev
,
1
,
adjusted_mode
);
}
}
return
true
;
}
...
...
@@ -461,7 +449,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
case
1
:
args
.
v1
.
ucMisc
=
0
;
args
.
v1
.
ucAction
=
action
;
if
(
drm_detect_hdmi_monitor
(
(
struct
edid
*
)
connector
->
edid_blob_ptr
))
if
(
drm_detect_hdmi_monitor
(
radeon_connector
->
edid
))
args
.
v1
.
ucMisc
|=
PANEL_ENCODER_MISC_HDMI_TYPE
;
args
.
v1
.
usPixelClock
=
cpu_to_le16
(
radeon_encoder
->
pixel_clock
/
10
);
if
(
radeon_encoder
->
devices
&
(
ATOM_DEVICE_LCD_SUPPORT
))
{
...
...
@@ -486,7 +474,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
if
(
dig
->
coherent_mode
)
args
.
v2
.
ucMisc
|=
PANEL_ENCODER_MISC_COHERENT
;
}
if
(
drm_detect_hdmi_monitor
(
(
struct
edid
*
)
connector
->
edid_blob_ptr
))
if
(
drm_detect_hdmi_monitor
(
radeon_connector
->
edid
))
args
.
v2
.
ucMisc
|=
PANEL_ENCODER_MISC_HDMI_TYPE
;
args
.
v2
.
usPixelClock
=
cpu_to_le16
(
radeon_encoder
->
pixel_clock
/
10
);
args
.
v2
.
ucTruncate
=
0
;
...
...
@@ -544,7 +532,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
switch
(
connector
->
connector_type
)
{
case
DRM_MODE_CONNECTOR_DVII
:
case
DRM_MODE_CONNECTOR_HDMIB
:
/* HDMI-B is basically DL-DVI; analog works fine */
if
(
drm_detect_hdmi_monitor
(
(
struct
edid
*
)
connector
->
edid_blob_ptr
))
if
(
drm_detect_hdmi_monitor
(
radeon_connector
->
edid
))
return
ATOM_ENCODER_MODE_HDMI
;
else
if
(
radeon_connector
->
use_digital
)
return
ATOM_ENCODER_MODE_DVI
;
...
...
@@ -554,7 +542,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
case
DRM_MODE_CONNECTOR_DVID
:
case
DRM_MODE_CONNECTOR_HDMIA
:
default:
if
(
drm_detect_hdmi_monitor
(
(
struct
edid
*
)
connector
->
edid_blob_ptr
))
if
(
drm_detect_hdmi_monitor
(
radeon_connector
->
edid
))
return
ATOM_ENCODER_MODE_HDMI
;
else
return
ATOM_ENCODER_MODE_DVI
;
...
...
@@ -566,7 +554,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
/*if (radeon_output->MonType == MT_DP)
return ATOM_ENCODER_MODE_DP;
else*/
if
(
drm_detect_hdmi_monitor
(
(
struct
edid
*
)
connector
->
edid_blob_ptr
))
if
(
drm_detect_hdmi_monitor
(
radeon_connector
->
edid
))
return
ATOM_ENCODER_MODE_HDMI
;
else
return
ATOM_ENCODER_MODE_DVI
;
...
...
@@ -874,16 +862,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
args
;
int
index
=
0
;
bool
is_dig
=
false
;
int
devices
;
memset
(
&
args
,
0
,
sizeof
(
args
));
/* on DPMS off we have no idea if active device is meaningful */
if
(
mode
!=
DRM_MODE_DPMS_ON
&&
!
radeon_encoder
->
active_device
)
devices
=
radeon_encoder
->
devices
;
else
devices
=
radeon_encoder
->
active_device
;
DRM_DEBUG
(
"encoder dpms %d to mode %d, devices %08x, active_devices %08x
\n
"
,
radeon_encoder
->
encoder_id
,
mode
,
radeon_encoder
->
devices
,
radeon_encoder
->
active_device
);
...
...
@@ -914,18 +895,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
break
;
case
ENCODER_OBJECT_ID_INTERNAL_DAC1
:
case
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
if
(
devices
&
(
ATOM_DEVICE_TV_SUPPORT
))
if
(
radeon_encoder
->
active_device
&
(
ATOM_DEVICE_TV_SUPPORT
))
index
=
GetIndexIntoMasterTable
(
COMMAND
,
TV1OutputControl
);
else
if
(
devices
&
(
ATOM_DEVICE_CV_SUPPORT
))
else
if
(
radeon_encoder
->
active_device
&
(
ATOM_DEVICE_CV_SUPPORT
))
index
=
GetIndexIntoMasterTable
(
COMMAND
,
CV1OutputControl
);
else
index
=
GetIndexIntoMasterTable
(
COMMAND
,
DAC1OutputControl
);
break
;
case
ENCODER_OBJECT_ID_INTERNAL_DAC2
:
case
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
if
(
devices
&
(
ATOM_DEVICE_TV_SUPPORT
))
if
(
radeon_encoder
->
active_device
&
(
ATOM_DEVICE_TV_SUPPORT
))
index
=
GetIndexIntoMasterTable
(
COMMAND
,
TV1OutputControl
);
else
if
(
devices
&
(
ATOM_DEVICE_CV_SUPPORT
))
else
if
(
radeon_encoder
->
active_device
&
(
ATOM_DEVICE_CV_SUPPORT
))
index
=
GetIndexIntoMasterTable
(
COMMAND
,
CV1OutputControl
);
else
index
=
GetIndexIntoMasterTable
(
COMMAND
,
DAC2OutputControl
);
...
...
@@ -1104,8 +1085,11 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
}
/* set scaler clears this on some chips */
if
(
ASIC_IS_AVIVO
(
rdev
)
&&
(
mode
->
flags
&
DRM_MODE_FLAG_INTERLACE
))
WREG32
(
AVIVO_D1MODE_DATA_FORMAT
+
radeon_crtc
->
crtc_offset
,
AVIVO_D1MODE_INTERLEAVE_EN
);
if
(
!
(
radeon_encoder
->
active_device
&
(
ATOM_DEVICE_TV_SUPPORT
)))
{
if
(
ASIC_IS_AVIVO
(
rdev
)
&&
(
mode
->
flags
&
DRM_MODE_FLAG_INTERLACE
))
WREG32
(
AVIVO_D1MODE_DATA_FORMAT
+
radeon_crtc
->
crtc_offset
,
AVIVO_D1MODE_INTERLEAVE_EN
);
}
}
static
void
...
...
@@ -1268,8 +1252,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
{
radeon_atom_output_lock
(
encoder
,
true
);
radeon_atom_encoder_dpms
(
encoder
,
DRM_MODE_DPMS_OFF
);
radeon_encoder_set_active_device
(
encoder
);
}
static
void
radeon_atom_encoder_commit
(
struct
drm_encoder
*
encoder
)
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_gart.c
浏览文件 @
5b8f0be0
...
...
@@ -140,15 +140,15 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
WARN
(
1
,
"trying to unbind memory to unitialized GART !
\n
"
);
return
;
}
t
=
offset
/
4096
;
p
=
t
/
(
PAGE_SIZE
/
4096
);
t
=
offset
/
RADEON_GPU_PAGE_SIZE
;
p
=
t
/
(
PAGE_SIZE
/
RADEON_GPU_PAGE_SIZE
);
for
(
i
=
0
;
i
<
pages
;
i
++
,
p
++
)
{
if
(
rdev
->
gart
.
pages
[
p
])
{
pci_unmap_page
(
rdev
->
pdev
,
rdev
->
gart
.
pages_addr
[
p
],
PAGE_SIZE
,
PCI_DMA_BIDIRECTIONAL
);
rdev
->
gart
.
pages
[
p
]
=
NULL
;
rdev
->
gart
.
pages_addr
[
p
]
=
0
;
for
(
j
=
0
;
j
<
(
PAGE_SIZE
/
4096
);
j
++
,
t
++
)
{
for
(
j
=
0
;
j
<
(
PAGE_SIZE
/
RADEON_GPU_PAGE_SIZE
);
j
++
,
t
++
)
{
radeon_gart_set_page
(
rdev
,
t
,
0
);
}
}
...
...
@@ -169,8 +169,8 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
DRM_ERROR
(
"trying to bind memory to unitialized GART !
\n
"
);
return
-
EINVAL
;
}
t
=
offset
/
4096
;
p
=
t
/
(
PAGE_SIZE
/
4096
);
t
=
offset
/
RADEON_GPU_PAGE_SIZE
;
p
=
t
/
(
PAGE_SIZE
/
RADEON_GPU_PAGE_SIZE
);
for
(
i
=
0
;
i
<
pages
;
i
++
,
p
++
)
{
/* we need to support large memory configurations */
...
...
@@ -185,9 +185,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
}
rdev
->
gart
.
pages
[
p
]
=
pagelist
[
i
];
page_base
=
rdev
->
gart
.
pages_addr
[
p
];
for
(
j
=
0
;
j
<
(
PAGE_SIZE
/
4096
);
j
++
,
t
++
)
{
for
(
j
=
0
;
j
<
(
PAGE_SIZE
/
RADEON_GPU_PAGE_SIZE
);
j
++
,
t
++
)
{
radeon_gart_set_page
(
rdev
,
t
,
page_base
);
page_base
+=
4096
;
page_base
+=
RADEON_GPU_PAGE_SIZE
;
}
}
mb
();
...
...
@@ -200,14 +200,14 @@ int radeon_gart_init(struct radeon_device *rdev)
if
(
rdev
->
gart
.
pages
)
{
return
0
;
}
/* We need PAGE_SIZE >=
4096
*/
if
(
PAGE_SIZE
<
4096
)
{
/* We need PAGE_SIZE >=
RADEON_GPU_PAGE_SIZE
*/
if
(
PAGE_SIZE
<
RADEON_GPU_PAGE_SIZE
)
{
DRM_ERROR
(
"Page size is smaller than GPU page size!
\n
"
);
return
-
EINVAL
;
}
/* Compute table size */
rdev
->
gart
.
num_cpu_pages
=
rdev
->
mc
.
gtt_size
/
PAGE_SIZE
;
rdev
->
gart
.
num_gpu_pages
=
rdev
->
mc
.
gtt_size
/
4096
;
rdev
->
gart
.
num_gpu_pages
=
rdev
->
mc
.
gtt_size
/
RADEON_GPU_PAGE_SIZE
;
DRM_INFO
(
"GART: num cpu pages %u, num gpu pages %u
\n
"
,
rdev
->
gart
.
num_cpu_pages
,
rdev
->
gart
.
num_gpu_pages
);
/* Allocate pages table */
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_irq_kms.c
浏览文件 @
5b8f0be0
...
...
@@ -92,6 +92,13 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
if
(
r
)
{
return
r
;
}
/* enable msi */
rdev
->
msi_enabled
=
0
;
if
(
rdev
->
family
>=
CHIP_RV380
)
{
int
ret
=
pci_enable_msi
(
rdev
->
pdev
);
if
(
!
ret
)
rdev
->
msi_enabled
=
1
;
}
drm_irq_install
(
rdev
->
ddev
);
rdev
->
irq
.
installed
=
true
;
DRM_INFO
(
"radeon: irq initialized.
\n
"
);
...
...
@@ -103,5 +110,7 @@ void radeon_irq_kms_fini(struct radeon_device *rdev)
if
(
rdev
->
irq
.
installed
)
{
rdev
->
irq
.
installed
=
false
;
drm_irq_uninstall
(
rdev
->
ddev
);
if
(
rdev
->
msi_enabled
)
pci_disable_msi
(
rdev
->
pdev
);
}
}
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
浏览文件 @
5b8f0be0
...
...
@@ -48,7 +48,7 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
u32
fp_horz_stretch
,
fp_vert_stretch
,
fp_horz_vert_active
;
u32
fp_h_sync_strt_wid
,
fp_crtc_h_total_disp
;
u32
fp_v_sync_strt_wid
,
fp_crtc_v_total_disp
;
struct
radeon_native
_mode
*
native_mode
=
&
radeon_crtc
->
native_mode
;
struct
drm_display
_mode
*
native_mode
=
&
radeon_crtc
->
native_mode
;
fp_vert_stretch
=
RREG32
(
RADEON_FP_VERT_STRETCH
)
&
(
RADEON_VERT_STRETCH_RESERVED
|
...
...
@@ -95,19 +95,19 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
fp_horz_vert_active
=
0
;
if
(
native_mode
->
panel_xres
==
0
||
native_mode
->
panel_yres
==
0
)
{
if
(
native_mode
->
hdisplay
==
0
||
native_mode
->
vdisplay
==
0
)
{
hscale
=
false
;
vscale
=
false
;
}
else
{
if
(
xres
>
native_mode
->
panel_xres
)
xres
=
native_mode
->
panel_xres
;
if
(
yres
>
native_mode
->
panel_yres
)
yres
=
native_mode
->
panel_yres
;
if
(
xres
>
native_mode
->
hdisplay
)
xres
=
native_mode
->
hdisplay
;
if
(
yres
>
native_mode
->
vdisplay
)
yres
=
native_mode
->
vdisplay
;
if
(
xres
==
native_mode
->
panel_xres
)
if
(
xres
==
native_mode
->
hdisplay
)
hscale
=
false
;
if
(
yres
==
native_mode
->
panel_yres
)
if
(
yres
==
native_mode
->
vdisplay
)
vscale
=
false
;
}
...
...
@@ -119,11 +119,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
else
{
inc
=
(
fp_horz_stretch
&
RADEON_HORZ_AUTO_RATIO_INC
)
?
1
:
0
;
scale
=
((
xres
+
inc
)
*
RADEON_HORZ_STRETCH_RATIO_MAX
)
/
native_mode
->
panel_xres
+
1
;
/
native_mode
->
hdisplay
+
1
;
fp_horz_stretch
|=
(((
scale
)
&
RADEON_HORZ_STRETCH_RATIO_MASK
)
|
RADEON_HORZ_STRETCH_BLEND
|
RADEON_HORZ_STRETCH_ENABLE
|
((
native_mode
->
panel_xres
/
8
-
1
)
<<
16
));
((
native_mode
->
hdisplay
/
8
-
1
)
<<
16
));
}
if
(
!
vscale
)
...
...
@@ -131,11 +131,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
else
{
inc
=
(
fp_vert_stretch
&
RADEON_VERT_AUTO_RATIO_INC
)
?
1
:
0
;
scale
=
((
yres
+
inc
)
*
RADEON_VERT_STRETCH_RATIO_MAX
)
/
native_mode
->
panel_yres
+
1
;
/
native_mode
->
vdisplay
+
1
;
fp_vert_stretch
|=
(((
scale
)
&
RADEON_VERT_STRETCH_RATIO_MASK
)
|
RADEON_VERT_STRETCH_ENABLE
|
RADEON_VERT_STRETCH_BLEND
|
((
native_mode
->
panel_yres
-
1
)
<<
12
));
((
native_mode
->
vdisplay
-
1
)
<<
12
));
}
break
;
case
RMX_CENTER
:
...
...
@@ -175,8 +175,8 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
?
RADEON_CRTC_V_SYNC_POL
:
0
)));
fp_horz_vert_active
=
(((
native_mode
->
panel_yres
)
&
0xfff
)
|
(((
native_mode
->
panel_xres
/
8
)
&
0x1ff
)
<<
16
));
fp_horz_vert_active
=
(((
native_mode
->
vdisplay
)
&
0xfff
)
|
(((
native_mode
->
hdisplay
/
8
)
&
0x1ff
)
<<
16
));
break
;
case
RMX_OFF
:
default:
...
...
@@ -532,6 +532,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
radeon_fb
=
to_radeon_framebuffer
(
old_fb
);
radeon_gem_object_unpin
(
radeon_fb
->
obj
);
}
/* Bytes per pixel may have changed */
radeon_bandwidth_update
(
rdev
);
return
0
;
}
...
...
@@ -664,6 +668,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
WREG32
(
RADEON_DISP2_MERGE_CNTL
,
disp2_merge_cntl
);
WREG32
(
RADEON_CRTC2_GEN_CNTL
,
crtc2_gen_cntl
);
WREG32
(
RADEON_FP_H2_SYNC_STRT_WID
,
crtc_h_sync_strt_wid
);
WREG32
(
RADEON_FP_V2_SYNC_STRT_WID
,
crtc_v_sync_strt_wid
);
}
else
{
uint32_t
crtc_gen_cntl
;
uint32_t
crtc_ext_cntl
;
...
...
@@ -1015,14 +1022,11 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
int
x
,
int
y
,
struct
drm_framebuffer
*
old_fb
)
{
struct
radeon_crtc
*
radeon_crtc
=
to_radeon_crtc
(
crtc
);
struct
drm_device
*
dev
=
crtc
->
dev
;
struct
radeon_device
*
rdev
=
dev
->
dev_private
;
/* TODO TV */
radeon_crtc_set_base
(
crtc
,
x
,
y
,
old_fb
);
radeon_set_crtc_timing
(
crtc
,
adjusted_mode
);
radeon_set_pll
(
crtc
,
adjusted_mode
);
radeon_bandwidth_update
(
rdev
);
if
(
radeon_crtc
->
crtc_id
==
0
)
{
radeon_legacy_rmx_mode_set
(
crtc
,
mode
,
adjusted_mode
);
}
else
{
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
浏览文件 @
5b8f0be0
...
...
@@ -107,8 +107,6 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock
(
encoder
,
true
);
radeon_legacy_lvds_dpms
(
encoder
,
DRM_MODE_DPMS_OFF
);
radeon_encoder_set_active_device
(
encoder
);
}
static
void
radeon_legacy_lvds_commit
(
struct
drm_encoder
*
encoder
)
...
...
@@ -192,6 +190,8 @@ static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
{
struct
radeon_encoder
*
radeon_encoder
=
to_radeon_encoder
(
encoder
);
/* set the active encoder to connector routing */
radeon_encoder_set_active_device
(
encoder
);
drm_mode_set_crtcinfo
(
adjusted_mode
,
0
);
if
(
radeon_encoder
->
rmx_type
!=
RMX_OFF
)
...
...
@@ -218,7 +218,8 @@ static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
struct
drm_display_mode
*
mode
,
struct
drm_display_mode
*
adjusted_mode
)
{
/* set the active encoder to connector routing */
radeon_encoder_set_active_device
(
encoder
);
drm_mode_set_crtcinfo
(
adjusted_mode
,
0
);
return
true
;
...
...
@@ -272,7 +273,6 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock
(
encoder
,
true
);
radeon_legacy_primary_dac_dpms
(
encoder
,
DRM_MODE_DPMS_OFF
);
radeon_encoder_set_active_device
(
encoder
);
}
static
void
radeon_legacy_primary_dac_commit
(
struct
drm_encoder
*
encoder
)
...
...
@@ -468,7 +468,6 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock
(
encoder
,
true
);
radeon_legacy_tmds_int_dpms
(
encoder
,
DRM_MODE_DPMS_OFF
);
radeon_encoder_set_active_device
(
encoder
);
}
static
void
radeon_legacy_tmds_int_commit
(
struct
drm_encoder
*
encoder
)
...
...
@@ -543,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
fp_gen_cntl
&=
~
(
RADEON_FP_FPON
|
RADEON_FP_TMDS_EN
);
fp_gen_cntl
&=
~
(
RADEON_FP_RMX_HVSYNC_CONTROL_EN
|
RADEON_FP_DFP_SYNC_SEL
|
RADEON_FP_CRT_SYNC_SEL
|
RADEON_FP_CRTC_LOCK_8DOT
|
RADEON_FP_USE_SHADOW_EN
|
RADEON_FP_CRTC_USE_SHADOW_VEND
|
RADEON_FP_CRT_SYNC_ALT
);
if
(
1
)
/* FIXME rgbBits == 8 */
fp_gen_cntl
|=
RADEON_FP_PANEL_FORMAT
;
/* 24 bit format */
else
...
...
@@ -556,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
else
fp_gen_cntl
|=
R200_FP_SOURCE_SEL_CRTC1
;
}
else
fp_gen_cntl
|=
RADEON_FP_SEL_CRTC1
;
fp_gen_cntl
&=
~
RADEON_FP_SEL_CRTC2
;
}
else
{
if
(
ASIC_IS_R300
(
rdev
)
||
rdev
->
family
==
CHIP_R200
)
{
fp_gen_cntl
&=
~
R200_FP_SOURCE_SEL_MASK
;
...
...
@@ -593,7 +600,8 @@ static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
struct
drm_display_mode
*
mode
,
struct
drm_display_mode
*
adjusted_mode
)
{
/* set the active encoder to connector routing */
radeon_encoder_set_active_device
(
encoder
);
drm_mode_set_crtcinfo
(
adjusted_mode
,
0
);
return
true
;
...
...
@@ -636,7 +644,6 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock
(
encoder
,
true
);
radeon_legacy_tmds_ext_dpms
(
encoder
,
DRM_MODE_DPMS_OFF
);
radeon_encoder_set_active_device
(
encoder
);
}
static
void
radeon_legacy_tmds_ext_commit
(
struct
drm_encoder
*
encoder
)
...
...
@@ -735,7 +742,8 @@ static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
struct
drm_display_mode
*
mode
,
struct
drm_display_mode
*
adjusted_mode
)
{
/* set the active encoder to connector routing */
radeon_encoder_set_active_device
(
encoder
);
drm_mode_set_crtcinfo
(
adjusted_mode
,
0
);
return
true
;
...
...
@@ -839,7 +847,6 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
else
radeon_combios_output_lock
(
encoder
,
true
);
radeon_legacy_tv_dac_dpms
(
encoder
,
DRM_MODE_DPMS_OFF
);
radeon_encoder_set_active_device
(
encoder
);
}
static
void
radeon_legacy_tv_dac_commit
(
struct
drm_encoder
*
encoder
)
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_mode.h
浏览文件 @
5b8f0be0
...
...
@@ -172,6 +172,7 @@ enum radeon_connector_table {
struct
radeon_mode_info
{
struct
atom_context
*
atom_context
;
struct
card_info
*
atom_card_info
;
enum
radeon_connector_table
connector_table
;
bool
mode_config_initialized
;
struct
radeon_crtc
*
crtcs
[
2
];
...
...
@@ -186,17 +187,6 @@ struct radeon_mode_info {
};
struct
radeon_native_mode
{
/* preferred mode */
uint32_t
panel_xres
,
panel_yres
;
uint32_t
hoverplus
,
hsync_width
;
uint32_t
hblank
;
uint32_t
voverplus
,
vsync_width
;
uint32_t
vblank
;
uint32_t
dotclock
;
uint32_t
flags
;
};
#define MAX_H_CODE_TIMING_LEN 32
#define MAX_V_CODE_TIMING_LEN 32
...
...
@@ -228,7 +218,7 @@ struct radeon_crtc {
enum
radeon_rmx_type
rmx_type
;
fixed20_12
vsc
;
fixed20_12
hsc
;
struct
radeon_native
_mode
native_mode
;
struct
drm_display
_mode
native_mode
;
};
struct
radeon_encoder_primary_dac
{
...
...
@@ -248,7 +238,7 @@ struct radeon_encoder_lvds {
bool
use_bios_dividers
;
uint32_t
lvds_gen_cntl
;
/* panel mode */
struct
radeon_native
_mode
native_mode
;
struct
drm_display
_mode
native_mode
;
};
struct
radeon_encoder_tv_dac
{
...
...
@@ -271,6 +261,16 @@ struct radeon_encoder_int_tmds {
struct
radeon_tmds_pll
tmds_pll
[
4
];
};
/* spread spectrum */
struct
radeon_atom_ss
{
uint16_t
percentage
;
uint8_t
type
;
uint8_t
step
;
uint8_t
delay
;
uint8_t
range
;
uint8_t
refdiv
;
};
struct
radeon_encoder_atom_dig
{
/* atom dig */
bool
coherent_mode
;
...
...
@@ -278,8 +278,9 @@ struct radeon_encoder_atom_dig {
/* atom lvds */
uint32_t
lvds_misc
;
uint16_t
panel_pwr_delay
;
struct
radeon_atom_ss
*
ss
;
/* panel mode */
struct
radeon_native
_mode
native_mode
;
struct
drm_display
_mode
native_mode
;
};
struct
radeon_encoder_atom_dac
{
...
...
@@ -294,7 +295,7 @@ struct radeon_encoder {
uint32_t
flags
;
uint32_t
pixel_clock
;
enum
radeon_rmx_type
rmx_type
;
struct
radeon_native
_mode
native_mode
;
struct
drm_display
_mode
native_mode
;
void
*
enc_priv
;
};
...
...
@@ -308,6 +309,8 @@ struct radeon_connector {
uint32_t
connector_id
;
uint32_t
devices
;
struct
radeon_i2c_chan
*
ddc_bus
;
/* some systems have a an hdmi and vga port with a shared ddc line */
bool
shared_ddc
;
bool
use_digital
;
/* we need to mind the EDID between detect
and get modes due to analog/digital/tvencoder */
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_reg.h
浏览文件 @
5b8f0be0
...
...
@@ -290,6 +290,8 @@
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
# define RS600_BUS_MASTER_DIS (1 << 14)
# define RS600_MSI_REARM (1 << 20)
/* rs600/rs690/rs740 */
# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
# define RADEON_BUS_RD_ABORT_EN (1 << 25)
# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
...
...
@@ -297,6 +299,9 @@
# define RADEON_BUS_READ_BURST (1 << 30)
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
/* rv370/rv380, rv410, r423/r430/r480, r5xx */
#define RADEON_MSI_REARM_EN 0x0160
# define RV370_MSI_REARM_EN (1 << 0)
/* #define RADEON_PCIE_INDEX 0x0030 */
/* #define RADEON_PCIE_DATA 0x0034 */
...
...
@@ -3311,6 +3316,7 @@
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
# define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)
# define RS400_MSI_REARM (1 << 3)
/* rs400/rs480 */
#define RADEON_AIC_LO_ADDR 0x01dc
#define RADEON_AIC_PT_BASE 0x01d8
#define RADEON_AIC_HI_ADDR 0x01e0
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_test.c
浏览文件 @
5b8f0be0
...
...
@@ -42,7 +42,7 @@ void radeon_test_moves(struct radeon_device *rdev)
/* Number of tests =
* (Total GTT - IB pool - writeback page - ring buffer) / test size
*/
n
=
(
rdev
->
mc
.
gtt_size
-
RADEON_IB_POOL_SIZE
*
64
*
1024
-
4096
-
n
=
(
rdev
->
mc
.
gtt_size
-
RADEON_IB_POOL_SIZE
*
64
*
1024
-
RADEON_GPU_PAGE_SIZE
-
rdev
->
cp
.
ring_size
)
/
size
;
gtt_obj
=
kzalloc
(
n
*
sizeof
(
*
gtt_obj
),
GFP_KERNEL
);
...
...
@@ -102,7 +102,7 @@ void radeon_test_moves(struct radeon_device *rdev)
goto
out_cleanup
;
}
r
=
radeon_copy
(
rdev
,
gtt_addr
,
vram_addr
,
size
/
4096
,
fence
);
r
=
radeon_copy
(
rdev
,
gtt_addr
,
vram_addr
,
size
/
RADEON_GPU_PAGE_SIZE
,
fence
);
if
(
r
)
{
DRM_ERROR
(
"Failed GTT->VRAM copy %d
\n
"
,
i
);
goto
out_cleanup
;
...
...
@@ -145,7 +145,7 @@ void radeon_test_moves(struct radeon_device *rdev)
goto
out_cleanup
;
}
r
=
radeon_copy
(
rdev
,
vram_addr
,
gtt_addr
,
size
/
4096
,
fence
);
r
=
radeon_copy
(
rdev
,
vram_addr
,
gtt_addr
,
size
/
RADEON_GPU_PAGE_SIZE
,
fence
);
if
(
r
)
{
DRM_ERROR
(
"Failed VRAM->GTT copy %d
\n
"
,
i
);
goto
out_cleanup
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/radeon_ttm.c
浏览文件 @
5b8f0be0
...
...
@@ -295,6 +295,12 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
if
(
unlikely
(
r
))
{
return
r
;
}
r
=
ttm_tt_set_placement_caching
(
bo
->
ttm
,
tmp_mem
.
placement
);
if
(
unlikely
(
r
))
{
goto
out_cleanup
;
}
r
=
ttm_tt_bind
(
bo
->
ttm
,
&
tmp_mem
);
if
(
unlikely
(
r
))
{
goto
out_cleanup
;
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/rs400.c
浏览文件 @
5b8f0be0
...
...
@@ -418,6 +418,8 @@ int rs400_resume(struct radeon_device *rdev)
rs400_gart_disable
(
rdev
);
/* Resume clock before doing reset */
r300_clock_startup
(
rdev
);
/* setup MC before calling post tables */
rs400_mc_program
(
rdev
);
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
if
(
radeon_gpu_reset
(
rdev
))
{
dev_warn
(
rdev
->
dev
,
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)
\n
"
,
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/rs600.c
浏览文件 @
5b8f0be0
...
...
@@ -242,7 +242,7 @@ void rs600_irq_disable(struct radeon_device *rdev)
int
rs600_irq_process
(
struct
radeon_device
*
rdev
)
{
uint32_t
status
;
uint32_t
status
,
msi_rearm
;
uint32_t
r500_disp_int
;
status
=
rs600_irq_ack
(
rdev
,
&
r500_disp_int
);
...
...
@@ -260,6 +260,22 @@ int rs600_irq_process(struct radeon_device *rdev)
drm_handle_vblank
(
rdev
->
ddev
,
1
);
status
=
rs600_irq_ack
(
rdev
,
&
r500_disp_int
);
}
if
(
rdev
->
msi_enabled
)
{
switch
(
rdev
->
family
)
{
case
CHIP_RS600
:
case
CHIP_RS690
:
case
CHIP_RS740
:
msi_rearm
=
RREG32
(
RADEON_BUS_CNTL
)
&
~
RS600_MSI_REARM
;
WREG32
(
RADEON_BUS_CNTL
,
msi_rearm
);
WREG32
(
RADEON_BUS_CNTL
,
msi_rearm
|
RS600_MSI_REARM
);
break
;
default:
msi_rearm
=
RREG32
(
RADEON_MSI_REARM_EN
)
&
~
RV370_MSI_REARM_EN
;
WREG32
(
RADEON_MSI_REARM_EN
,
msi_rearm
);
WREG32
(
RADEON_MSI_REARM_EN
,
msi_rearm
|
RV370_MSI_REARM_EN
);
break
;
}
}
return
IRQ_HANDLED
;
}
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/rv515.c
浏览文件 @
5b8f0be0
...
...
@@ -137,6 +137,8 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev)
void
rv515_vga_render_disable
(
struct
radeon_device
*
rdev
)
{
WREG32
(
R_000330_D1VGA_CONTROL
,
0
);
WREG32
(
R_000338_D2VGA_CONTROL
,
0
);
WREG32
(
R_000300_VGA_RENDER_CONTROL
,
RREG32
(
R_000300_VGA_RENDER_CONTROL
)
&
C_000300_VGA_VSTATUS_CNTL
);
}
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/rv770.c
浏览文件 @
5b8f0be0
...
...
@@ -529,11 +529,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
if
(
rdev
->
family
==
CHIP_RV770
)
gb_tiling_config
|=
BANK_TILING
(
1
);
else
gb_tiling_config
|=
BANK_TILING
((
mc_arb_ramcfg
&
NOOFBANK_
SHIFT
)
>>
NOOFBANK_MASK
);
gb_tiling_config
|=
BANK_TILING
((
mc_arb_ramcfg
&
NOOFBANK_
MASK
)
>>
NOOFBANK_SHIFT
);
gb_tiling_config
|=
GROUP_SIZE
(
0
);
if
(((
mc_arb_ramcfg
&
NOOFROWS_MASK
)
&
NOOFROWS_SHIFT
)
>
3
)
{
if
(((
mc_arb_ramcfg
&
NOOFROWS_MASK
)
>>
NOOFROWS_SHIFT
)
>
3
)
{
gb_tiling_config
|=
ROW_TILING
(
3
);
gb_tiling_config
|=
SAMPLE_SPLIT
(
3
);
}
else
{
...
...
@@ -579,14 +579,14 @@ static void rv770_gpu_init(struct radeon_device *rdev)
/* set HW defaults for 3D engine */
WREG32
(
CP_QUEUE_THRESHOLDS
,
(
ROQ_IB1_START
(
0x16
)
|
ROQ_IB2_START
(
0x2b
)));
ROQ_IB2_START
(
0x2b
)));
WREG32
(
CP_MEQ_THRESHOLDS
,
STQ_SPLIT
(
0x30
));
WREG32
(
TA_CNTL_AUX
,
(
DISABLE_CUBE_ANISO
|
SYNC_GRADIENT
|
SYNC_WALKER
|
SYNC_ALIGNER
));
SYNC_GRADIENT
|
SYNC_WALKER
|
SYNC_ALIGNER
));
sx_debug_1
=
RREG32
(
SX_DEBUG_1
);
sx_debug_1
|=
ENABLE_NEW_SMX_ADDRESS
;
...
...
@@ -598,9 +598,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32
(
SMX_DC_CTL0
,
smx_dc_ctl0
);
WREG32
(
SMX_EVENT_CTL
,
(
ES_FLUSH_CTL
(
4
)
|
GS_FLUSH_CTL
(
4
)
|
ACK_FLUSH_CTL
(
3
)
|
SYNC_FLUSH_CTL
));
GS_FLUSH_CTL
(
4
)
|
ACK_FLUSH_CTL
(
3
)
|
SYNC_FLUSH_CTL
));
if
(
rdev
->
family
==
CHIP_RV770
)
WREG32
(
DB_DEBUG3
,
DB_CLK_OFF_DELAY
(
0x1f
));
...
...
@@ -611,12 +611,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
}
WREG32
(
SX_EXPORT_BUFFER_SIZES
,
(
COLOR_BUFFER_SIZE
((
rdev
->
config
.
rv770
.
sx_max_export_size
/
4
)
-
1
)
|
POSITION_BUFFER_SIZE
((
rdev
->
config
.
rv770
.
sx_max_export_pos_size
/
4
)
-
1
)
|
SMX_BUFFER_SIZE
((
rdev
->
config
.
rv770
.
sx_max_export_smx_size
/
4
)
-
1
)));
POSITION_BUFFER_SIZE
((
rdev
->
config
.
rv770
.
sx_max_export_pos_size
/
4
)
-
1
)
|
SMX_BUFFER_SIZE
((
rdev
->
config
.
rv770
.
sx_max_export_smx_size
/
4
)
-
1
)));
WREG32
(
PA_SC_FIFO_SIZE
,
(
SC_PRIM_FIFO_SIZE
(
rdev
->
config
.
rv770
.
sc_prim_fifo_size
)
|
SC_HIZ_TILE_FIFO_SIZE
(
rdev
->
config
.
rv770
.
sc_hiz_tile_fifo_size
)
|
SC_EARLYZ_TILE_FIFO_SIZE
(
rdev
->
config
.
rv770
.
sc_earlyz_tile_fifo_fize
)));
SC_HIZ_TILE_FIFO_SIZE
(
rdev
->
config
.
rv770
.
sc_hiz_tile_fifo_size
)
|
SC_EARLYZ_TILE_FIFO_SIZE
(
rdev
->
config
.
rv770
.
sc_earlyz_tile_fifo_fize
)));
WREG32
(
PA_SC_MULTI_CHIP_CNTL
,
0
);
...
...
@@ -774,14 +774,36 @@ int rv770_mc_init(struct radeon_device *rdev)
{
fixed20_12
a
;
u32
tmp
;
int
chansize
,
numchan
;
int
r
;
/* Get VRAM informations */
/* FIXME: Don't know how to determine vram width, need to check
* vram_width usage
*/
rdev
->
mc
.
vram_width
=
128
;
rdev
->
mc
.
vram_is_ddr
=
true
;
tmp
=
RREG32
(
MC_ARB_RAMCFG
);
if
(
tmp
&
CHANSIZE_OVERRIDE
)
{
chansize
=
16
;
}
else
if
(
tmp
&
CHANSIZE_MASK
)
{
chansize
=
64
;
}
else
{
chansize
=
32
;
}
tmp
=
RREG32
(
MC_SHARED_CHMAP
);
switch
((
tmp
&
NOOFCHAN_MASK
)
>>
NOOFCHAN_SHIFT
)
{
case
0
:
default:
numchan
=
1
;
break
;
case
1
:
numchan
=
2
;
break
;
case
2
:
numchan
=
4
;
break
;
case
3
:
numchan
=
8
;
break
;
}
rdev
->
mc
.
vram_width
=
numchan
*
chansize
;
/* Could aper size report 0 ? */
rdev
->
mc
.
aper_base
=
drm_get_resource_start
(
rdev
->
ddev
,
0
);
rdev
->
mc
.
aper_size
=
drm_get_resource_len
(
rdev
->
ddev
,
0
);
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/radeon/rv770d.h
浏览文件 @
5b8f0be0
...
...
@@ -129,6 +129,10 @@
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define HDP_TILING_CONFIG 0x2F3C
#define MC_SHARED_CHMAP 0x2004
#define NOOFCHAN_SHIFT 12
#define NOOFCHAN_MASK 0x00003000
#define MC_ARB_RAMCFG 0x2760
#define NOOFBANK_SHIFT 0
#define NOOFBANK_MASK 0x00000003
...
...
@@ -142,6 +146,7 @@
#define CHANSIZE_MASK 0x00000100
#define BURSTLENGTH_SHIFT 9
#define BURSTLENGTH_MASK 0x00000200
#define CHANSIZE_OVERRIDE (1 << 11)
#define MC_VM_AGP_TOP 0x2028
#define MC_VM_AGP_BOT 0x202C
#define MC_VM_AGP_BASE 0x2030
...
...
This diff is collapsed.
Click to expand it.
drivers/gpu/drm/ttm/ttm_tt.c
浏览文件 @
5b8f0be0
...
...
@@ -279,6 +279,7 @@ int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement)
return
ttm_tt_set_caching
(
ttm
,
state
);
}
EXPORT_SYMBOL
(
ttm_tt_set_placement_caching
);
static
void
ttm_tt_free_alloced_pages
(
struct
ttm_tt
*
ttm
)
{
...
...
This diff is collapsed.
Click to expand it.
include/drm/drm.h
浏览文件 @
5b8f0be0
...
...
@@ -454,6 +454,7 @@ struct drm_irq_busid {
enum
drm_vblank_seq_type
{
_DRM_VBLANK_ABSOLUTE
=
0x0
,
/**< Wait for specific vblank sequence number */
_DRM_VBLANK_RELATIVE
=
0x1
,
/**< Wait for given number of vblanks */
_DRM_VBLANK_EVENT
=
0x4000000
,
/**< Send event instead of blocking */
_DRM_VBLANK_FLIP
=
0x8000000
,
/**< Scheduled buffer swap should flip */
_DRM_VBLANK_NEXTONMISS
=
0x10000000
,
/**< If missed, wait for next vblank */
_DRM_VBLANK_SECONDARY
=
0x20000000
,
/**< Secondary display controller */
...
...
@@ -461,8 +462,8 @@ enum drm_vblank_seq_type {
};
#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_
SIGNAL | _DRM_VBLANK_SECONDARY
| \
_DRM_VBLANK_NEXTONMISS)
#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_
EVENT | _DRM_VBLANK_SIGNAL
| \
_DRM_VBLANK_
SECONDARY | _DRM_VBLANK_
NEXTONMISS)
struct
drm_wait_vblank_request
{
enum
drm_vblank_seq_type
type
;
...
...
@@ -698,6 +699,34 @@ struct drm_gem_open {
#define DRM_COMMAND_BASE 0x40
#define DRM_COMMAND_END 0xA0
/**
* Header for events written back to userspace on the drm fd. The
* type defines the type of event, the length specifies the total
* length of the event (including the header), and user_data is
* typically a 64 bit value passed with the ioctl that triggered the
* event. A read on the drm fd will always only return complete
* events, that is, if for example the read buffer is 100 bytes, and
* there are two 64 byte events pending, only one will be returned.
*
* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
* up are chipset specific.
*/
struct
drm_event
{
__u32
type
;
__u32
length
;
};
#define DRM_EVENT_VBLANK 0x01
struct
drm_event_vblank
{
struct
drm_event
base
;
__u64
user_data
;
__u32
tv_sec
;
__u32
tv_usec
;
__u32
sequence
;
__u32
reserved
;
};
/* typedef area */
#ifndef __KERNEL__
typedef
struct
drm_clip_rect
drm_clip_rect_t
;
...
...
This diff is collapsed.
Click to expand it.
include/drm/drmP.h
浏览文件 @
5b8f0be0
...
...
@@ -426,6 +426,14 @@ struct drm_buf_entry {
struct
drm_freelist
freelist
;
};
/* Event queued up for userspace to read */
struct
drm_pending_event
{
struct
drm_event
*
event
;
struct
list_head
link
;
struct
drm_file
*
file_priv
;
void
(
*
destroy
)(
struct
drm_pending_event
*
event
);
};
/** File private data */
struct
drm_file
{
int
authenticated
;
...
...
@@ -449,6 +457,10 @@ struct drm_file {
struct
drm_master
*
master
;
/* master this node is currently associated with
N.B. not always minor->master */
struct
list_head
fbs
;
wait_queue_head_t
event_wait
;
struct
list_head
event_list
;
int
event_space
;
};
/** Wait queue */
...
...
@@ -900,6 +912,12 @@ struct drm_minor {
struct
drm_mode_group
mode_group
;
};
struct
drm_pending_vblank_event
{
struct
drm_pending_event
base
;
int
pipe
;
struct
drm_event_vblank
event
;
};
/**
* DRM device structure. This structure represent a complete card that
* may contain multiple heads.
...
...
@@ -999,6 +1017,12 @@ struct drm_device {
u32
max_vblank_count
;
/**< size of vblank counter register */
/**
* List of events
*/
struct
list_head
vblank_event_list
;
spinlock_t
event_lock
;
/*@} */
cycles_t
ctx_start
;
cycles_t
lck_start
;
...
...
@@ -1135,6 +1159,8 @@ extern int drm_lastclose(struct drm_device *dev);
extern
int
drm_open
(
struct
inode
*
inode
,
struct
file
*
filp
);
extern
int
drm_stub_open
(
struct
inode
*
inode
,
struct
file
*
filp
);
extern
int
drm_fasync
(
int
fd
,
struct
file
*
filp
,
int
on
);
extern
ssize_t
drm_read
(
struct
file
*
filp
,
char
__user
*
buffer
,
size_t
count
,
loff_t
*
offset
);
extern
int
drm_release
(
struct
inode
*
inode
,
struct
file
*
filp
);
/* Mapping support (drm_vm.h) */
...
...
This diff is collapsed.
Click to expand it.
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