提交 598056d5 编写于 作者: N Nick Piggin 提交者: Paul Mackerras

[POWERPC] Fix rmb to order cacheable vs. noncacheable

lwsync is explicitly defined not to have any effect on the ordering of
accesses to device memory, so it cannot be used for rmb(). sync appears
to be the only barrier which fits the bill.
Signed-off-by: NNick Piggin <npiggin@suse.de>
Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
上级 a9653cf5
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
* SMP since it is only used to order updates to system memory. * SMP since it is only used to order updates to system memory.
*/ */
#define mb() __asm__ __volatile__ ("sync" : : : "memory") #define mb() __asm__ __volatile__ ("sync" : : : "memory")
#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory") #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
#define wmb() __asm__ __volatile__ ("sync" : : : "memory") #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
#define read_barrier_depends() do { } while(0) #define read_barrier_depends() do { } while(0)
......
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