[Blackfin] arch: remove useless IRQ_SW_INT defines

IRQ_SW_INT1 and IRQ_SW_INT2 obsolete:
Remove useless defines
Fix SYS_IRQS
Keep numbering scheme, so we don't break existing configurations.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

include/asm-blackfin/mach-bf533/irq.h

@@ -66,12 +66,13 @@ Core        Emulation               **
 	    DMA8/9 Interrupt	    IVG13	28
 	    DMA10/11 Interrupt	    IVG13	29
 	    Watchdog Timer	    IVG13	30
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
+
+            Softirq		    IVG14       31
+            System Call    --
                  (lowest priority)  IVG15       32 *
  */
-#define SYS_IRQS		32
-#define NR_PERI_INTS    24
+#define SYS_IRQS	31
+#define NR_PERI_INTS	24
 
 /* The ABSTRACT IRQ definitions */
 /** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core        Emulation               **
 #define	IRQ_SPORT0_TX		17	/*DMA2 Interrupt (SPORT0 TX) */
 #define	IRQ_SPORT1_RX		18	/*DMA3 Interrupt (SPORT1 RX) */
 #define	IRQ_SPORT1_TX		19	/*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI			20	/*DMA5 Interrupt (SPI) */
+#define 	IRQ_SPI			20	/*DMA5 Interrupt (SPI) */
 #define	IRQ_UART_RX		21	/*DMA6 Interrupt (UART RX) */
 #define	IRQ_UART_TX		22	/*DMA7 Interrupt (UART TX) */
 #define	IRQ_TMR0		23	/*Timer 0 */
@@ -108,9 +109,6 @@ Core        Emulation               **
 #define	IRQ_MEM_DMA1		29	/*DMA10/11 Interrupt (Memory DMA Stream 1) */
 #define	IRQ_WATCH	   	30	/*Watch Dog Timer */
 
-#define	IRQ_SW_INT1		31	/*Software Int 1 */
-#define	IRQ_SW_INT2		32	/*Software Int 2 (reserved for SYSCALL) */
-
 #define IRQ_PF0			33
 #define IRQ_PF1			34
 #define IRQ_PF2			35

include/asm-blackfin/mach-bf537/irq.h

@@ -34,24 +34,23 @@
 
 /*
  * Interrupt source definitions
-             Event Source    Core Event Name
-Core        Emulation               **
- Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-
-.....
-
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
-                 (lowest priority)  IVG15       32 *
+ *            Event Source    Core Event Name
+ * Core       Emulation               **
+ * Events         (highest priority)  EMU         0
+ *            Reset                   RST         1
+ *            NMI                     NMI         2
+ *            Exception               EVX         3
+ *            Reserved                --          4
+ *            Hardware Error          IVHW        5
+ *            Core Timer              IVTMR       6
+ *  .....
+ *
+ *            Softirq		      IVG14
+ *            System Call    --
+ *               (lowest priority)    IVG15
  */
 
-#define SYS_IRQS        41
+#define SYS_IRQS        39
 #define NR_PERI_INTS    32
 
 /* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core        Emulation               **
 #define IRQ_PORTG_INTB      35	/* PF Port G (PF15:0) Interrupt B */
 #define IRQ_MEM_DMA0        36	/*(Memory DMA Stream 0) */
 #define IRQ_MEM_DMA1        37	/*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB	    38	/* PF Ports F (PF15:0) Interrupt B */
+#define IRQ_PROG_INTB	      38	/* PF Ports F (PF15:0) Interrupt B */
 #define IRQ_WATCH           38	/*Watch Dog Timer */
-#define IRQ_SW_INT1         40	/*Software Int 1 */
-#define IRQ_SW_INT2         41	/*Software Int 2 (reserved for SYSCALL) */
 
 #define IRQ_PPI_ERROR       42	/*PPI Error Interrupt */
 #define IRQ_CAN_ERROR       43	/*CAN Error Interrupt */

include/asm-blackfin/mach-bf561/irq.h

@@ -118,12 +118,13 @@
 	    Supplemental interrupt 0		IVG7	    69
 	    supplemental interrupt 1		IVG7	    70
 
-            Software Interrupt 1		IVG14       71
-            Software Interrupt 2		IVG15       72 *
-						(lowest priority)
+            Softirq		    		IVG14
+            System Call    --
+                 (lowest priority)  		IVG15
+
  **********************************************************************/
 
-#define SYS_IRQS		72
+#define SYS_IRQS		71
 #define NR_PERI_INTS		64
 
 /*
@@ -237,9 +238,7 @@
 #define IRQ_RESERVED_2		(IVG_BASE + 61)	/* Reserved interrupt       */
 #define IRQ_SUPPLE_0		(IVG_BASE + 62)	/* Supplemental interrupt 0 */
 #define IRQ_SUPPLE_1		(IVG_BASE + 63)	/* supplemental interrupt 1 */
-#define	IRQ_SW_INT1		71	/* Software Interrupt 1     */
-#define	IRQ_SW_INT2		72	/* Software Interrupt 2     */
-						/* reserved for SYSCALL */
+
 #define IRQ_PF0			73
 #define IRQ_PF1			74
 #define IRQ_PF2			75