powerpc/85xx: p2020rdb & p1010rdb - lower spi flash freq to 40Mhz
This is here most likely since the FSL bsp. Back in the FSL bsp it was set to 50Mhz and working. However the driver divided the SoC freq. only by 2. According to the TRM the platform clock (which the manual refers in its formula) is the system clock divided by two. So in the end it has to divide by 4 and this is what the fsl-spi driver in tree is doing. Since then the flash is not wokring I guess. After chaning the freq from 50Mhz to 40Mhz like others do then I can access the flash. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Showing
想要评论请 注册 或 登录