Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
大约 1 年 前同步成功

通知 158
Star 36
Fork 7
cloud-kernel
cloud-kernel

体验新版 GitCode，发现更多精彩内容 >>

提交 51fd554b 编写于 作者: J Jean Delvare 提交者： Jean Delvare
浏览文件
操作

i2c: Delete the broken i2c-ite bus driver 

The rest of the ITE8172 support was already removed from MIPS tree.
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
上级 36cfb5cc
展开全部 隐藏空白更改
内联 并排
Showing with 0 addition and 1312 deletion
Documentation/feature-removal-schedule.txt
浏览文件 @ 51fd554b
......@@ -216,17 +216,6 @@ Who: Thomas Gleixner <tglx@linutronix.de>
---------------------------
What: i2c-ite and i2c-algo-ite drivers
When: September 2006
Why: These drivers never compiled since they were added to the kernel
tree 5 years ago. This feature removal can be reevaluated if
someone shows interest in the drivers, fixes them and takes over
maintenance.
http://marc.theaimsgroup.com/?l=linux-mips&m=115040510817448
Who: Jean Delvare <khali@linux-fr.org>
---------------------------
What: Bridge netfilter deferred IPv4/IPv6 output hook calling
When: January 2007
Why: The deferred output hooks are a layering violation causing unusual
......
drivers/i2c/algos/Kconfig
浏览文件 @ 51fd554b
......@@ -38,17 +38,6 @@ config I2C_ALGOPCA
This support is also available as a module. If so, the module
will be called i2c-algo-pca.
config I2C_ALGOITE
tristate "ITE I2C Algorithm"
depends on MIPS_ITE8172 && I2C
help
This supports the use of the ITE8172 I2C interface found on some MIPS
systems. Say Y if you have one of these. You should also say Y for
the ITE I2C peripheral driver support below.
This support is also available as a module. If so, the module
will be called i2c-algo-ite.
config I2C_ALGO8XX
tristate "MPC8xx CPM I2C interface"
depends on 8xx && I2C
......
drivers/i2c/algos/Makefile
浏览文件 @ 51fd554b
......@@ -5,7 +5,6 @@
obj-$(CONFIG_I2C_ALGOBIT) += i2c-algo-bit.o
obj-$(CONFIG_I2C_ALGOPCF) += i2c-algo-pcf.o
obj-$(CONFIG_I2C_ALGOPCA) += i2c-algo-pca.o
obj-$(CONFIG_I2C_ALGOITE) += i2c-algo-ite.o
obj-$(CONFIG_I2C_ALGO_SGI) += i2c-algo-sgi.o
ifeq ($(CONFIG_I2C_DEBUG_ALGO),y)
......
drivers/i2c/algos/i2c-algo-ite.c 已删除 100644 → 0
浏览文件 @ 36cfb5cc
此差异已折叠。
drivers/i2c/algos/i2c-algo-ite.h 已删除 100644 → 0
浏览文件 @ 36cfb5cc
/*
--------------------------------------------------------------------
i2c-ite.h: Global defines for the I2C controller on board the
ITE MIPS processor.
--------------------------------------------------------------------
Hai-Pao Fan, MontaVista Software, Inc.
hpfan@mvista.com or source@mvista.com
Copyright 2001 MontaVista Software Inc.
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef I2C_ITE_H
#define I2C_ITE_H 1
#include <asm/it8172/it8172.h>
/* I2C Registers */
#define ITE_I2CHCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x30
#define ITE_I2CHSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x34
#define ITE_I2CSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x38
#define ITE_I2CSSAR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x3c
#define ITE_I2CCKCNT IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x48
#define ITE_I2CSHDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x4c
#define ITE_I2CRSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x50
#define ITE_I2CPSUR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x54
#define ITE_I2CFDR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x70
#define ITE_I2CFBCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x74
#define ITE_I2CFCR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x78
#define ITE_I2CFSR IT8172_PCI_IO_BASE + IT_I2C_BASE + 0x7c
/* Host Control Register ITE_I2CHCR */
#define ITE_I2CHCR_HCE 0x01 /* Enable I2C Host Controller */
#define ITE_I2CHCR_IE 0x02 /* Enable the interrupt after completing
the current transaction */
#define ITE_I2CHCR_CP_W 0x00 /* bit2-4 000 - Write */
#define ITE_I2CHCR_CP_R 0x08 /* 010 - Current address read */
#define ITE_I2CHCR_CP_S 0x10 /* 100 - Sequential read */
#define ITE_I2CHCR_ST 0x20 /* Initiates the I2C host controller to execute
the command and send the data programmed in
all required registers to I2C bus */
#define ITE_CMD ITE_I2CHCR_HCE | ITE_I2CHCR_IE | ITE_I2CHCR_ST
#define ITE_WRITE ITE_CMD | ITE_I2CHCR_CP_W
#define ITE_READ ITE_CMD | ITE_I2CHCR_CP_R
#define ITE_SREAD ITE_CMD | ITE_I2CHCR_CP_S
/* Host Status Register ITE_I2CHSR */
#define ITE_I2CHSR_DB 0x01 /* Device is busy, receives NACK response except
in the first and last bytes */
#define ITE_I2CHSR_DNE 0x02 /* Target address on I2C bus does not exist */
#define ITE_I2CHSR_TDI 0x04 /* R/W Transaction on I2C bus was completed */
#define ITE_I2CHSR_HB 0x08 /* Host controller is processing transactions */
#define ITE_I2CHSR_FER 0x10 /* Error occurs in the FIFO */
/* Slave Address Register ITE_I2CSAR */
#define ITE_I2CSAR_SA_MASK 0xfe /* Target I2C device address */
#define ITE_I2CSAR_ASO 0x0100 /* Output 1/0 to I2CAS port when the
next slave address is addressed */
/* Slave Sub-address Register ITE_I2CSSAR */
#define ITE_I2CSSAR_SUBA_MASK 0xff /* Target I2C device sub-address */
/* Clock Counter Register ITE_I2CCKCNT */
#define ITE_I2CCKCNT_STOP 0x00 /* stop I2C clock */
#define ITE_I2CCKCNT_HPCC_MASK 0x7f /* SCL high period counter */
#define ITE_I2CCKCNT_LPCC_MASK 0x7f00 /* SCL low period counter */
/* START Hold Time Register ITE_I2CSHDR */
/* value is counted based on 16 MHz internal clock */
#define ITE_I2CSHDR_FM 0x0a /* START condition at fast mode */
#define ITE_I2CSHDR_SM 0x47 /* START contition at standard mode */
/* (Repeated) START Setup Time Register ITE_I2CRSUR */
/* value is counted based on 16 MHz internal clock */
#define ITE_I2CRSUR_FM 0x0a /* repeated START condition at fast mode */
#define ITE_I2CRSUR_SM 0x50 /* repeated START condition at standard mode */
/* STOP setup Time Register ITE_I2CPSUR */
/* FIFO Data Register ITE_I2CFDR */
#define ITE_I2CFDR_MASK 0xff
/* FIFO Byte Count Register ITE_I2CFBCR */
#define ITE_I2CFBCR_MASK 0x3f
/* FIFO Control Register ITE_I2CFCR */
#define ITE_I2CFCR_FLUSH 0x01 /* Flush FIFO and reset the FIFO point
and I2CFSR */
/* FIFO Status Register ITE_I2CFSR */
#define ITE_I2CFSR_FO 0x01 /* FIFO is overrun when write */
#define ITE_I2CFSR_FU 0x02 /* FIFO is underrun when read */
#define ITE_I2CFSR_FF 0x04 /* FIFO is full when write */
#define ITE_I2CFSR_FE 0x08 /* FIFO is empty when read */
#endif /* I2C_ITE_H */
drivers/i2c/busses/Kconfig
浏览文件 @ 51fd554b
......@@ -209,18 +209,6 @@ config I2C_ISA
tristate
depends on I2C
config I2C_ITE
tristate "ITE I2C Adapter"
depends on I2C && MIPS_ITE8172
select I2C_ALGOITE
help
This supports the ITE8172 I2C peripheral found on some MIPS
systems. Say Y if you have one of these. You should also say Y for
the ITE I2C driver algorithm support above.
This support is also available as a module. If so, the module
will be called i2c-ite.
config I2C_IXP4XX
tristate "IXP4xx GPIO-Based I2C Interface"
depends on I2C && ARCH_IXP4XX
......
drivers/i2c/busses/Makefile
浏览文件 @ 51fd554b
......@@ -16,7 +16,6 @@ obj-$(CONFIG_I2C_I810) += i2c-i810.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
obj-$(CONFIG_I2C_ISA) += i2c-isa.o
obj-$(CONFIG_I2C_ITE) += i2c-ite.o
obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
obj-$(CONFIG_I2C_IXP4XX) += i2c-ixp4xx.o
obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
......
drivers/i2c/busses/i2c-ite.c 已删除 100644 → 0
浏览文件 @ 36cfb5cc
/*
-------------------------------------------------------------------------
i2c-adap-ite.c i2c-hw access for the IIC peripheral on the ITE MIPS system
-------------------------------------------------------------------------
Hai-Pao Fan, MontaVista Software, Inc.
hpfan@mvista.com or source@mvista.com
Copyright 2001 MontaVista Software Inc.
----------------------------------------------------------------------------
This file was highly leveraged from i2c-elektor.c, which was created
by Simon G. Vogl and Hans Berglund:
Copyright (C) 1995-97 Simon G. Vogl
1998-99 Hans Berglund
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* ------------------------------------------------------------------------- */
/* With some changes from Kysti Mlkki <kmalkki@cc.hut.fi> and even
Frodo Looijaard <frodol@dds.nl> */
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/wait.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-ite.h>
#include <linux/i2c-adap-ite.h>
#include "../i2c-ite.h"
#define DEFAULT_BASE 0x14014030
#define ITE_IIC_IO_SIZE 0x40
#define DEFAULT_IRQ 0
#define DEFAULT_CLOCK 0x1b0e /* default 16MHz/(27+14) = 400KHz */
#define DEFAULT_OWN 0x55
static int base;
static int irq;
static int clock;
static int own;
static struct iic_ite gpi;
static wait_queue_head_t iic_wait;
static int iic_pending;
static spinlock_t lock;
/* ----- local functions ---------------------------------------------- */
static void iic_ite_setiic(void *data, int ctl, short val)
{
unsigned long j = jiffies + 10;
pr_debug(" Write 0x%02x to 0x%x\n",(unsigned short)val, ctl&0xff);
#ifdef DEBUG
while (time_before(jiffies, j))
schedule();
#endif
outw(val,ctl);
}
static short iic_ite_getiic(void *data, int ctl)
{
short val;
val = inw(ctl);
pr_debug("Read 0x%02x from 0x%x\n",(unsigned short)val, ctl&0xff);
return (val);
}
/* Return our slave address. This is the address
* put on the I2C bus when another master on the bus wants to address us
* as a slave
*/
static int iic_ite_getown(void *data)
{
return (gpi.iic_own);
}
static int iic_ite_getclock(void *data)
{
return (gpi.iic_clock);
}
/* Put this process to sleep. We will wake up when the
* IIC controller interrupts.
*/
static void iic_ite_waitforpin(void) {
DEFINE_WAIT(wait);
int timeout = 2;
unsigned long flags;
/* If interrupts are enabled (which they are), then put the process to
* sleep. This process will be awakened by two events -- either the
* the IIC peripheral interrupts or the timeout expires.
* If interrupts are not enabled then delay for a reasonable amount
* of time and return.
*/
if (gpi.iic_irq > 0) {
spin_lock_irqsave(&lock, flags);
if (iic_pending == 0) {
spin_unlock_irqrestore(&lock, flags);
prepare_to_wait(&iic_wait, &wait, TASK_INTERRUPTIBLE);
if (schedule_timeout(timeout*HZ)) {
spin_lock_irqsave(&lock, flags);
if (iic_pending == 1) {
iic_pending = 0;
}
spin_unlock_irqrestore(&lock, flags);
}
finish_wait(&iic_wait, &wait);
} else {
iic_pending = 0;
spin_unlock_irqrestore(&lock, flags);
}
} else {
udelay(100);
}
}
static irqreturn_t iic_ite_handler(int this_irq, void *dev_id)
{
spin_lock(&lock);
iic_pending = 1;
spin_unlock(&lock);
wake_up_interruptible(&iic_wait);
return IRQ_HANDLED;
}
/* Lock the region of memory where I/O registers exist. Request our
* interrupt line and register its associated handler.
*/
static int iic_hw_resrc_init(void)
{
if (!request_region(gpi.iic_base, ITE_IIC_IO_SIZE, "i2c"))
return -ENODEV;
if (gpi.iic_irq <= 0)
return 0;
if (request_irq(gpi.iic_irq, iic_ite_handler, 0, "ITE IIC", 0) < 0)
gpi.iic_irq = 0;
else
enable_irq(gpi.iic_irq);
return 0;
}
static void iic_ite_release(void)
{
if (gpi.iic_irq > 0) {
disable_irq(gpi.iic_irq);
free_irq(gpi.iic_irq, 0);
}
release_region(gpi.iic_base , 2);
}
/* ------------------------------------------------------------------------
* Encapsulate the above functions in the correct operations structure.
* This is only done when more than one hardware adapter is supported.
*/
static struct i2c_algo_iic_data iic_ite_data = {
NULL,
iic_ite_setiic,
iic_ite_getiic,
iic_ite_getown,
iic_ite_getclock,
iic_ite_waitforpin,
80, 80, 100, /* waits, timeout */
};
static struct i2c_adapter iic_ite_ops = {
.owner = THIS_MODULE,
.id = I2C_HW_I_IIC,
.algo_data = &iic_ite_data,
.name = "ITE IIC adapter",
};
/* Called when the module is loaded. This function starts the
* cascade of calls up through the hierarchy of i2c modules (i.e. up to the
* algorithm layer and into to the core layer)
*/
static int __init iic_ite_init(void)
{
struct iic_ite *piic = &gpi;
printk(KERN_INFO "Initialize ITE IIC adapter module\n");
if (base == 0)
piic->iic_base = DEFAULT_BASE;
else
piic->iic_base = base;
if (irq == 0)
piic->iic_irq = DEFAULT_IRQ;
else
piic->iic_irq = irq;
if (clock == 0)
piic->iic_clock = DEFAULT_CLOCK;
else
piic->iic_clock = clock;
if (own == 0)
piic->iic_own = DEFAULT_OWN;
else
piic->iic_own = own;
iic_ite_data.data = (void *)piic;
init_waitqueue_head(&iic_wait);
spin_lock_init(&lock);
if (iic_hw_resrc_init() == 0) {
if (i2c_iic_add_bus(&iic_ite_ops) < 0)
return -ENODEV;
} else {
return -ENODEV;
}
printk(KERN_INFO " found device at %#x irq %d.\n",
piic->iic_base, piic->iic_irq);
return 0;
}
static void iic_ite_exit(void)
{
i2c_iic_del_bus(&iic_ite_ops);
iic_ite_release();
}
/* If modules is NOT defined when this file is compiled, then the MODULE_*
* macros will resolve to nothing
*/
MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
MODULE_DESCRIPTION("I2C-Bus adapter routines for ITE IIC bus adapter");
MODULE_LICENSE("GPL");
module_param(base, int, 0);
module_param(irq, int, 0);
module_param(clock, int, 0);
module_param(own, int, 0);
/* Called when module is loaded or when kernel is initialized.
* If MODULES is defined when this file is compiled, then this function will
* resolve to init_module (the function called when insmod is invoked for a
* module). Otherwise, this function is called early in the boot, when the
* kernel is intialized. Check out /include/init.h to see how this works.
*/
module_init(iic_ite_init);
/* Resolves to module_cleanup when MODULES is defined. */
module_exit(iic_ite_exit);
include/linux/i2c-algo-ite.h 已删除 100644 → 0
浏览文件 @ 36cfb5cc
/* ------------------------------------------------------------------------- */
/* i2c-algo-ite.h i2c driver algorithms for ITE IIC adapters */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 1995-97 Simon G. Vogl
1998-99 Hans Berglund
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* ------------------------------------------------------------------------- */
/* With some changes from Kysti Mlkki <kmalkki@cc.hut.fi> and even
Frodo Looijaard <frodol@dds.nl> */
/* Modifications by MontaVista Software, 2001
Changes made to support the ITE IIC peripheral */
#ifndef I2C_ALGO_ITE_H
#define I2C_ALGO_ITE_H 1
#include <linux/types.h>
/* Example of a sequential read request:
struct i2c_iic_msg s_msg;
s_msg.addr=device_address;
s_msg.len=length;
s_msg.buf=buffer;
s_msg.waddr=word_address;
ioctl(file,I2C_SREAD, &s_msg);
*/
#define I2C_SREAD 0x780 /* SREAD ioctl command */
struct i2c_iic_msg {
__u16 addr; /* device address */
__u16 waddr; /* word address */
short len; /* msg length */
char *buf; /* pointer to msg data */
};
#ifdef __KERNEL__
struct i2c_adapter;
struct i2c_algo_iic_data {
void *data; /* private data for lolevel routines */
void (*setiic) (void *data, int ctl, int val);
int (*getiic) (void *data, int ctl);
int (*getown) (void *data);
int (*getclock) (void *data);
void (*waitforpin) (void);
/* local settings */
int udelay;
int mdelay;
int timeout;
};
int i2c_iic_add_bus(struct i2c_adapter *);
int i2c_iic_del_bus(struct i2c_adapter *);
#endif /* __KERNEL__ */
#endif /* I2C_ALGO_ITE_H */
include/linux/i2c-id.h
浏览文件 @ 51fd554b
......@@ -210,9 +210,6 @@
/* --- MPC8xx PowerPC adapters */
#define I2C_HW_MPC8XX_EPON 0x110000 /* Eponymous MPC8xx I2C adapter */
/* --- ITE based algorithms */
#define I2C_HW_I_IIC 0x080000 /* controller on the ITE */
/* --- PowerPC on-chip adapters */
#define I2C_HW_OCP 0x120000 /* IBM on-chip I2C adapter */
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或