Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
大约 1 年 前同步成功

通知 155
Star 36
Fork 7
cloud-kernel
cloud-kernel

体验新版 GitCode，发现更多精彩内容 >>

提交 51c9d654 编写于 作者: G Greg Kroah-Hartman
浏览文件
操作

Staging: delete tty drivers 

Delete the drivers/staging/tty drivers as no one has wanted to step up
and maintain and fix them.  This was discussed in commit
4a6514e6 (tty: move obsolete and broken
tty drivers to drivers/staging/tty/)

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Jiri Slaby <jslaby@suse.cz>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 bb2a97e9
展开全部 隐藏空白更改
内联 并排
Showing with 0 addition and 29526 deletion
drivers/staging/Kconfig
浏览文件 @ 51c9d654
......@@ -24,8 +24,6 @@ menuconfig STAGING
if STAGING
source "drivers/staging/tty/Kconfig"
source "drivers/staging/et131x/Kconfig"
source "drivers/staging/slicoss/Kconfig"
......
drivers/staging/Makefile
浏览文件 @ 51c9d654
......@@ -3,7 +3,6 @@
# fix for build system bug...
obj-$(CONFIG_STAGING) += staging.o
obj-y += tty/
obj-$(CONFIG_ET131X) += et131x/
obj-$(CONFIG_SLICOSS) += slicoss/
obj-$(CONFIG_VIDEO_GO7007) += go7007/
......
drivers/staging/tty/Kconfig 已删除 100644 → 0
浏览文件 @ bb2a97e9
config STALLION
tristate "Stallion EasyIO or EC8/32 support"
depends on STALDRV && (ISA || EISA || PCI)
help
If you have an EasyIO or EasyConnection 8/32 multiport Stallion
card, then this is for you; say Y. Make sure to read
<file:Documentation/serial/stallion.txt>.
To compile this driver as a module, choose M here: the
module will be called stallion.
config ISTALLION
tristate "Stallion EC8/64, ONboard, Brumby support"
depends on STALDRV && (ISA || EISA || PCI)
help
If you have an EasyConnection 8/64, ONboard, Brumby or Stallion
serial multiport card, say Y here. Make sure to read
<file:Documentation/serial/stallion.txt>.
To compile this driver as a module, choose M here: the
module will be called istallion.
config DIGIEPCA
tristate "Digiboard Intelligent Async Support"
depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI)
---help---
This is a driver for Digi International's Xx, Xeve, and Xem series
of cards which provide multiple serial ports. You would need
something like this to connect more than two modems to your Linux
box, for instance in order to become a dial-in server. This driver
supports the original PC (ISA) boards as well as PCI, and EISA. If
you have a card like this, say Y here and read the file
<file:Documentation/serial/digiepca.txt>.
To compile this driver as a module, choose M here: the
module will be called epca.
config RISCOM8
tristate "SDL RISCom/8 card support"
depends on SERIAL_NONSTANDARD
help
This is a driver for the SDL Communications RISCom/8 multiport card,
which gives you many serial ports. You would need something like
this to connect more than two modems to your Linux box, for instance
in order to become a dial-in server. If you have a card like that,
say Y here and read the file <file:Documentation/serial/riscom8.txt>.
Also it's possible to say M here and compile this driver as kernel
loadable module; the module will be called riscom8.
config SPECIALIX
tristate "Specialix IO8+ card support"
depends on SERIAL_NONSTANDARD
help
This is a driver for the Specialix IO8+ multiport card (both the
ISA and the PCI version) which gives you many serial ports. You
would need something like this to connect more than two modems to
your Linux box, for instance in order to become a dial-in server.
If you have a card like that, say Y here and read the file
<file:Documentation/serial/specialix.txt>. Also it's possible to say
M here and compile this driver as kernel loadable module which will be
called specialix.
config COMPUTONE
tristate "Computone IntelliPort Plus serial support"
depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI)
---help---
This driver supports the entire family of Intelliport II/Plus
controllers with the exception of the MicroChannel controllers and
products previous to the Intelliport II. These are multiport cards,
which give you many serial ports. You would need something like this
to connect more than two modems to your Linux box, for instance in
order to become a dial-in server. If you have a card like that, say
Y here and read <file:Documentation/serial/computone.txt>.
To compile this driver as module, choose M here: the
module will be called ip2.
config SERIAL167
bool "CD2401 support for MVME166/7 serial ports"
depends on MVME16x
help
This is the driver for the serial ports on the Motorola MVME166,
167, and 172 boards. Everyone using one of these boards should say
Y here.
drivers/staging/tty/Makefile 已删除 100644 → 0
浏览文件 @ bb2a97e9
obj-$(CONFIG_STALLION) += stallion.o
obj-$(CONFIG_ISTALLION) += istallion.o
obj-$(CONFIG_DIGIEPCA) += epca.o
obj-$(CONFIG_SERIAL167) += serial167.o
obj-$(CONFIG_SPECIALIX) += specialix.o
obj-$(CONFIG_RISCOM8) += riscom8.o
obj-$(CONFIG_COMPUTONE) += ip2/
drivers/staging/tty/TODO 已删除 100644 → 0
浏览文件 @ bb2a97e9
These are a few tty/serial drivers that either do not build,
or work if they do build, or if they seem to work, are for obsolete
hardware, or are full of unfixable races and no one uses them anymore.
If no one steps up to adopt any of these drivers, they will be removed
in the 2.6.41 release.
drivers/staging/tty/cd1865.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
/*
* linux/drivers/char/cd1865.h -- Definitions relating to the CD1865
* for the Specialix IO8+ multiport serial driver.
*
* Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl)
* Copyright (C) 1994-1996 Dmitry Gorodchanin (pgmdsg@ibi.com)
*
* Specialix pays for the development and support of this driver.
* Please DO contact io8-linux@specialix.co.uk if you require
* support.
*
* This driver was developed in the BitWizard linux device
* driver service. If you require a linux device driver for your
* product, please contact devices@BitWizard.nl for a quote.
*
*/
/*
* Definitions for Driving CD180/CD1864/CD1865 based eightport serial cards.
*/
/* Values of choice for Interrupt ACKs */
/* These values are "obligatory" if you use the register based
* interrupt acknowledgements. See page 99-101 of V2.0 of the CD1865
* databook */
#define SX_ACK_MINT 0x75 /* goes to PILR1 */
#define SX_ACK_TINT 0x76 /* goes to PILR2 */
#define SX_ACK_RINT 0x77 /* goes to PILR3 */
/* Chip ID (is used when chips ar daisy chained.) */
#define SX_ID 0x10
/* Definitions for Cirrus Logic CL-CD186x 8-port async mux chip */
#define CD186x_NCH 8 /* Total number of channels */
#define CD186x_TPC 16 /* Ticks per character */
#define CD186x_NFIFO 8 /* TX FIFO size */
/* Global registers */
#define CD186x_GIVR 0x40 /* Global Interrupt Vector Register */
#define CD186x_GICR 0x41 /* Global Interrupting Channel Register */
#define CD186x_PILR1 0x61 /* Priority Interrupt Level Register 1 */
#define CD186x_PILR2 0x62 /* Priority Interrupt Level Register 2 */
#define CD186x_PILR3 0x63 /* Priority Interrupt Level Register 3 */
#define CD186x_CAR 0x64 /* Channel Access Register */
#define CD186x_SRSR 0x65 /* Channel Access Register */
#define CD186x_GFRCR 0x6b /* Global Firmware Revision Code Register */
#define CD186x_PPRH 0x70 /* Prescaler Period Register High */
#define CD186x_PPRL 0x71 /* Prescaler Period Register Low */
#define CD186x_RDR 0x78 /* Receiver Data Register */
#define CD186x_RCSR 0x7a /* Receiver Character Status Register */
#define CD186x_TDR 0x7b /* Transmit Data Register */
#define CD186x_EOIR 0x7f /* End of Interrupt Register */
#define CD186x_MRAR 0x75 /* Modem Request Acknowledge register */
#define CD186x_TRAR 0x76 /* Transmit Request Acknowledge register */
#define CD186x_RRAR 0x77 /* Receive Request Acknowledge register */
#define CD186x_SRCR 0x66 /* Service Request Configuration register */
/* Channel Registers */
#define CD186x_CCR 0x01 /* Channel Command Register */
#define CD186x_IER 0x02 /* Interrupt Enable Register */
#define CD186x_COR1 0x03 /* Channel Option Register 1 */
#define CD186x_COR2 0x04 /* Channel Option Register 2 */
#define CD186x_COR3 0x05 /* Channel Option Register 3 */
#define CD186x_CCSR 0x06 /* Channel Control Status Register */
#define CD186x_RDCR 0x07 /* Receive Data Count Register */
#define CD186x_SCHR1 0x09 /* Special Character Register 1 */
#define CD186x_SCHR2 0x0a /* Special Character Register 2 */
#define CD186x_SCHR3 0x0b /* Special Character Register 3 */
#define CD186x_SCHR4 0x0c /* Special Character Register 4 */
#define CD186x_MCOR1 0x10 /* Modem Change Option 1 Register */
#define CD186x_MCOR2 0x11 /* Modem Change Option 2 Register */
#define CD186x_MCR 0x12 /* Modem Change Register */
#define CD186x_RTPR 0x18 /* Receive Timeout Period Register */
#define CD186x_MSVR 0x28 /* Modem Signal Value Register */
#define CD186x_MSVRTS 0x29 /* Modem Signal Value Register */
#define CD186x_MSVDTR 0x2a /* Modem Signal Value Register */
#define CD186x_RBPRH 0x31 /* Receive Baud Rate Period Register High */
#define CD186x_RBPRL 0x32 /* Receive Baud Rate Period Register Low */
#define CD186x_TBPRH 0x39 /* Transmit Baud Rate Period Register High */
#define CD186x_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */
/* Global Interrupt Vector Register (R/W) */
#define GIVR_ITMASK 0x07 /* Interrupt type mask */
#define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */
#define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */
#define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */
#define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */
/* Global Interrupt Channel Register (R/W) */
#define GICR_CHAN 0x1c /* Channel Number Mask */
#define GICR_CHAN_OFF 2 /* Channel Number shift */
/* Channel Address Register (R/W) */
#define CAR_CHAN 0x07 /* Channel Number Mask */
#define CAR_A7 0x08 /* A7 Address Extension (unused) */
/* Receive Character Status Register (R/O) */
#define RCSR_TOUT 0x80 /* Rx Timeout */
#define RCSR_SCDET 0x70 /* Special Character Detected Mask */
#define RCSR_NO_SC 0x00 /* No Special Characters Detected */
#define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
#define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
#define RCSR_SC_3 0x30 /* Special Char 3 Detected */
#define RCSR_SC_4 0x40 /* Special Char 4 Detected */
#define RCSR_BREAK 0x08 /* Break has been detected */
#define RCSR_PE 0x04 /* Parity Error */
#define RCSR_FE 0x02 /* Frame Error */
#define RCSR_OE 0x01 /* Overrun Error */
/* Channel Command Register (R/W) (commands in groups can be OR-ed) */
#define CCR_HARDRESET 0x81 /* Reset the chip */
#define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
#define CCR_SSCH1 0x21 /* Send Special Character 1 */
#define CCR_SSCH2 0x22 /* Send Special Character 2 */
#define CCR_SSCH3 0x23 /* Send Special Character 3 */
#define CCR_SSCH4 0x24 /* Send Special Character 4 */
#define CCR_TXEN 0x18 /* Enable Transmitter */
#define CCR_RXEN 0x12 /* Enable Receiver */
#define CCR_TXDIS 0x14 /* Disable Transmitter */
#define CCR_RXDIS 0x11 /* Disable Receiver */
/* Interrupt Enable Register (R/W) */
#define IER_DSR 0x80 /* Enable interrupt on DSR change */
#define IER_CD 0x40 /* Enable interrupt on CD change */
#define IER_CTS 0x20 /* Enable interrupt on CTS change */
#define IER_RXD 0x10 /* Enable interrupt on Receive Data */
#define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
#define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
#define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
#define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
/* Channel Option Register 1 (R/W) */
#define COR1_ODDP 0x80 /* Odd Parity */
#define COR1_PARMODE 0x60 /* Parity Mode mask */
#define COR1_NOPAR 0x00 /* No Parity */
#define COR1_FORCEPAR 0x20 /* Force Parity */
#define COR1_NORMPAR 0x40 /* Normal Parity */
#define COR1_IGNORE 0x10 /* Ignore Parity on RX */
#define COR1_STOPBITS 0x0c /* Number of Stop Bits */
#define COR1_1SB 0x00 /* 1 Stop Bit */
#define COR1_15SB 0x04 /* 1.5 Stop Bits */
#define COR1_2SB 0x08 /* 2 Stop Bits */
#define COR1_CHARLEN 0x03 /* Character Length */
#define COR1_5BITS 0x00 /* 5 bits */
#define COR1_6BITS 0x01 /* 6 bits */
#define COR1_7BITS 0x02 /* 7 bits */
#define COR1_8BITS 0x03 /* 8 bits */
/* Channel Option Register 2 (R/W) */
#define COR2_IXM 0x80 /* Implied XON mode */
#define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
#define COR2_LLM 0x10 /* Local Loopback Mode */
#define COR2_RLM 0x08 /* Remote Loopback Mode */
#define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
#define COR2_CTSAE 0x02 /* CTS Automatic Enable */
#define COR2_DSRAE 0x01 /* DSR Automatic Enable */
/* Channel Option Register 3 (R/W) */
#define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
#define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
#define COR3_SCDE 0x10 /* Special Character Detection Enable */
#define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
/* Channel Control Status Register (R/O) */
#define CCSR_RXEN 0x80 /* Receiver Enabled */
#define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
#define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
#define CCSR_TXEN 0x08 /* Transmitter Enabled */
#define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
#define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
/* Modem Change Option Register 1 (R/W) */
#define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
#define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
#define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
#define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
#define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
/* Modem Change Option Register 2 (R/W) */
#define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
#define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
#define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
/* Modem Change Register (R/W) */
#define MCR_DSRCHG 0x80 /* DSR Changed */
#define MCR_CDCHG 0x40 /* CD Changed */
#define MCR_CTSCHG 0x20 /* CTS Changed */
/* Modem Signal Value Register (R/W) */
#define MSVR_DSR 0x80 /* Current state of DSR input */
#define MSVR_CD 0x40 /* Current state of CD input */
#define MSVR_CTS 0x20 /* Current state of CTS input */
#define MSVR_DTR 0x02 /* Current state of DTR output */
#define MSVR_RTS 0x01 /* Current state of RTS output */
/* Escape characters */
#define CD186x_C_ESC 0x00 /* Escape character */
#define CD186x_C_SBRK 0x81 /* Start sending BREAK */
#define CD186x_C_DELAY 0x82 /* Delay output */
#define CD186x_C_EBRK 0x83 /* Stop sending BREAK */
#define SRSR_RREQint 0x10 /* This chip wants "rec" serviced */
#define SRSR_TREQint 0x04 /* This chip wants "transmit" serviced */
#define SRSR_MREQint 0x01 /* This chip wants "mdm change" serviced */
#define SRCR_PKGTYPE 0x80
#define SRCR_REGACKEN 0x40
#define SRCR_DAISYEN 0x20
#define SRCR_GLOBPRI 0x10
#define SRCR_UNFAIR 0x08
#define SRCR_AUTOPRI 0x02
#define SRCR_PRISEL 0x01
drivers/staging/tty/digi1.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
/* Definitions for DigiBoard ditty(1) command. */
#if !defined(TIOCMODG)
#define TIOCMODG (('d'<<8) | 250) /* get modem ctrl state */
#define TIOCMODS (('d'<<8) | 251) /* set modem ctrl state */
#endif
#if !defined(TIOCMSET)
#define TIOCMSET (('d'<<8) | 252) /* set modem ctrl state */
#define TIOCMGET (('d'<<8) | 253) /* set modem ctrl state */
#endif
#if !defined(TIOCMBIC)
#define TIOCMBIC (('d'<<8) | 254) /* set modem ctrl state */
#define TIOCMBIS (('d'<<8) | 255) /* set modem ctrl state */
#endif
#if !defined(TIOCSDTR)
#define TIOCSDTR (('e'<<8) | 0) /* set DTR */
#define TIOCCDTR (('e'<<8) | 1) /* clear DTR */
#endif
/************************************************************************
* Ioctl command arguments for DIGI parameters.
************************************************************************/
#define DIGI_GETA (('e'<<8) | 94) /* Read params */
#define DIGI_SETA (('e'<<8) | 95) /* Set params */
#define DIGI_SETAW (('e'<<8) | 96) /* Drain & set params */
#define DIGI_SETAF (('e'<<8) | 97) /* Drain, flush & set params */
#define DIGI_GETFLOW (('e'<<8) | 99) /* Get startc/stopc flow */
/* control characters */
#define DIGI_SETFLOW (('e'<<8) | 100) /* Set startc/stopc flow */
/* control characters */
#define DIGI_GETAFLOW (('e'<<8) | 101) /* Get Aux. startc/stopc */
/* flow control chars */
#define DIGI_SETAFLOW (('e'<<8) | 102) /* Set Aux. startc/stopc */
/* flow control chars */
#define DIGI_GETINFO (('e'<<8) | 103) /* Fill in digi_info */
#define DIGI_POLLER (('e'<<8) | 104) /* Turn on/off poller */
#define DIGI_INIT (('e'<<8) | 105) /* Allow things to run. */
struct digiflow_struct
{
unsigned char startc; /* flow cntl start char */
unsigned char stopc; /* flow cntl stop char */
};
typedef struct digiflow_struct digiflow_t;
/************************************************************************
* Values for digi_flags
************************************************************************/
#define DIGI_IXON 0x0001 /* Handle IXON in the FEP */
#define DIGI_FAST 0x0002 /* Fast baud rates */
#define RTSPACE 0x0004 /* RTS input flow control */
#define CTSPACE 0x0008 /* CTS output flow control */
#define DSRPACE 0x0010 /* DSR output flow control */
#define DCDPACE 0x0020 /* DCD output flow control */
#define DTRPACE 0x0040 /* DTR input flow control */
#define DIGI_FORCEDCD 0x0100 /* Force carrier */
#define DIGI_ALTPIN 0x0200 /* Alternate RJ-45 pin config */
#define DIGI_AIXON 0x0400 /* Aux flow control in fep */
/************************************************************************
* Values for digiDload
************************************************************************/
#define NORMAL 0
#define PCI_CTL 1
#define SIZE8 0
#define SIZE16 1
#define SIZE32 2
/************************************************************************
* Structure used with ioctl commands for DIGI parameters.
************************************************************************/
struct digi_struct
{
unsigned short digi_flags; /* Flags (see above) */
};
typedef struct digi_struct digi_t;
struct digi_info
{
unsigned long board; /* Which board is this ? */
unsigned char status; /* Alive or dead */
unsigned char type; /* see epca.h */
unsigned char subtype; /* For future XEM, XR, etc ... */
unsigned short numports; /* Number of ports configured */
unsigned char *port; /* I/O Address */
unsigned char *membase; /* DPR Address */
unsigned char *version; /* For future ... */
unsigned short windowData; /* For future ... */
} ;
drivers/staging/tty/digiFep1.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
#define CSTART 0x400L
#define CMAX 0x800L
#define ISTART 0x800L
#define IMAX 0xC00L
#define CIN 0xD10L
#define GLOBAL 0xD10L
#define EIN 0xD18L
#define FEPSTAT 0xD20L
#define CHANSTRUCT 0x1000L
#define RXTXBUF 0x4000L
struct global_data
{
u16 cin;
u16 cout;
u16 cstart;
u16 cmax;
u16 ein;
u16 eout;
u16 istart;
u16 imax;
};
struct board_chan
{
u32 filler1;
u32 filler2;
u16 tseg;
u16 tin;
u16 tout;
u16 tmax;
u16 rseg;
u16 rin;
u16 rout;
u16 rmax;
u16 tlow;
u16 rlow;
u16 rhigh;
u16 incr;
u16 etime;
u16 edelay;
unchar *dev;
u16 iflag;
u16 oflag;
u16 cflag;
u16 gmask;
u16 col;
u16 delay;
u16 imask;
u16 tflush;
u32 filler3;
u32 filler4;
u32 filler5;
u32 filler6;
u8 num;
u8 ract;
u8 bstat;
u8 tbusy;
u8 iempty;
u8 ilow;
u8 idata;
u8 eflag;
u8 tflag;
u8 rflag;
u8 xmask;
u8 xval;
u8 mstat;
u8 mchange;
u8 mint;
u8 lstat;
u8 mtran;
u8 orun;
u8 startca;
u8 stopca;
u8 startc;
u8 stopc;
u8 vnext;
u8 hflow;
u8 fillc;
u8 ochar;
u8 omask;
u8 filler7;
u8 filler8[28];
};
#define SRXLWATER 0xE0
#define SRXHWATER 0xE1
#define STOUT 0xE2
#define PAUSETX 0xE3
#define RESUMETX 0xE4
#define SAUXONOFFC 0xE6
#define SENDBREAK 0xE8
#define SETMODEM 0xE9
#define SETIFLAGS 0xEA
#define SONOFFC 0xEB
#define STXLWATER 0xEC
#define PAUSERX 0xEE
#define RESUMERX 0xEF
#define SETBUFFER 0xF2
#define SETCOOKED 0xF3
#define SETHFLOW 0xF4
#define SETCTRLFLAGS 0xF5
#define SETVNEXT 0xF6
#define BREAK_IND 0x01
#define LOWTX_IND 0x02
#define EMPTYTX_IND 0x04
#define DATA_IND 0x08
#define MODEMCHG_IND 0x20
#define FEP_HUPCL 0002000
#if 0
#define RTS 0x02
#define CD 0x08
#define DSR 0x10
#define CTS 0x20
#define RI 0x40
#define DTR 0x80
#endif
drivers/staging/tty/digiPCI.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
/*************************************************************************
* Defines and structure definitions for PCI BIOS Interface
*************************************************************************/
#define PCIMAX 32 /* maximum number of PCI boards */
#define PCI_VENDOR_DIGI 0x114F
#define PCI_DEVICE_EPC 0x0002
#define PCI_DEVICE_RIGHTSWITCH 0x0003 /* For testing */
#define PCI_DEVICE_XEM 0x0004
#define PCI_DEVICE_XR 0x0005
#define PCI_DEVICE_CX 0x0006
#define PCI_DEVICE_XRJ 0x0009 /* Jupiter boards with */
#define PCI_DEVICE_EPCJ 0x000a /* PLX 9060 chip for PCI */
/*
* On the PCI boards, there is no IO space allocated
* The I/O registers will be in the first 3 bytes of the
* upper 2MB of the 4MB memory space. The board memory
* will be mapped into the low 2MB of the 4MB memory space
*/
/* Potential location of PCI Bios from E0000 to FFFFF*/
#define PCI_BIOS_SIZE 0x00020000
/* Size of Memory and I/O for PCI (4MB) */
#define PCI_RAM_SIZE 0x00400000
/* Size of Memory (2MB) */
#define PCI_MEM_SIZE 0x00200000
/* Offset of I/0 in Memory (2MB) */
#define PCI_IO_OFFSET 0x00200000
#define MEMOUTB(basemem, pnum, setmemval) *(caddr_t)((basemem) + ( PCI_IO_OFFSET | pnum << 4 | pnum )) = (setmemval)
#define MEMINB(basemem, pnum) *(caddr_t)((basemem) + (PCI_IO_OFFSET | pnum << 4 | pnum )) /* for PCI I/O */
drivers/staging/tty/epca.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/epca.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
#define XEMPORTS 0xC02
#define XEPORTS 0xC22
#define MAX_ALLOC 0x100
#define MAXBOARDS 12
#define FEPCODESEG 0x0200L
#define FEPCODE 0x2000L
#define BIOSCODE 0xf800L
#define MISCGLOBAL 0x0C00L
#define NPORT 0x0C22L
#define MBOX 0x0C40L
#define PORTBASE 0x0C90L
/* Begin code defines used for epca_setup */
#define INVALID_BOARD_TYPE 0x1
#define INVALID_NUM_PORTS 0x2
#define INVALID_MEM_BASE 0x4
#define INVALID_PORT_BASE 0x8
#define INVALID_BOARD_STATUS 0x10
#define INVALID_ALTPIN 0x20
/* End code defines used for epca_setup */
#define FEPCLR 0x00
#define FEPMEM 0x02
#define FEPRST 0x04
#define FEPINT 0x08
#define FEPMASK 0x0e
#define FEPWIN 0x80
#define PCXE 0
#define PCXEVE 1
#define PCXEM 2
#define EISAXEM 3
#define PC64XE 4
#define PCXI 5
#define PCIXEM 7
#define PCICX 8
#define PCIXR 9
#define PCIXRJ 10
#define EPCA_NUM_TYPES 6
static char *board_desc[] =
{
"PC/Xe",
"PC/Xeve",
"PC/Xem",
"EISA/Xem",
"PC/64Xe",
"PC/Xi",
"unknown",
"PCI/Xem",
"PCI/CX",
"PCI/Xr",
"PCI/Xrj",
};
#define STARTC 021
#define STOPC 023
#define IAIXON 0x2000
#define TXSTOPPED 0x1
#define LOWWAIT 0x2
#define EMPTYWAIT 0x4
#define RXSTOPPED 0x8
#define TXBUSY 0x10
#define DISABLED 0
#define ENABLED 1
#define OFF 0
#define ON 1
#define FEPTIMEOUT 200000
#define SERIAL_TYPE_INFO 3
#define EPCA_EVENT_HANGUP 1
#define EPCA_MAGIC 0x5c6df104L
struct channel
{
long magic;
struct tty_port port;
unsigned char boardnum;
unsigned char channelnum;
unsigned char omodem; /* FEP output modem status */
unsigned char imodem; /* FEP input modem status */
unsigned char modemfake; /* Modem values to be forced */
unsigned char modem; /* Force values */
unsigned char hflow;
unsigned char dsr;
unsigned char dcd;
unsigned char m_rts ; /* The bits used in whatever FEP */
unsigned char m_dcd ; /* is indiginous to this board to */
unsigned char m_dsr ; /* represent each of the physical */
unsigned char m_cts ; /* handshake lines */
unsigned char m_ri ;
unsigned char m_dtr ;
unsigned char stopc;
unsigned char startc;
unsigned char stopca;
unsigned char startca;
unsigned char fepstopc;
unsigned char fepstartc;
unsigned char fepstopca;
unsigned char fepstartca;
unsigned char txwin;
unsigned char rxwin;
unsigned short fepiflag;
unsigned short fepcflag;
unsigned short fepoflag;
unsigned short txbufhead;
unsigned short txbufsize;
unsigned short rxbufhead;
unsigned short rxbufsize;
int close_delay;
unsigned long event;
uint dev;
unsigned long statusflags;
unsigned long c_iflag;
unsigned long c_cflag;
unsigned long c_lflag;
unsigned long c_oflag;
unsigned char __iomem *txptr;
unsigned char __iomem *rxptr;
struct board_info *board;
struct board_chan __iomem *brdchan;
struct digi_struct digiext;
struct work_struct tqueue;
struct global_data __iomem *mailbox;
};
struct board_info
{
unsigned char status;
unsigned char type;
unsigned char altpin;
unsigned short numports;
unsigned long port;
unsigned long membase;
void __iomem *re_map_port;
void __iomem *re_map_membase;
unsigned long memory_seg;
void ( * memwinon ) (struct board_info *, unsigned int) ;
void ( * memwinoff ) (struct board_info *, unsigned int) ;
void ( * globalwinon ) (struct channel *) ;
void ( * txwinon ) (struct channel *) ;
void ( * rxwinon ) (struct channel *) ;
void ( * memoff ) (struct channel *) ;
void ( * assertgwinon ) (struct channel *) ;
void ( * assertmemoff ) (struct channel *) ;
unsigned char poller_inhibited ;
};
drivers/staging/tty/epcaconfig.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
#define NUMCARDS 0
#define NBDEVS 0
struct board_info static_boards[NUMCARDS]={
};
/* DO NOT HAND EDIT THIS FILE! */
drivers/staging/tty/ip2/Makefile 已删除 100644 → 0
浏览文件 @ bb2a97e9
#
# Makefile for the Computone IntelliPort Plus Driver
#
obj-$(CONFIG_COMPUTONE) += ip2.o
ip2-y := ip2main.o
drivers/staging/tty/ip2/i2cmd.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Definition table for In-line and Bypass commands. Applicable
* only when the standard loadware is active. (This is included
* source code, not a separate compilation module.)
*
*******************************************************************************/
//------------------------------------------------------------------------------
//
// Revision History:
//
// 10 October 1991 MAG First Draft
// 7 November 1991 MAG Reflects additional commands.
// 24 February 1992 MAG Additional commands for 1.4.x loadware
// 11 March 1992 MAG Additional commands
// 30 March 1992 MAG Additional command: CMD_DSS_NOW
// 18 May 1992 MAG Discovered commands 39 & 40 must be at the end of a
// packet: affects implementation.
//------------------------------------------------------------------------------
//************
//* Includes *
//************
#include "i2cmd.h" /* To get some bit-defines */
//------------------------------------------------------------------------------
// Here is the table of global arrays which represent each type of command
// supported in the IntelliPort standard loadware. See also i2cmd.h
// for a more complete explanation of what is going on.
//------------------------------------------------------------------------------
// Here are the various globals: note that the names are not used except through
// the macros defined in i2cmd.h. Also note that although they are character
// arrays here (for extendability) they are cast to structure pointers in the
// i2cmd.h macros. See i2cmd.h for flags definitions.
// Length Flags Command
static UCHAR ct02[] = { 1, BTH, 0x02 }; // DTR UP
static UCHAR ct03[] = { 1, BTH, 0x03 }; // DTR DN
static UCHAR ct04[] = { 1, BTH, 0x04 }; // RTS UP
static UCHAR ct05[] = { 1, BTH, 0x05 }; // RTS DN
static UCHAR ct06[] = { 1, BYP, 0x06 }; // START FL
static UCHAR ct07[] = { 2, BTH, 0x07,0 }; // BAUD
static UCHAR ct08[] = { 2, BTH, 0x08,0 }; // BITS
static UCHAR ct09[] = { 2, BTH, 0x09,0 }; // STOP
static UCHAR ct10[] = { 2, BTH, 0x0A,0 }; // PARITY
static UCHAR ct11[] = { 2, BTH, 0x0B,0 }; // XON
static UCHAR ct12[] = { 2, BTH, 0x0C,0 }; // XOFF
static UCHAR ct13[] = { 1, BTH, 0x0D }; // STOP FL
static UCHAR ct14[] = { 1, BYP|VIP, 0x0E }; // ACK HOTK
//static UCHAR ct15[]={ 2, BTH|VIP, 0x0F,0 }; // IRQ SET
static UCHAR ct16[] = { 2, INL, 0x10,0 }; // IXONOPTS
static UCHAR ct17[] = { 2, INL, 0x11,0 }; // OXONOPTS
static UCHAR ct18[] = { 1, INL, 0x12 }; // CTSENAB
static UCHAR ct19[] = { 1, BTH, 0x13 }; // CTSDSAB
static UCHAR ct20[] = { 1, INL, 0x14 }; // DCDENAB
static UCHAR ct21[] = { 1, BTH, 0x15 }; // DCDDSAB
static UCHAR ct22[] = { 1, BTH, 0x16 }; // DSRENAB
static UCHAR ct23[] = { 1, BTH, 0x17 }; // DSRDSAB
static UCHAR ct24[] = { 1, BTH, 0x18 }; // RIENAB
static UCHAR ct25[] = { 1, BTH, 0x19 }; // RIDSAB
static UCHAR ct26[] = { 2, BTH, 0x1A,0 }; // BRKENAB
static UCHAR ct27[] = { 1, BTH, 0x1B }; // BRKDSAB
//static UCHAR ct28[]={ 2, BTH, 0x1C,0 }; // MAXBLOKSIZE
//static UCHAR ct29[]={ 2, 0, 0x1D,0 }; // reserved
static UCHAR ct30[] = { 1, INL, 0x1E }; // CTSFLOWENAB
static UCHAR ct31[] = { 1, INL, 0x1F }; // CTSFLOWDSAB
static UCHAR ct32[] = { 1, INL, 0x20 }; // RTSFLOWENAB
static UCHAR ct33[] = { 1, INL, 0x21 }; // RTSFLOWDSAB
static UCHAR ct34[] = { 2, BTH, 0x22,0 }; // ISTRIPMODE
static UCHAR ct35[] = { 2, BTH|END, 0x23,0 }; // SENDBREAK
static UCHAR ct36[] = { 2, BTH, 0x24,0 }; // SETERRMODE
//static UCHAR ct36a[]={ 3, INL, 0x24,0,0 }; // SET_REPLACE
// The following is listed for completeness, but should never be sent directly
// by user-level code. It is sent only by library routines in response to data
// movement.
//static UCHAR ct37[]={ 5, BYP|VIP, 0x25,0,0,0,0 }; // FLOW PACKET
// Back to normal
//static UCHAR ct38[] = {11, BTH|VAR, 0x26,0,0,0,0,0,0,0,0,0,0 }; // DEF KEY SEQ
//static UCHAR ct39[]={ 3, BTH|END, 0x27,0,0 }; // OPOSTON
//static UCHAR ct40[]={ 1, BTH|END, 0x28 }; // OPOSTOFF
static UCHAR ct41[] = { 1, BYP, 0x29 }; // RESUME
//static UCHAR ct42[]={ 2, BTH, 0x2A,0 }; // TXBAUD
//static UCHAR ct43[]={ 2, BTH, 0x2B,0 }; // RXBAUD
//static UCHAR ct44[]={ 2, BTH, 0x2C,0 }; // MS PING
//static UCHAR ct45[]={ 1, BTH, 0x2D }; // HOTENAB
//static UCHAR ct46[]={ 1, BTH, 0x2E }; // HOTDSAB
//static UCHAR ct47[]={ 7, BTH, 0x2F,0,0,0,0,0,0 }; // UNIX FLAGS
//static UCHAR ct48[]={ 1, BTH, 0x30 }; // DSRFLOWENAB
//static UCHAR ct49[]={ 1, BTH, 0x31 }; // DSRFLOWDSAB
//static UCHAR ct50[]={ 1, BTH, 0x32 }; // DTRFLOWENAB
//static UCHAR ct51[]={ 1, BTH, 0x33 }; // DTRFLOWDSAB
//static UCHAR ct52[]={ 1, BTH, 0x34 }; // BAUDTABRESET
//static UCHAR ct53[] = { 3, BTH, 0x35,0,0 }; // BAUDREMAP
static UCHAR ct54[] = { 3, BTH, 0x36,0,0 }; // CUSTOMBAUD1
static UCHAR ct55[] = { 3, BTH, 0x37,0,0 }; // CUSTOMBAUD2
static UCHAR ct56[] = { 2, BTH|END, 0x38,0 }; // PAUSE
static UCHAR ct57[] = { 1, BYP, 0x39 }; // SUSPEND
static UCHAR ct58[] = { 1, BYP, 0x3A }; // UNSUSPEND
static UCHAR ct59[] = { 2, BTH, 0x3B,0 }; // PARITYCHK
static UCHAR ct60[] = { 1, INL|VIP, 0x3C }; // BOOKMARKREQ
//static UCHAR ct61[]={ 2, BTH, 0x3D,0 }; // INTERNALLOOP
//static UCHAR ct62[]={ 2, BTH, 0x3E,0 }; // HOTKTIMEOUT
static UCHAR ct63[] = { 2, INL, 0x3F,0 }; // SETTXON
static UCHAR ct64[] = { 2, INL, 0x40,0 }; // SETTXOFF
//static UCHAR ct65[]={ 2, BTH, 0x41,0 }; // SETAUTORTS
//static UCHAR ct66[]={ 2, BTH, 0x42,0 }; // SETHIGHWAT
//static UCHAR ct67[]={ 2, BYP, 0x43,0 }; // STARTSELFL
//static UCHAR ct68[]={ 2, INL, 0x44,0 }; // ENDSELFL
//static UCHAR ct69[]={ 1, BYP, 0x45 }; // HWFLOW_OFF
//static UCHAR ct70[]={ 1, BTH, 0x46 }; // ODSRFL_ENAB
//static UCHAR ct71[]={ 1, BTH, 0x47 }; // ODSRFL_DSAB
//static UCHAR ct72[]={ 1, BTH, 0x48 }; // ODCDFL_ENAB
//static UCHAR ct73[]={ 1, BTH, 0x49 }; // ODCDFL_DSAB
//static UCHAR ct74[]={ 2, BTH, 0x4A,0 }; // LOADLEVEL
//static UCHAR ct75[]={ 2, BTH, 0x4B,0 }; // STATDATA
//static UCHAR ct76[]={ 1, BYP, 0x4C }; // BREAK_ON
//static UCHAR ct77[]={ 1, BYP, 0x4D }; // BREAK_OFF
//static UCHAR ct78[]={ 1, BYP, 0x4E }; // GETFC
static UCHAR ct79[] = { 2, BYP, 0x4F,0 }; // XMIT_NOW
//static UCHAR ct80[]={ 4, BTH, 0x50,0,0,0 }; // DIVISOR_LATCH
//static UCHAR ct81[]={ 1, BYP, 0x51 }; // GET_STATUS
//static UCHAR ct82[]={ 1, BYP, 0x52 }; // GET_TXCNT
//static UCHAR ct83[]={ 1, BYP, 0x53 }; // GET_RXCNT
//static UCHAR ct84[]={ 1, BYP, 0x54 }; // GET_BOXIDS
//static UCHAR ct85[]={10, BYP, 0x55,0,0,0,0,0,0,0,0,0 }; // ENAB_MULT
//static UCHAR ct86[]={ 2, BTH, 0x56,0 }; // RCV_ENABLE
static UCHAR ct87[] = { 1, BYP, 0x57 }; // HW_TEST
//static UCHAR ct88[]={ 3, BTH, 0x58,0,0 }; // RCV_THRESHOLD
//static UCHAR ct90[]={ 3, BYP, 0x5A,0,0 }; // Set SILO
//static UCHAR ct91[]={ 2, BYP, 0x5B,0 }; // timed break
// Some composite commands as well
//static UCHAR cc01[]={ 2, BTH, 0x02,0x04 }; // DTR & RTS UP
//static UCHAR cc02[]={ 2, BTH, 0x03,0x05 }; // DTR & RTS DN
//********
//* Code *
//********
//******************************************************************************
// Function: i2cmdUnixFlags(iflag, cflag, lflag)
// Parameters: Unix tty flags
//
// Returns: Pointer to command structure
//
// Description:
//
// This routine sets the parameters of command 47 and returns a pointer to the
// appropriate structure.
//******************************************************************************
#if 0
cmdSyntaxPtr
i2cmdUnixFlags(unsigned short iflag,unsigned short cflag,unsigned short lflag)
{
cmdSyntaxPtr pCM = (cmdSyntaxPtr) ct47;
pCM->cmd[1] = (unsigned char) iflag;
pCM->cmd[2] = (unsigned char) (iflag >> 8);
pCM->cmd[3] = (unsigned char) cflag;
pCM->cmd[4] = (unsigned char) (cflag >> 8);
pCM->cmd[5] = (unsigned char) lflag;
pCM->cmd[6] = (unsigned char) (lflag >> 8);
return pCM;
}
#endif /* 0 */
//******************************************************************************
// Function: i2cmdBaudDef(which, rate)
// Parameters: ?
//
// Returns: Pointer to command structure
//
// Description:
//
// This routine sets the parameters of commands 54 or 55 (according to the
// argument which), and returns a pointer to the appropriate structure.
//******************************************************************************
static cmdSyntaxPtr
i2cmdBaudDef(int which, unsigned short rate)
{
cmdSyntaxPtr pCM;
switch(which)
{
case 1:
pCM = (cmdSyntaxPtr) ct54;
break;
default:
case 2:
pCM = (cmdSyntaxPtr) ct55;
break;
}
pCM->cmd[1] = (unsigned char) rate;
pCM->cmd[2] = (unsigned char) (rate >> 8);
return pCM;
}
drivers/staging/tty/ip2/i2cmd.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/i2ellis.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/i2ellis.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/i2hw.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/i2lib.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/i2lib.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Header file for high level library functions
*
*******************************************************************************/
#ifndef I2LIB_H
#define I2LIB_H 1
//------------------------------------------------------------------------------
// I2LIB.H
//
// IntelliPort-II and IntelliPort-IIEX
//
// Defines, structure definitions, and external declarations for i2lib.c
//------------------------------------------------------------------------------
//--------------------------------------
// Mandatory Includes:
//--------------------------------------
#include "ip2types.h"
#include "i2ellis.h"
#include "i2pack.h"
#include "i2cmd.h"
#include <linux/workqueue.h>
//------------------------------------------------------------------------------
// i2ChanStr -- Channel Structure:
// Used to track per-channel information for the library routines using standard
// loadware. Note also, a pointer to an array of these structures is patched
// into the i2eBordStr (see i2ellis.h)
//------------------------------------------------------------------------------
//
// If we make some limits on the maximum block sizes, we can avoid dealing with
// buffer wrap. The wrapping of the buffer is based on where the start of the
// packet is. Then there is always room for the packet contiguously.
//
// Maximum total length of an outgoing data or in-line command block. The limit
// of 36 on data is quite arbitrary and based more on DOS memory limitations
// than the board interface. However, for commands, the maximum packet length is
// MAX_CMD_PACK_SIZE, because the field size for the count is only a few bits
// (see I2PACK.H) in such packets. For data packets, the count field size is not
// the limiting factor. As of this writing, MAX_OBUF_BLOCK < MAX_CMD_PACK_SIZE,
// but be careful if wanting to modify either.
//
#define MAX_OBUF_BLOCK 36
// Another note on maximum block sizes: we are buffering packets here. Data is
// put into the buffer (if there is room) regardless of the credits from the
// board. The board sends new credits whenever it has removed from his buffers a
// number of characters equal to 80% of total buffer size. (Of course, the total
// buffer size is what is reported when the very first set of flow control
// status packets are received from the board. Therefore, to be robust, you must
// always fill the board to at least 80% of the current credit limit, else you
// might not give it enough to trigger a new report. These conditions are
// obtained here so long as the maximum output block size is less than 20% the
// size of the board's output buffers. This is true at present by "coincidence"
// or "infernal knowledge": the board's output buffers are at least 700 bytes
// long (20% = 140 bytes, at least). The 80% figure is "official", so the safest
// strategy might be to trap the first flow control report and guarantee that
// the effective maxObufBlock is the minimum of MAX_OBUF_BLOCK and 20% of first
// reported buffer credit.
//
#define MAX_CBUF_BLOCK 6 // Maximum total length of a bypass command block
#define IBUF_SIZE 512 // character capacity of input buffer per channel
#define OBUF_SIZE 1024// character capacity of output buffer per channel
#define CBUF_SIZE 10 // character capacity of output bypass buffer
typedef struct _i2ChanStr
{
// First, back-pointers so that given a pointer to this structure, you can
// determine the correct board and channel number to reference, (say, when
// issuing commands, etc. (Note, channel number is in infl.hd.i2sChannel.)
int port_index; // Index of port in channel structure array attached
// to board structure.
PTTY pTTY; // Pointer to tty structure for port (OS specific)
USHORT validity; // Indicates whether the given channel has been
// initialized, really exists (or is a missing
// channel, e.g. channel 9 on an 8-port box.)
i2eBordStrPtr pMyBord; // Back-pointer to this channel's board structure
int wopen; // waiting fer carrier
int throttled; // Set if upper layer can take no data
int flags; // Defined in tty.h
PWAITQ open_wait; // Pointer for OS sleep function.
PWAITQ close_wait; // Pointer for OS sleep function.
PWAITQ delta_msr_wait;// Pointer for OS sleep function.
PWAITQ dss_now_wait; // Pointer for OS sleep function.
struct timer_list BookmarkTimer; // Used by i2DrainOutput
wait_queue_head_t pBookmarkWait; // Used by i2DrainOutput
int BaudBase;
int BaudDivisor;
USHORT ClosingDelay;
USHORT ClosingWaitTime;
volatile
flowIn infl; // This structure is initialized as a completely
// formed flow-control command packet, and as such
// has the channel number, also the capacity and
// "as-of" data needed continuously.
USHORT sinceLastFlow; // Counts the number of characters read from input
// buffers, since the last time flow control info
// was sent.
USHORT whenSendFlow; // Determines when new flow control is to be sent to
// the board. Note unlike earlier manifestations of
// the driver, these packets can be sent from
// in-place.
USHORT channelNeeds; // Bit map of important things which must be done
// for this channel. (See bits below )
volatile
flowStat outfl; // Same type of structure is used to hold current
// flow control information used to control our
// output. "asof" is kept updated as data is sent,
// and "room" never goes to zero.
// The incoming ring buffer
// Unlike the outgoing buffers, this holds raw data, not packets. The two
// extra bytes are used to hold the byte-padding when there is room for an
// odd number of bytes before we must wrap.
//
UCHAR Ibuf[IBUF_SIZE + 2];
volatile
USHORT Ibuf_stuff; // Stuffing index
volatile
USHORT Ibuf_strip; // Stripping index
// The outgoing ring-buffer: Holds Data and command packets. N.B., even
// though these are in the channel structure, the channel is also written
// here, the easier to send it to the fifo when ready. HOWEVER, individual
// packets here are NOT padded to even length: the routines for writing
// blocks to the fifo will pad to even byte counts.
//
UCHAR Obuf[OBUF_SIZE+MAX_OBUF_BLOCK+4];
volatile
USHORT Obuf_stuff; // Stuffing index
volatile
USHORT Obuf_strip; // Stripping index
int Obuf_char_count;
// The outgoing bypass-command buffer. Unlike earlier manifestations, the
// flow control packets are sent directly from the structures. As above, the
// channel number is included in the packet, but they are NOT padded to even
// size.
//
UCHAR Cbuf[CBUF_SIZE+MAX_CBUF_BLOCK+2];
volatile
USHORT Cbuf_stuff; // Stuffing index
volatile
USHORT Cbuf_strip; // Stripping index
// The temporary buffer for the Linux tty driver PutChar entry.
//
UCHAR Pbuf[MAX_OBUF_BLOCK - sizeof (i2DataHeader)];
volatile
USHORT Pbuf_stuff; // Stuffing index
// The state of incoming data-set signals
//
USHORT dataSetIn; // Bit-mapped according to below. Also indicates
// whether a break has been detected since last
// inquiry.
// The state of outcoming data-set signals (as far as we can tell!)
//
USHORT dataSetOut; // Bit-mapped according to below.
// Most recent hot-key identifier detected
//
USHORT hotKeyIn; // Hot key as sent by the board, HOT_CLEAR indicates
// no hot key detected since last examined.
// Counter of outstanding requests for bookmarks
//
short bookMarks; // Number of outstanding bookmark requests, (+ive
// whenever a bookmark request if queued up, -ive
// whenever a bookmark is received).
// Misc options
//
USHORT channelOptions; // See below
// To store various incoming special packets
//
debugStat channelStatus;
cntStat channelRcount;
cntStat channelTcount;
failStat channelFail;
// To store the last values for line characteristics we sent to the board.
//
int speed;
int flush_flags;
void (*trace)(unsigned short,unsigned char,unsigned char,unsigned long,...);
/*
* Kernel counters for the 4 input interrupts
*/
struct async_icount icount;
/*
* Task queues for processing input packets from the board.
*/
struct work_struct tqueue_input;
struct work_struct tqueue_status;
struct work_struct tqueue_hangup;
rwlock_t Ibuf_spinlock;
rwlock_t Obuf_spinlock;
rwlock_t Cbuf_spinlock;
rwlock_t Pbuf_spinlock;
} i2ChanStr, *i2ChanStrPtr;
//---------------------------------------------------
// Manifests and bit-maps for elements in i2ChanStr
//---------------------------------------------------
//
// flush flags
//
#define STARTFL_FLAG 1
#define STOPFL_FLAG 2
// validity
//
#define CHANNEL_MAGIC_BITS 0xff00
#define CHANNEL_MAGIC 0x5300 // (validity & CHANNEL_MAGIC_BITS) ==
// CHANNEL_MAGIC --> structure good
#define CHANNEL_SUPPORT 0x0001 // Indicates channel is supported, exists,
// and passed P.O.S.T.
// channelNeeds
//
#define NEED_FLOW 1 // Indicates flow control has been queued
#define NEED_INLINE 2 // Indicates inline commands or data queued
#define NEED_BYPASS 4 // Indicates bypass commands queued
#define NEED_CREDIT 8 // Indicates would be sending except has not sufficient
// credit. The data is still in the channel structure,
// but the channel is not enqueued in the board
// structure again until there is a credit received from
// the board.
// dataSetIn (Also the bits for i2GetStatus return value)
//
#define I2_DCD 1
#define I2_CTS 2
#define I2_DSR 4
#define I2_RI 8
// dataSetOut (Also the bits for i2GetStatus return value)
//
#define I2_DTR 1
#define I2_RTS 2
// i2GetStatus() can optionally clear these bits
//
#define I2_BRK 0x10 // A break was detected
#define I2_PAR 0x20 // A parity error was received
#define I2_FRA 0x40 // A framing error was received
#define I2_OVR 0x80 // An overrun error was received
// i2GetStatus() automatically clears these bits */
//
#define I2_DDCD 0x100 // DCD changed from its former value
#define I2_DCTS 0x200 // CTS changed from its former value
#define I2_DDSR 0x400 // DSR changed from its former value
#define I2_DRI 0x800 // RI changed from its former value
// hotKeyIn
//
#define HOT_CLEAR 0x1322 // Indicates that no hot-key has been detected
// channelOptions
//
#define CO_NBLOCK_WRITE 1 // Writes don't block waiting for buffer. (Default
// is, they do wait.)
// fcmodes
//
#define I2_OUTFLOW_CTS 0x0001
#define I2_INFLOW_RTS 0x0002
#define I2_INFLOW_DSR 0x0004
#define I2_INFLOW_DTR 0x0008
#define I2_OUTFLOW_DSR 0x0010
#define I2_OUTFLOW_DTR 0x0020
#define I2_OUTFLOW_XON 0x0040
#define I2_OUTFLOW_XANY 0x0080
#define I2_INFLOW_XON 0x0100
#define I2_CRTSCTS (I2_OUTFLOW_CTS|I2_INFLOW_RTS)
#define I2_IXANY_MODE (I2_OUTFLOW_XON|I2_OUTFLOW_XANY)
//-------------------------------------------
// Macros used from user level like functions
//-------------------------------------------
// Macros to set and clear channel options
//
#define i2SetOption(pCh, option) pCh->channelOptions |= option
#define i2ClrOption(pCh, option) pCh->channelOptions &= ~option
// Macro to set fatal-error trap
//
#define i2SetFatalTrap(pB, routine) pB->i2eFatalTrap = routine
//--------------------------------------------
// Declarations and prototypes for i2lib.c
//--------------------------------------------
//
static int i2InitChannels(i2eBordStrPtr, int, i2ChanStrPtr);
static int i2QueueCommands(int, i2ChanStrPtr, int, int, cmdSyntaxPtr,...);
static int i2GetStatus(i2ChanStrPtr, int);
static int i2Input(i2ChanStrPtr);
static int i2InputFlush(i2ChanStrPtr);
static int i2Output(i2ChanStrPtr, const char *, int);
static int i2OutputFree(i2ChanStrPtr);
static int i2ServiceBoard(i2eBordStrPtr);
static void i2DrainOutput(i2ChanStrPtr, int);
#ifdef IP2DEBUG_TRACE
void ip2trace(unsigned short,unsigned char,unsigned char,unsigned long,...);
#else
#define ip2trace(a,b,c,d...) do {} while (0)
#endif
// Argument to i2QueueCommands
//
#define C_IN_LINE 1
#define C_BYPASS 0
#endif // I2LIB_H
drivers/staging/tty/ip2/i2pack.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/ip2.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Driver constants for configuration and tuning
*
* NOTES:
*
*******************************************************************************/
#ifndef IP2_H
#define IP2_H
#include "ip2types.h"
#include "i2cmd.h"
/*************/
/* Constants */
/*************/
/* Device major numbers - since version 2.0.26. */
#define IP2_TTY_MAJOR 71
#define IP2_CALLOUT_MAJOR 72
#define IP2_IPL_MAJOR 73
/* Board configuration array.
* This array defines the hardware irq and address for up to IP2_MAX_BOARDS
* (4 supported per ip2_types.h) ISA board addresses and irqs MUST be specified,
* PCI and EISA boards are probed for and automagicly configed
* iff the addresses are set to 1 and 2 respectivily.
* 0x0100 - 0x03f0 == ISA
* 1 == PCI
* 2 == EISA
* 0 == (skip this board)
* This array defines the hardware addresses for them. Special
* addresses are EISA and PCI which go sniffing for boards.
* In a multiboard system the position in the array determines which port
* devices are assigned to each board:
* board 0 is assigned ttyF0.. to ttyF63,
* board 1 is assigned ttyF64 to ttyF127,
* board 2 is assigned ttyF128 to ttyF191,
* board 3 is assigned ttyF192 to ttyF255.
*
* In PCI and EISA bus systems each range is mapped to card in
* monotonically increasing slot number order, ISA position is as specified
* here.
* If the irqs are ALL set to 0,0,0,0 all boards operate in
* polled mode. For interrupt operation ISA boards require that the IRQ be
* specified, while PCI and EISA boards any nonzero entry
* will enable interrupts using the BIOS configured irq for the board.
* An invalid irq entry will default to polled mode for that card and print
* console warning.
* When the driver is loaded as a module these setting can be overridden on the
* modprobe command line or on an option line in /etc/modprobe.conf.
* If the driver is built-in the configuration must be
* set here for ISA cards and address set to 1 and 2 for PCI and EISA.
*
* Here is an example that shows most if not all possibe combinations:
*static ip2config_t ip2config =
*{
* {11,1,0,0}, // irqs
* { // Addresses
* 0x0308, // Board 0, ttyF0 - ttyF63// ISA card at io=0x308, irq=11
* 0x0001, // Board 1, ttyF64 - ttyF127//PCI card configured by BIOS
* 0x0000, // Board 2, ttyF128 - ttyF191// Slot skipped
* 0x0002 // Board 3, ttyF192 - ttyF255//EISA card configured by BIOS
* // but polled not irq driven
* }
*};
*/
/* this structure is zeroed out because the suggested method is to configure
* the driver as a module, set up the parameters with an options line in
* /etc/modprobe.conf and load with modprobe or kmod, the kernel
* module loader
*/
/* This structure is NOW always initialized when the driver is initialized.
* Compiled in defaults MUST be added to the io and irq arrays in
* ip2.c. Those values are configurable from insmod parameters in the
* case of modules or from command line parameters (ip2=io,irq) when
* compiled in.
*/
static ip2config_t ip2config =
{
{0,0,0,0}, // irqs
{ // Addresses
/* Do NOT set compile time defaults HERE! Use the arrays in
ip2.c! These WILL be overwritten! =mhw= */
0x0000, // Board 0, ttyF0 - ttyF63
0x0000, // Board 1, ttyF64 - ttyF127
0x0000, // Board 2, ttyF128 - ttyF191
0x0000 // Board 3, ttyF192 - ttyF255
}
};
#endif
drivers/staging/tty/ip2/ip2ioctl.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
/*******************************************************************************
*
* (c) 1998 by Computone Corporation
*
********************************************************************************
*
*
* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
* serial I/O controllers.
*
* DESCRIPTION: Driver constants for configuration and tuning
*
* NOTES:
*
*******************************************************************************/
#ifndef IP2IOCTL_H
#define IP2IOCTL_H
//*************
//* Constants *
//*************
// High baud rates (if not defined elsewhere.
#ifndef B153600
# define B153600 0010005
#endif
#ifndef B307200
# define B307200 0010006
#endif
#ifndef B921600
# define B921600 0010007
#endif
#endif
drivers/staging/tty/ip2/ip2main.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/ip2/ip2trace.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
//
union ip2breadcrumb
{
struct {
unsigned char port, cat, codes, label;
} __attribute__ ((packed)) hdr;
unsigned long value;
};
#define ITRC_NO_PORT 0xFF
#define CHANN (pCh->port_index)
#define ITRC_ERROR '!'
#define ITRC_INIT 'A'
#define ITRC_OPEN 'B'
#define ITRC_CLOSE 'C'
#define ITRC_DRAIN 'D'
#define ITRC_IOCTL 'E'
#define ITRC_FLUSH 'F'
#define ITRC_STATUS 'G'
#define ITRC_HANGUP 'H'
#define ITRC_INTR 'I'
#define ITRC_SFLOW 'J'
#define ITRC_SBCMD 'K'
#define ITRC_SICMD 'L'
#define ITRC_MODEM 'M'
#define ITRC_INPUT 'N'
#define ITRC_OUTPUT 'O'
#define ITRC_PUTC 'P'
#define ITRC_QUEUE 'Q'
#define ITRC_STFLW 'R'
#define ITRC_SFIFO 'S'
#define ITRC_VERIFY 'V'
#define ITRC_WRITE 'W'
#define ITRC_ENTER 0x00
#define ITRC_RETURN 0xFF
#define ITRC_QUEUE_ROOM 2
#define ITRC_QUEUE_CMD 6
drivers/staging/tty/ip2/ip2types.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/istallion.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/riscom8.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/riscom8.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/riscom8_reg.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/serial167.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/specialix.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/specialix_io8.h 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
drivers/staging/tty/stallion.c 已删除 100644 → 0
浏览文件 @ bb2a97e9
此差异已折叠。
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或