提交 503b0f1c 编写于 作者: B Ben Skeggs

drm/nouveau/fifo: separate object classes for dma channels

Future code will use the object class rather than chipset checks in order to
identify available channel features.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
上级 72a14827
......@@ -118,7 +118,10 @@ nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
switch (nv_mclass(parent)) {
case 0x006b:
case 0x006e:
case 0x176e:
case 0x406e:
ret = dmaeng->bind(dmaeng, *pobject, &dmaobj->base, &gpuobj);
nouveau_object_ref(NULL, pobject);
*pobject = nv_object(gpuobj);
......
......@@ -247,7 +247,7 @@ nv04_fifo_ofuncs = {
static struct nouveau_oclass
nv04_fifo_sclass[] = {
{ 0x006e, &nv04_fifo_ofuncs },
{ 0x006b, &nv04_fifo_ofuncs },
{}
};
......
......@@ -113,7 +113,7 @@ nv17_fifo_ofuncs = {
static struct nouveau_oclass
nv17_fifo_sclass[] = {
{ 0x006e, &nv17_fifo_ofuncs },
{ 0x176e, &nv17_fifo_ofuncs },
{}
};
......
......@@ -232,7 +232,7 @@ nv40_fifo_ofuncs = {
static struct nouveau_oclass
nv40_fifo_sclass[] = {
{ 0x006e, &nv40_fifo_ofuncs },
{ 0x406e, &nv40_fifo_ofuncs },
{}
};
......
......@@ -53,6 +53,7 @@ struct nv_dma_class {
/* 006b: NV03_CHANNEL_DMA
* 006e: NV10_CHANNEL_DMA
* 176e: NV17_CHANNEL_DMA
* 406e: NV40_CHANNEL_DMA
*/
......
......@@ -221,7 +221,7 @@ static int
nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli,
u32 parent, u32 handle, struct nouveau_channel **pchan)
{
static const u16 oclasses[] = { 0x006e, 0 };
static const u16 oclasses[] = { 0x406e, 0x176e, 0x006e, 0x006b, 0 };
const u16 *oclass = oclasses;
struct nv_channel_dma_class args;
struct nouveau_channel *chan;
......@@ -305,7 +305,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
}
/* initialise dma tracking parameters */
switch (nv_hclass(chan->object) & 0xffff) {
switch (nv_hclass(chan->object) & 0x00ff) {
case 0x006b:
case 0x006e:
chan->user_put = 0x40;
chan->user_get = 0x44;
......
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