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4c27bd33
cloud-kernel
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体验新版 GitCode,发现更多精彩内容 >>
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4c27bd33
编写于
2月 11, 2010
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nv50: more efficient clearing of gpu page table entries
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
66b6ebac
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
44 addition
and
24 deletion
+44
-24
drivers/gpu/drm/nouveau/nouveau_mem.c
drivers/gpu/drm/nouveau/nouveau_mem.c
+44
-24
未找到文件。
drivers/gpu/drm/nouveau/nouveau_mem.c
浏览文件 @
4c27bd33
...
@@ -291,31 +291,17 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
...
@@ -291,31 +291,17 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
pages
=
size
>>
16
;
pages
=
size
>>
16
;
dev_priv
->
engine
.
instmem
.
prepare_access
(
dev
,
true
);
dev_priv
->
engine
.
instmem
.
prepare_access
(
dev
,
true
);
if
(
flags
&
0x80000000
)
{
while
(
pages
--
)
{
while
(
pages
--
)
{
struct
nouveau_gpuobj
*
pt
=
dev_priv
->
vm_vram_pt
[
virt
>>
29
];
struct
nouveau_gpuobj
*
pt
=
unsigned
pte
=
((
virt
&
0x1fffffffULL
)
>>
16
)
<<
1
;
dev_priv
->
vm_vram_pt
[
virt
>>
29
]
;
unsigned
offset_h
=
upper_32_bits
(
phys
)
&
0xff
;
unsigned
pte
=
((
virt
&
0x1fffffffULL
)
>>
16
)
<<
1
;
unsigned
offset_l
=
lower_32_bits
(
phys
)
;
nv_wo32
(
dev
,
pt
,
pte
++
,
0x00000000
);
nv_wo32
(
dev
,
pt
,
pte
++
,
offset_l
|
1
);
nv_wo32
(
dev
,
pt
,
pte
++
,
0x00000000
);
nv_wo32
(
dev
,
pt
,
pte
++
,
offset_h
|
flags
);
virt
+=
(
1
<<
16
);
phys
+=
(
1
<<
16
);
}
virt
+=
(
1
<<
16
);
}
else
{
while
(
pages
--
)
{
struct
nouveau_gpuobj
*
pt
=
dev_priv
->
vm_vram_pt
[
virt
>>
29
];
unsigned
pte
=
((
virt
&
0x1fffffffULL
)
>>
16
)
<<
1
;
unsigned
offset_h
=
upper_32_bits
(
phys
)
&
0xff
;
unsigned
offset_l
=
lower_32_bits
(
phys
);
nv_wo32
(
dev
,
pt
,
pte
++
,
offset_l
|
1
);
nv_wo32
(
dev
,
pt
,
pte
++
,
offset_h
|
flags
);
phys
+=
(
1
<<
16
);
virt
+=
(
1
<<
16
);
}
}
}
dev_priv
->
engine
.
instmem
.
finish_access
(
dev
);
dev_priv
->
engine
.
instmem
.
finish_access
(
dev
);
...
@@ -339,7 +325,41 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
...
@@ -339,7 +325,41 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
void
void
nv50_mem_vm_unbind
(
struct
drm_device
*
dev
,
uint64_t
virt
,
uint32_t
size
)
nv50_mem_vm_unbind
(
struct
drm_device
*
dev
,
uint64_t
virt
,
uint32_t
size
)
{
{
nv50_mem_vm_bind_linear
(
dev
,
virt
,
size
,
0x80000000
,
0
);
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
struct
nouveau_gpuobj
*
pgt
;
unsigned
pages
,
pte
,
end
;
virt
-=
dev_priv
->
vm_vram_base
;
pages
=
(
size
>>
16
)
<<
1
;
dev_priv
->
engine
.
instmem
.
prepare_access
(
dev
,
true
);
while
(
pages
)
{
pgt
=
dev_priv
->
vm_vram_pt
[
virt
>>
29
];
pte
=
(
virt
&
0x1ffe0000ULL
)
>>
15
;
end
=
pte
+
pages
;
if
(
end
>
16384
)
end
=
16384
;
pages
-=
(
end
-
pte
);
virt
+=
(
end
-
pte
)
<<
15
;
while
(
pte
<
end
)
nv_wo32
(
dev
,
pgt
,
pte
++
,
0
);
}
dev_priv
->
engine
.
instmem
.
finish_access
(
dev
);
nv_wr32
(
dev
,
0x100c80
,
0x00050001
);
if
(
!
nv_wait
(
0x100c80
,
0x00000001
,
0x00000000
))
{
NV_ERROR
(
dev
,
"timeout: (0x100c80 & 1) == 0 (2)
\n
"
);
NV_ERROR
(
dev
,
"0x100c80 = 0x%08x
\n
"
,
nv_rd32
(
dev
,
0x100c80
));
return
;
}
nv_wr32
(
dev
,
0x100c80
,
0x00000001
);
if
(
!
nv_wait
(
0x100c80
,
0x00000001
,
0x00000000
))
{
NV_ERROR
(
dev
,
"timeout: (0x100c80 & 1) == 0 (2)
\n
"
);
NV_ERROR
(
dev
,
"0x100c80 = 0x%08x
\n
"
,
nv_rd32
(
dev
,
0x100c80
));
}
}
}
/*
/*
...
...
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