Staging: sep: Introduce sep driver

This driver is for the Security Processor, a dedicated encryption
and decryption driver that is used on the Intel mobile platform.

This has been checked with checkpatch and there are four
warnings for lines over 80 charactors.

There is one compile warning. This is for a function that is
only used if the rar register driver is needed. There is an
ifdef in a header file that stubs out the rar register driver
if the rar register is not configured.

This driver does add a configuration, which is CONFIG_DX_SEP.
Signed-off-by: NMark Allyn <mark.a.allyn@intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

drivers/staging/Kconfig

@@ -119,6 +119,8 @@ source "drivers/staging/vme/Kconfig"
 
 source "drivers/staging/memrar/Kconfig"
 
+source "drivers/staging/sep/Kconfig"
+
 source "drivers/staging/iio/Kconfig"
 
 source "drivers/staging/zram/Kconfig"

drivers/staging/Makefile

@@ -42,6 +42,7 @@ obj-$(CONFIG_FB_UDL)		+= udlfb/
 obj-$(CONFIG_HYPERV)		+= hv/
 obj-$(CONFIG_VME_BUS)		+= vme/
 obj-$(CONFIG_MRST_RAR_HANDLER)	+= memrar/
+obj-$(CONFIG_DX_SEP)            += sep/
 obj-$(CONFIG_IIO)		+= iio/
 obj-$(CONFIG_ZRAM)		+= zram/
 obj-$(CONFIG_WLAGS49_H2)	+= wlags49_h2/

drivers/staging/sep/Kconfig

+config DX_SEP
+	tristate "Discretix SEP driver"
+	depends on PCI
+	default y
+	help
+	  Discretix SEP driver; used for the security processor subsystem
+	  on bard the Intel Mobile Internet Device.
+
+	  The driver's name is sep_driver.
+
+	  If unsure, select N.

drivers/staging/sep/Makefile

+obj-$(CONFIG_DX_SEP) := sep_driver.o
+

drivers/staging/sep/TODO

+Todo's so far (from Alan Cox)
+- Fix firmware loading - Done 09/10 M. Allyn
+- Get firmware into firmware git tree - Firmware is non open source
+- Review and tidy each algorithm function - Done 09/10 M. Allyn
+- Check whether it can be plugged into any of the kernel crypto API
+  interfaces - Crypto API 'glue' is still not ready to submit
+- Do something about the magic shared memory interface and replace it
+  with something saner (in Linux terms) - Done 09/10 M. Allyn
+- Clean up unused ioctls - Needs vendor help
+- Clean up unused fields in ioctl structures - Needs vendor help
+- 64 bit size to be used for all user space addresses passed
+  to ioctl - Done 10/10 M. Allyn

drivers/staging/sep/sep_dev.h

+#ifndef __SEP_DEV_H__
+#define __SEP_DEV_H__
+
+/*
+ *
+ *  sep_dev.h - Security Processor Device Structures
+ *
+ *  Copyright(c) 2009,2010 Intel Corporation. All rights reserved.
+ *  Contributions(c) 2009,2010 Discretix. All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the Free
+ *  Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ *  more details.
+ *
+ *  You should have received a copy of the GNU General Public License along with
+ *  this program; if not, write to the Free Software Foundation, Inc., 59
+ *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ *  CONTACTS:
+ *
+ *  Mark Allyn		mark.a.allyn@intel.com
+ *  Jayant Mangalampalli jayant.mangalampalli@intel.com
+ *
+ *  CHANGES
+ *  2010.09.14  upgrade to Medfield
+ */
+
+struct sep_device {
+	/* pointer to pci dev */
+	struct pci_dev *pdev;
+
+	/* character device file */
+	struct cdev sep_cdev;
+	struct cdev sep_daemon_cdev;
+	struct cdev sep_singleton_cdev;
+
+	/* devices (using misc dev) */
+	struct miscdevice miscdev_sep;
+	struct miscdevice miscdev_singleton;
+	struct miscdevice miscdev_daemon;
+
+	/* major / minor numbers of device */
+	dev_t sep_devno;
+	dev_t sep_daemon_devno;
+	dev_t sep_singleton_devno;
+
+	struct mutex sep_mutex;
+	struct mutex ioctl_mutex;
+	spinlock_t snd_rply_lck;
+
+	/* flags to indicate use and lock status of sep */
+	u32 pid_doing_transaction;
+	unsigned long in_use_flags;
+
+	/* request daemon alread open */
+	unsigned long request_daemon_open;
+
+	/* 1 = Moorestown; 0 = Medfield */
+	int mrst;
+
+	/* address of the shared memory allocated during init for SEP driver
+	   (coherent alloc) */
+	dma_addr_t shared_bus;
+	size_t shared_size;
+	void *shared_addr;
+
+	/* restricted access region (coherent alloc) */
+	dma_addr_t rar_bus;
+	size_t rar_size;
+	void *rar_addr;
+
+	/* Firmware regions; cache is at rar for Moorestown and
+	   resident is at rar for Medfield */
+	dma_addr_t cache_bus;
+	size_t cache_size;
+	void *cache_addr;
+
+	dma_addr_t resident_bus;
+	size_t resident_size;
+	void *resident_addr;
+
+	/* sep's scratchpad */
+	dma_addr_t dcache_bus;
+	size_t dcache_size;
+	void *dcache_addr;
+
+	/* Only used on Medfield */
+	dma_addr_t extapp_bus;
+	size_t extapp_size;
+	void *extapp_addr;
+
+	/* start address of the access to the SEP registers from driver */
+	dma_addr_t reg_physical_addr;
+	dma_addr_t reg_physical_end;
+	void __iomem *reg_addr;
+
+	/* wait queue head (event) of the driver */
+	wait_queue_head_t event;
+	wait_queue_head_t event_request_daemon;
+	wait_queue_head_t event_mmap;
+
+	struct sep_caller_id_entry
+		caller_id_table[SEP_CALLER_ID_TABLE_NUM_ENTRIES];
+
+	/* access flag for singleton device */
+	unsigned long singleton_access_flag;
+
+	/* transaction counter that coordinates the
+	   transactions between SEP and HOST */
+	unsigned long send_ct;
+	/* counter for the messages from sep */
+	unsigned long reply_ct;
+	/* counter for the number of bytes allocated in the pool for the
+	   current transaction */
+	long data_pool_bytes_allocated;
+
+	u32 num_of_data_allocations;
+
+	/* number of the lli tables created in the current transaction */
+	u32     num_lli_tables_created;
+
+	/* number of data control blocks */
+	u32 nr_dcb_creat;
+
+	struct sep_dma_resource dma_res_arr[SEP_MAX_NUM_SYNC_DMA_OPS];
+
+};
+
+static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
+{
+	void __iomem *addr = dev->reg_addr + reg;
+	writel(value, addr);
+}
+
+static inline u32 sep_read_reg(struct sep_device *dev, int reg)
+{
+	void __iomem *addr = dev->reg_addr + reg;
+	return readl(addr);
+}
+
+/* wait for SRAM write complete(indirect write */
+static inline void sep_wait_sram_write(struct sep_device *dev)
+{
+	u32 reg_val;
+	do
+		reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
+	while (!(reg_val & 1));
+}
+
+
+#endif

drivers/staging/sep/sep_driver_api.h

+/*
+ *
+ *  sep_driver_api.h - Security Processor Driver api definitions
+ *
+ *  Copyright(c) 2009,2010 Intel Corporation. All rights reserved.
+ *  Contributions(c) 2009,2010 Discretix. All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the Free
+ *  Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ *  more details.
+ *
+ *  You should have received a copy of the GNU General Public License along with
+ *  this program; if not, write to the Free Software Foundation, Inc., 59
+ *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ *  CONTACTS:
+ *
+ *  Mark Allyn		mark.a.allyn@intel.com
+ *  Jayant Mangalampalli jayant.mangalampalli@intel.com
+ *
+ *  CHANGES:
+ *
+ *  2010.09.14  Upgrade to Medfield
+ *
+ */
+
+#ifndef __SEP_DRIVER_API_H__
+#define __SEP_DRIVER_API_H__
+
+/* Type of request from device */
+#define SEP_DRIVER_SRC_REPLY		1
+#define SEP_DRIVER_SRC_REQ		2
+#define SEP_DRIVER_SRC_PRINTF		3
+
+
+/*-------------------------------------------
+    TYPEDEFS
+----------------------------------------------*/
+
+/*
+ * Note that several members of these structres are only here
+ * for campatability with the middleware; they are not used
+ * by this driver.
+ * All user space buffer addresses are set to aligned u64
+ * in order to ensure compatibility with 64 bit systems
+ */
+
+/*
+  init command struct; this will go away when SCU does init
+*/
+struct init_struct {
+	/* address that SEP can access for message */
+	aligned_u64   message_addr;
+
+	/* message size */
+	u32   message_size_in_words;
+
+	/* offset of the init message in the sep sram */
+	aligned_u64   sep_sram_addr;
+
+	/* -not used- resident size in bytes*/
+	u32   unused_resident_size_in_bytes;
+
+	/* -not used- cache size in bytes*/
+	u32   unused_cache_size_in_bytes;
+
+	/* -not used- ext cache current address */
+	aligned_u64   unused_extcache_addr;
+
+	/* -not used- ext cache size in bytes*/
+	u32   unused_extcache_size_in_bytes;
+};
+
+struct realloc_ext_struct {
+	/* -not used- current external cache address */
+	aligned_u64   unused_ext_cache_addr;
+
+	/* -not used- external cache size in bytes*/
+	u32   unused_ext_cache_size_in_bytes;
+};
+
+struct alloc_struct {
+	/* offset from start of shared pool area */
+	u32  offset;
+	/* number of bytes to allocate */
+	u32  num_bytes;
+};
+
+/*
+	Note that all app addresses are cast as u32; the sep
+	middleware sends them as fixed 32 bit words
+*/
+struct bld_syn_tab_struct {
+	/* address value of the data in (user space addr) */
+	aligned_u64 app_in_address;
+
+	/* size of data in */
+	u32 data_in_size;
+
+	/* address of the data out (user space addr) */
+	aligned_u64 app_out_address;
+
+	/* the size of the block of the operation - if needed,
+	   every table will be modulo this parameter */
+	u32 block_size;
+
+	/* -not used- distinct user/kernel layout */
+	bool isKernelVirtualAddress;
+
+};
+
+/*
+ * command struct for static pool addresses
+ * Please note that this is a kernel virtual
+ * address; this will be removed at the next
+ * release of the Discretix middleware
+ */
+struct stat_pool_addr_struct {
+	/* virtual address of the static pool */
+	aligned_u64 static_virt_address;
+};
+
+
+/* command struct for getting caller id value and address */
+struct caller_id_struct {
+	/* pid of the process */
+	u32 pid;
+	/* virtual address of the caller id hash */
+	aligned_u64 callerIdAddress;
+	/* caller id hash size in bytes */
+	u32 callerIdSizeInBytes;
+};
+
+/*
+  structure that represents DCB
+*/
+struct sep_dcblock {
+	/* physical address of the first input mlli */
+	u32	input_mlli_address;
+	/* num of entries in the first input mlli */
+	u32	input_mlli_num_entries;
+	/* size of data in the first input mlli */
+	u32	input_mlli_data_size;
+	/* physical address of the first output mlli */
+	u32	output_mlli_address;
+	/* num of entries in the first output mlli */
+	u32	output_mlli_num_entries;
+	/* size of data in the first output mlli */
+	u32	output_mlli_data_size;
+	/* pointer to the output virtual tail */
+	u32	out_vr_tail_pt;
+	/* size of tail data */
+	u32	tail_data_size;
+	/* input tail data array */
+	u8	tail_data[64];
+};
+
+struct sep_caller_id_entry {
+	int pid;
+	unsigned char callerIdHash[SEP_CALLER_ID_HASH_SIZE_IN_BYTES];
+};
+
+/*
+	command structure for building dcb block (currently for ext app only
+*/
+struct build_dcb_struct {
+	/* address value of the data in */
+	aligned_u64 app_in_address;
+	/* size of data in */
+	u32  data_in_size;
+	/* address of the data out */
+	aligned_u64 app_out_address;
+	/* the size of the block of the operation - if needed,
+	every table will be modulo this parameter */
+	u32  block_size;
+	/* the size of the block of the operation - if needed,
+	every table will be modulo this parameter */
+	u32  tail_block_size;
+};
+
+/**
+ * @struct sep_dma_map
+ *
+ * Structure that contains all information needed for mapping the user pages
+ *	     or kernel buffers for dma operations
+ *
+ *
+ */
+struct sep_dma_map {
+	/* mapped dma address */
+	dma_addr_t    dma_addr;
+	/* size of the mapped data */
+	size_t        size;
+};
+
+struct sep_dma_resource {
+	/* array of pointers to the pages that represent
+	input data for the synchronic DMA action */
+	struct page **in_page_array;
+
+	/* array of pointers to the pages that represent out
+	data for the synchronic DMA action */
+	struct page **out_page_array;
+
+	/* number of pages in the sep_in_page_array */
+	u32 in_num_pages;
+
+	/* number of pages in the sep_out_page_array */
+	u32 out_num_pages;
+
+	/* map array of the input data */
+	struct sep_dma_map *in_map_array;
+
+	/* map array of the output data */
+	struct sep_dma_map *out_map_array;
+
+	/* number of entries of the input mapp array */
+	u32 in_map_num_entries;
+
+	/* number of entries of the output mapp array */
+	u32 out_map_num_entries;
+};
+
+
+/* command struct for translating rar handle to bus address
+   and setting it at predefined location */
+struct rar_hndl_to_bus_struct {
+
+	/* rar handle */
+	aligned_u64 rar_handle;
+};
+
+/*
+  structure that represent one entry in the DMA LLI table
+*/
+struct sep_lli_entry {
+	/* physical address */
+	u32 bus_address;
+
+	/* block size */
+	u32 block_size;
+};
+
+/*----------------------------------------------------------------
+	IOCTL command defines
+	-----------------------------------------------------------------*/
+
+/* magic number 1 of the sep IOCTL command */
+#define SEP_IOC_MAGIC_NUMBER	                     's'
+
+/* sends interrupt to sep that message is ready */
+#define SEP_IOCSENDSEPCOMMAND	 \
+	_IO(SEP_IOC_MAGIC_NUMBER, 0)
+
+/* sends interrupt to sep that message is ready */
+#define SEP_IOCSENDSEPRPLYCOMMAND	 \
+	_IO(SEP_IOC_MAGIC_NUMBER, 1)
+
+/* allocate memory in data pool */
+#define SEP_IOCALLOCDATAPOLL	\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 2, struct alloc_struct)
+
+/* create sym dma lli tables */
+#define SEP_IOCCREATESYMDMATABLE	\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 5, struct bld_syn_tab_struct)
+
+/* free dynamic data aalocated during table creation */
+#define SEP_IOCFREEDMATABLEDATA	 \
+	_IO(SEP_IOC_MAGIC_NUMBER, 7)
+
+/* get the static pool area addersses (physical and virtual) */
+#define SEP_IOCGETSTATICPOOLADDR	\
+	_IOR(SEP_IOC_MAGIC_NUMBER, 8, struct stat_pool_addr_struct)
+
+/* start sep command */
+#define SEP_IOCSEPSTART	 \
+	_IO(SEP_IOC_MAGIC_NUMBER, 12)
+
+/* init sep command */
+#define SEP_IOCSEPINIT	\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 13, struct init_struct)
+
+/* end transaction command */
+#define SEP_IOCENDTRANSACTION	 \
+	_IO(SEP_IOC_MAGIC_NUMBER, 15)
+
+/* reallocate external app; unused structure still needed for
+ * compatability with middleware */
+#define SEP_IOCREALLOCEXTCACHE	\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 18, struct realloc_ext_struct)
+
+#define SEP_IOCRARPREPAREMESSAGE	\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 20, struct rar_hndl_to_bus_struct)
+
+#define SEP_IOCTLSETCALLERID	\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 34, struct caller_id_struct)
+
+#define SEP_IOCPREPAREDCB					\
+	_IOW(SEP_IOC_MAGIC_NUMBER, 35, struct build_dcb_struct)
+
+#define SEP_IOCFREEDCB					\
+	_IO(SEP_IOC_MAGIC_NUMBER, 36)
+
+#endif

drivers/staging/sep/sep_driver_hw_defs.h

+/*
+ *
+ *  sep_driver_hw_defs.h - Security Processor Driver hardware definitions
+ *
+ *  Copyright(c) 2009,2010 Intel Corporation. All rights reserved.
+ *  Contributions(c) 2009,2010 Discretix. All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the Free
+ *  Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ *  more details.
+ *
+ *  You should have received a copy of the GNU General Public License along with
+ *  this program; if not, write to the Free Software Foundation, Inc., 59
+ *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ *  CONTACTS:
+ *
+ *  Mark Allyn		mark.a.allyn@intel.com
+ *  Jayant Mangalampalli jayant.mangalampalli@intel.com
+ *
+ *  CHANGES:
+ *
+ *  2010.09.20	Upgrade to Medfield
+ *
+ */
+
+#ifndef SEP_DRIVER_HW_DEFS__H
+#define SEP_DRIVER_HW_DEFS__H
+
+/* PCI ID's */
+#define MRST_PCI_DEVICE_ID 0x080c
+#define MFLD_PCI_DEVICE_ID 0x0826
+
+/*----------------------- */
+/* HW Registers Defines.  */
+/*                        */
+/*---------------------- -*/
+
+
+/* cf registers */
+#define		HW_R0B_ADDR_0_REG_ADDR			0x0000UL
+#define		HW_R0B_ADDR_1_REG_ADDR			0x0004UL
+#define		HW_R0B_ADDR_2_REG_ADDR			0x0008UL
+#define		HW_R0B_ADDR_3_REG_ADDR			0x000cUL
+#define		HW_R0B_ADDR_4_REG_ADDR			0x0010UL
+#define		HW_R0B_ADDR_5_REG_ADDR			0x0014UL
+#define		HW_R0B_ADDR_6_REG_ADDR			0x0018UL
+#define		HW_R0B_ADDR_7_REG_ADDR			0x001cUL
+#define		HW_R0B_ADDR_8_REG_ADDR			0x0020UL
+#define		HW_R2B_ADDR_0_REG_ADDR			0x0080UL
+#define		HW_R2B_ADDR_1_REG_ADDR			0x0084UL
+#define		HW_R2B_ADDR_2_REG_ADDR			0x0088UL
+#define		HW_R2B_ADDR_3_REG_ADDR			0x008cUL
+#define		HW_R2B_ADDR_4_REG_ADDR			0x0090UL
+#define		HW_R2B_ADDR_5_REG_ADDR			0x0094UL
+#define		HW_R2B_ADDR_6_REG_ADDR			0x0098UL
+#define		HW_R2B_ADDR_7_REG_ADDR			0x009cUL
+#define		HW_R2B_ADDR_8_REG_ADDR			0x00a0UL
+#define		HW_R3B_REG_ADDR				0x00C0UL
+#define		HW_R4B_REG_ADDR				0x0100UL
+#define		HW_CSA_ADDR_0_REG_ADDR			0x0140UL
+#define		HW_CSA_ADDR_1_REG_ADDR			0x0144UL
+#define		HW_CSA_ADDR_2_REG_ADDR			0x0148UL
+#define		HW_CSA_ADDR_3_REG_ADDR			0x014cUL
+#define		HW_CSA_ADDR_4_REG_ADDR			0x0150UL
+#define		HW_CSA_ADDR_5_REG_ADDR			0x0154UL
+#define		HW_CSA_ADDR_6_REG_ADDR			0x0158UL
+#define		HW_CSA_ADDR_7_REG_ADDR			0x015cUL
+#define		HW_CSA_ADDR_8_REG_ADDR			0x0160UL
+#define		HW_CSA_REG_ADDR				0x0140UL
+#define		HW_SINB_REG_ADDR			0x0180UL
+#define		HW_SOUTB_REG_ADDR			0x0184UL
+#define		HW_PKI_CONTROL_REG_ADDR			0x01C0UL
+#define		HW_PKI_STATUS_REG_ADDR			0x01C4UL
+#define		HW_PKI_BUSY_REG_ADDR			0x01C8UL
+#define		HW_PKI_A_1025_REG_ADDR			0x01CCUL
+#define		HW_PKI_SDMA_CTL_REG_ADDR		0x01D0UL
+#define		HW_PKI_SDMA_OFFSET_REG_ADDR		0x01D4UL
+#define		HW_PKI_SDMA_POINTERS_REG_ADDR		0x01D8UL
+#define		HW_PKI_SDMA_DLENG_REG_ADDR		0x01DCUL
+#define		HW_PKI_SDMA_EXP_POINTERS_REG_ADDR	0x01E0UL
+#define		HW_PKI_SDMA_RES_POINTERS_REG_ADDR	0x01E4UL
+#define		HW_PKI_CLR_REG_ADDR			0x01E8UL
+#define		HW_PKI_SDMA_BUSY_REG_ADDR		0x01E8UL
+#define		HW_PKI_SDMA_FIRST_EXP_N_REG_ADDR	0x01ECUL
+#define		HW_PKI_SDMA_MUL_BY1_REG_ADDR		0x01F0UL
+#define		HW_PKI_SDMA_RMUL_SEL_REG_ADDR		0x01F4UL
+#define		HW_DES_KEY_0_REG_ADDR			0x0208UL
+#define		HW_DES_KEY_1_REG_ADDR			0x020CUL
+#define		HW_DES_KEY_2_REG_ADDR			0x0210UL
+#define		HW_DES_KEY_3_REG_ADDR			0x0214UL
+#define		HW_DES_KEY_4_REG_ADDR			0x0218UL
+#define		HW_DES_KEY_5_REG_ADDR			0x021CUL
+#define		HW_DES_CONTROL_0_REG_ADDR		0x0220UL
+#define		HW_DES_CONTROL_1_REG_ADDR		0x0224UL
+#define		HW_DES_IV_0_REG_ADDR			0x0228UL
+#define		HW_DES_IV_1_REG_ADDR			0x022CUL
+#define		HW_AES_KEY_0_ADDR_0_REG_ADDR		0x0400UL
+#define		HW_AES_KEY_0_ADDR_1_REG_ADDR		0x0404UL
+#define		HW_AES_KEY_0_ADDR_2_REG_ADDR		0x0408UL
+#define		HW_AES_KEY_0_ADDR_3_REG_ADDR		0x040cUL
+#define		HW_AES_KEY_0_ADDR_4_REG_ADDR		0x0410UL
+#define		HW_AES_KEY_0_ADDR_5_REG_ADDR		0x0414UL
+#define		HW_AES_KEY_0_ADDR_6_REG_ADDR		0x0418UL
+#define		HW_AES_KEY_0_ADDR_7_REG_ADDR		0x041cUL
+#define		HW_AES_KEY_0_REG_ADDR			0x0400UL
+#define		HW_AES_IV_0_ADDR_0_REG_ADDR		0x0440UL
+#define		HW_AES_IV_0_ADDR_1_REG_ADDR		0x0444UL
+#define		HW_AES_IV_0_ADDR_2_REG_ADDR		0x0448UL
+#define		HW_AES_IV_0_ADDR_3_REG_ADDR		0x044cUL
+#define		HW_AES_IV_0_REG_ADDR			0x0440UL
+#define		HW_AES_CTR1_ADDR_0_REG_ADDR		0x0460UL
+#define		HW_AES_CTR1_ADDR_1_REG_ADDR		0x0464UL
+#define		HW_AES_CTR1_ADDR_2_REG_ADDR		0x0468UL
+#define		HW_AES_CTR1_ADDR_3_REG_ADDR		0x046cUL
+#define		HW_AES_CTR1_REG_ADDR			0x0460UL
+#define		HW_AES_SK_REG_ADDR			0x0478UL
+#define		HW_AES_MAC_OK_REG_ADDR			0x0480UL
+#define		HW_AES_PREV_IV_0_ADDR_0_REG_ADDR	0x0490UL
+#define		HW_AES_PREV_IV_0_ADDR_1_REG_ADDR	0x0494UL
+#define		HW_AES_PREV_IV_0_ADDR_2_REG_ADDR	0x0498UL
+#define		HW_AES_PREV_IV_0_ADDR_3_REG_ADDR	0x049cUL
+#define		HW_AES_PREV_IV_0_REG_ADDR		0x0490UL
+#define		HW_AES_CONTROL_REG_ADDR			0x04C0UL
+#define		HW_HASH_H0_REG_ADDR			0x0640UL
+#define		HW_HASH_H1_REG_ADDR			0x0644UL
+#define		HW_HASH_H2_REG_ADDR			0x0648UL
+#define		HW_HASH_H3_REG_ADDR			0x064CUL
+#define		HW_HASH_H4_REG_ADDR			0x0650UL
+#define		HW_HASH_H5_REG_ADDR			0x0654UL
+#define		HW_HASH_H6_REG_ADDR			0x0658UL
+#define		HW_HASH_H7_REG_ADDR			0x065CUL
+#define		HW_HASH_H8_REG_ADDR			0x0660UL
+#define		HW_HASH_H9_REG_ADDR			0x0664UL
+#define		HW_HASH_H10_REG_ADDR			0x0668UL
+#define		HW_HASH_H11_REG_ADDR			0x066CUL
+#define		HW_HASH_H12_REG_ADDR			0x0670UL
+#define		HW_HASH_H13_REG_ADDR			0x0674UL
+#define		HW_HASH_H14_REG_ADDR			0x0678UL
+#define		HW_HASH_H15_REG_ADDR			0x067CUL
+#define		HW_HASH_CONTROL_REG_ADDR		0x07C0UL
+#define		HW_HASH_PAD_EN_REG_ADDR			0x07C4UL
+#define		HW_HASH_PAD_CFG_REG_ADDR		0x07C8UL
+#define		HW_HASH_CUR_LEN_0_REG_ADDR		0x07CCUL
+#define		HW_HASH_CUR_LEN_1_REG_ADDR		0x07D0UL
+#define		HW_HASH_CUR_LEN_2_REG_ADDR		0x07D4UL
+#define		HW_HASH_CUR_LEN_3_REG_ADDR		0x07D8UL
+#define		HW_HASH_PARAM_REG_ADDR			0x07DCUL
+#define		HW_HASH_INT_BUSY_REG_ADDR		0x07E0UL
+#define		HW_HASH_SW_RESET_REG_ADDR		0x07E4UL
+#define		HW_HASH_ENDIANESS_REG_ADDR		0x07E8UL
+#define		HW_HASH_DATA_REG_ADDR			0x07ECUL
+#define		HW_DRNG_CONTROL_REG_ADDR		0x0800UL
+#define		HW_DRNG_VALID_REG_ADDR			0x0804UL
+#define		HW_DRNG_DATA_REG_ADDR			0x0808UL
+#define		HW_RND_SRC_EN_REG_ADDR			0x080CUL
+#define		HW_AES_CLK_ENABLE_REG_ADDR		0x0810UL
+#define		HW_DES_CLK_ENABLE_REG_ADDR		0x0814UL
+#define		HW_HASH_CLK_ENABLE_REG_ADDR		0x0818UL
+#define		HW_PKI_CLK_ENABLE_REG_ADDR		0x081CUL
+#define		HW_CLK_STATUS_REG_ADDR			0x0824UL
+#define		HW_CLK_ENABLE_REG_ADDR			0x0828UL
+#define		HW_DRNG_SAMPLE_REG_ADDR			0x0850UL
+#define		HW_RND_SRC_CTL_REG_ADDR			0x0858UL
+#define		HW_CRYPTO_CTL_REG_ADDR			0x0900UL
+#define		HW_CRYPTO_STATUS_REG_ADDR		0x090CUL
+#define		HW_CRYPTO_BUSY_REG_ADDR			0x0910UL
+#define		HW_AES_BUSY_REG_ADDR			0x0914UL
+#define		HW_DES_BUSY_REG_ADDR			0x0918UL
+#define		HW_HASH_BUSY_REG_ADDR			0x091CUL
+#define		HW_CONTENT_REG_ADDR			0x0924UL
+#define		HW_VERSION_REG_ADDR			0x0928UL
+#define		HW_CONTEXT_ID_REG_ADDR			0x0930UL
+#define		HW_DIN_BUFFER_REG_ADDR			0x0C00UL
+#define		HW_DIN_MEM_DMA_BUSY_REG_ADDR		0x0c20UL
+#define		HW_SRC_LLI_MEM_ADDR_REG_ADDR		0x0c24UL
+#define		HW_SRC_LLI_WORD0_REG_ADDR		0x0C28UL
+#define		HW_SRC_LLI_WORD1_REG_ADDR		0x0C2CUL
+#define		HW_SRAM_SRC_ADDR_REG_ADDR		0x0c30UL
+#define		HW_DIN_SRAM_BYTES_LEN_REG_ADDR		0x0c34UL
+#define		HW_DIN_SRAM_DMA_BUSY_REG_ADDR		0x0C38UL
+#define		HW_WRITE_ALIGN_REG_ADDR			0x0C3CUL
+#define		HW_OLD_DATA_REG_ADDR			0x0C48UL
+#define		HW_WRITE_ALIGN_LAST_REG_ADDR		0x0C4CUL
+#define		HW_DOUT_BUFFER_REG_ADDR			0x0C00UL
+#define		HW_DST_LLI_WORD0_REG_ADDR		0x0D28UL
+#define		HW_DST_LLI_WORD1_REG_ADDR		0x0D2CUL
+#define		HW_DST_LLI_MEM_ADDR_REG_ADDR		0x0D24UL
+#define		HW_DOUT_MEM_DMA_BUSY_REG_ADDR		0x0D20UL
+#define		HW_SRAM_DEST_ADDR_REG_ADDR		0x0D30UL
+#define		HW_DOUT_SRAM_BYTES_LEN_REG_ADDR		0x0D34UL
+#define		HW_DOUT_SRAM_DMA_BUSY_REG_ADDR		0x0D38UL
+#define		HW_READ_ALIGN_REG_ADDR			0x0D3CUL
+#define		HW_READ_LAST_DATA_REG_ADDR		0x0D44UL
+#define		HW_RC4_THRU_CPU_REG_ADDR		0x0D4CUL
+#define		HW_AHB_SINGLE_REG_ADDR			0x0E00UL
+#define		HW_SRAM_DATA_REG_ADDR			0x0F00UL
+#define		HW_SRAM_ADDR_REG_ADDR			0x0F04UL
+#define		HW_SRAM_DATA_READY_REG_ADDR		0x0F08UL
+#define		HW_HOST_IRR_REG_ADDR			0x0A00UL
+#define		HW_HOST_IMR_REG_ADDR			0x0A04UL
+#define		HW_HOST_ICR_REG_ADDR			0x0A08UL
+#define		HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR	0x0A10UL
+#define		HW_HOST_SEP_BUSY_REG_ADDR		0x0A14UL
+#define		HW_HOST_SEP_LCS_REG_ADDR		0x0A18UL
+#define		HW_HOST_CC_SW_RST_REG_ADDR		0x0A40UL
+#define		HW_HOST_SEP_SW_RST_REG_ADDR		0x0A44UL
+#define		HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR	0x0A80UL
+#define		HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR	0x0A84UL
+#define		HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR	0x0A88UL
+#define		HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR	0x0A8cUL
+#define		HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR	0x0A90UL
+#define		HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR	0x0A94UL
+#define		HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR	0x0A98UL
+#define		HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR	0x0A9cUL
+#define		HW_HOST_SEP_HOST_GPR0_REG_ADDR		0x0B00UL
+#define		HW_HOST_SEP_HOST_GPR1_REG_ADDR		0x0B04UL
+#define		HW_HOST_SEP_HOST_GPR2_REG_ADDR		0x0B08UL
+#define		HW_HOST_SEP_HOST_GPR3_REG_ADDR		0x0B0CUL
+#define		HW_HOST_HOST_SEP_GPR0_REG_ADDR		0x0B80UL
+#define		HW_HOST_HOST_SEP_GPR1_REG_ADDR		0x0B84UL
+#define		HW_HOST_HOST_SEP_GPR2_REG_ADDR		0x0B88UL
+#define		HW_HOST_HOST_SEP_GPR3_REG_ADDR		0x0B8CUL
+#define		HW_HOST_HOST_ENDIAN_REG_ADDR		0x0B90UL
+#define		HW_HOST_HOST_COMM_CLK_EN_REG_ADDR	0x0B94UL
+#define		HW_CLR_SRAM_BUSY_REG_REG_ADDR		0x0F0CUL
+#define		HW_CC_SRAM_BASE_ADDRESS			0x5800UL
+
+#endif		/* ifndef HW_DEFS */