提交 476eb491 编写于 作者: G Grant Likely 提交者: Benjamin Herrenschmidt

powerpc/irq: Stop exporting irq_map

First step in eliminating irq_map[] table entirely
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
上级 65f47f13
...@@ -128,25 +128,10 @@ struct irq_host { ...@@ -128,25 +128,10 @@ struct irq_host {
struct device_node *of_node; struct device_node *of_node;
}; };
/* The main irq map itself is an array of NR_IRQ entries containing the struct irq_data;
* associate host and irq number. An entry with a host of NULL is free. extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
* An entry can be allocated if it's free, the allocator always then sets
* hwirq first to the host's invalid irq number and then fills ops.
*/
struct irq_map_entry {
irq_hw_number_t hwirq;
struct irq_host *host;
};
extern struct irq_map_entry irq_map[NR_IRQS];
extern irq_hw_number_t virq_to_hw(unsigned int virq); extern irq_hw_number_t virq_to_hw(unsigned int virq);
extern struct irq_host *virq_to_host(unsigned int virq);
/* This will eventually -replace- virq_to_hw if/when we stash the
* HW number in the irq_data itself. We use a macro so we can inline
* it as irq_data isn't defined yet
*/
#define irq_data_to_hw(d) (irq_map[(d)->irq].hwirq)
/** /**
* irq_alloc_host - Allocate a new irq_host data structure * irq_alloc_host - Allocate a new irq_host data structure
......
...@@ -481,20 +481,42 @@ void do_softirq(void) ...@@ -481,20 +481,42 @@ void do_softirq(void)
* IRQ controller and virtual interrupts * IRQ controller and virtual interrupts
*/ */
/* The main irq map itself is an array of NR_IRQ entries containing the
* associate host and irq number. An entry with a host of NULL is free.
* An entry can be allocated if it's free, the allocator always then sets
* hwirq first to the host's invalid irq number and then fills ops.
*/
struct irq_map_entry {
irq_hw_number_t hwirq;
struct irq_host *host;
};
static LIST_HEAD(irq_hosts); static LIST_HEAD(irq_hosts);
static DEFINE_RAW_SPINLOCK(irq_big_lock); static DEFINE_RAW_SPINLOCK(irq_big_lock);
static unsigned int revmap_trees_allocated; static unsigned int revmap_trees_allocated;
static DEFINE_MUTEX(revmap_trees_mutex); static DEFINE_MUTEX(revmap_trees_mutex);
struct irq_map_entry irq_map[NR_IRQS]; static struct irq_map_entry irq_map[NR_IRQS];
static unsigned int irq_virq_count = NR_IRQS; static unsigned int irq_virq_count = NR_IRQS;
static struct irq_host *irq_default_host; static struct irq_host *irq_default_host;
irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
{
return irq_map[d->irq].hwirq;
}
EXPORT_SYMBOL_GPL(irqd_to_hwirq);
irq_hw_number_t virq_to_hw(unsigned int virq) irq_hw_number_t virq_to_hw(unsigned int virq)
{ {
return irq_map[virq].hwirq; return irq_map[virq].hwirq;
} }
EXPORT_SYMBOL_GPL(virq_to_hw); EXPORT_SYMBOL_GPL(virq_to_hw);
struct irq_host *virq_to_host(unsigned int virq)
{
return irq_map[virq].host;
}
EXPORT_SYMBOL_GPL(virq_to_host);
static int default_irq_host_match(struct irq_host *h, struct device_node *np) static int default_irq_host_match(struct irq_host *h, struct device_node *np)
{ {
return h->of_node != NULL && h->of_node == np; return h->of_node != NULL && h->of_node == np;
...@@ -1103,7 +1125,7 @@ static int virq_debug_show(struct seq_file *m, void *private) ...@@ -1103,7 +1125,7 @@ static int virq_debug_show(struct seq_file *m, void *private)
struct irq_chip *chip; struct irq_chip *chip;
seq_printf(m, "%5d ", i); seq_printf(m, "%5d ", i);
seq_printf(m, "0x%05lx ", virq_to_hw(i)); seq_printf(m, "0x%05lx ", irq_map[i].hwirq);
chip = irq_desc_get_chip(desc); chip = irq_desc_get_chip(desc);
if (chip && chip->name) if (chip && chip->name)
......
...@@ -61,7 +61,7 @@ irq_to_pic_bit(unsigned int irq) ...@@ -61,7 +61,7 @@ irq_to_pic_bit(unsigned int irq)
static void static void
cpld_mask_irq(struct irq_data *d) cpld_mask_irq(struct irq_data *d)
{ {
unsigned int cpld_irq = (unsigned int)irq_map[d->irq].hwirq; unsigned int cpld_irq = (unsigned int)irqd_to_hwirq(d);
void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); void __iomem *pic_mask = irq_to_pic_mask(cpld_irq);
out_8(pic_mask, out_8(pic_mask,
...@@ -71,7 +71,7 @@ cpld_mask_irq(struct irq_data *d) ...@@ -71,7 +71,7 @@ cpld_mask_irq(struct irq_data *d)
static void static void
cpld_unmask_irq(struct irq_data *d) cpld_unmask_irq(struct irq_data *d)
{ {
unsigned int cpld_irq = (unsigned int)irq_map[d->irq].hwirq; unsigned int cpld_irq = (unsigned int)irqd_to_hwirq(d);
void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); void __iomem *pic_mask = irq_to_pic_mask(cpld_irq);
out_8(pic_mask, out_8(pic_mask,
......
...@@ -56,7 +56,7 @@ static void media5200_irq_unmask(struct irq_data *d) ...@@ -56,7 +56,7 @@ static void media5200_irq_unmask(struct irq_data *d)
spin_lock_irqsave(&media5200_irq.lock, flags); spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq); val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d));
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags); spin_unlock_irqrestore(&media5200_irq.lock, flags);
} }
...@@ -68,7 +68,7 @@ static void media5200_irq_mask(struct irq_data *d) ...@@ -68,7 +68,7 @@ static void media5200_irq_mask(struct irq_data *d)
spin_lock_irqsave(&media5200_irq.lock, flags); spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq)); val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)));
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags); spin_unlock_irqrestore(&media5200_irq.lock, flags);
} }
......
...@@ -157,48 +157,30 @@ static inline void io_be_clrbit(u32 __iomem *addr, int bitno) ...@@ -157,48 +157,30 @@ static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
*/ */
static void mpc52xx_extirq_mask(struct irq_data *d) static void mpc52xx_extirq_mask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->ctrl, 11 - l2irq); io_be_clrbit(&intr->ctrl, 11 - l2irq);
} }
static void mpc52xx_extirq_unmask(struct irq_data *d) static void mpc52xx_extirq_unmask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->ctrl, 11 - l2irq); io_be_setbit(&intr->ctrl, 11 - l2irq);
} }
static void mpc52xx_extirq_ack(struct irq_data *d) static void mpc52xx_extirq_ack(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->ctrl, 27-l2irq); io_be_setbit(&intr->ctrl, 27-l2irq);
} }
static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type) static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
{ {
u32 ctrl_reg, type; u32 ctrl_reg, type;
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
void *handler = handle_level_irq; void *handler = handle_level_irq;
irq = irq_map[d->irq].hwirq; pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__,
l2irq = irq & MPC52xx_IRQ_L2_MASK; (int) irqd_to_hwirq(d), l2irq, flow_type);
pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
switch (flow_type) { switch (flow_type) {
case IRQF_TRIGGER_HIGH: type = 0; break; case IRQF_TRIGGER_HIGH: type = 0; break;
...@@ -237,23 +219,13 @@ static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -237,23 +219,13 @@ static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type)
static void mpc52xx_main_mask(struct irq_data *d) static void mpc52xx_main_mask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->main_mask, 16 - l2irq); io_be_setbit(&intr->main_mask, 16 - l2irq);
} }
static void mpc52xx_main_unmask(struct irq_data *d) static void mpc52xx_main_unmask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->main_mask, 16 - l2irq); io_be_clrbit(&intr->main_mask, 16 - l2irq);
} }
...@@ -270,23 +242,13 @@ static struct irq_chip mpc52xx_main_irqchip = { ...@@ -270,23 +242,13 @@ static struct irq_chip mpc52xx_main_irqchip = {
*/ */
static void mpc52xx_periph_mask(struct irq_data *d) static void mpc52xx_periph_mask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->per_mask, 31 - l2irq); io_be_setbit(&intr->per_mask, 31 - l2irq);
} }
static void mpc52xx_periph_unmask(struct irq_data *d) static void mpc52xx_periph_unmask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->per_mask, 31 - l2irq); io_be_clrbit(&intr->per_mask, 31 - l2irq);
} }
...@@ -303,34 +265,19 @@ static struct irq_chip mpc52xx_periph_irqchip = { ...@@ -303,34 +265,19 @@ static struct irq_chip mpc52xx_periph_irqchip = {
*/ */
static void mpc52xx_sdma_mask(struct irq_data *d) static void mpc52xx_sdma_mask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&sdma->IntMask, l2irq); io_be_setbit(&sdma->IntMask, l2irq);
} }
static void mpc52xx_sdma_unmask(struct irq_data *d) static void mpc52xx_sdma_unmask(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&sdma->IntMask, l2irq); io_be_clrbit(&sdma->IntMask, l2irq);
} }
static void mpc52xx_sdma_ack(struct irq_data *d) static void mpc52xx_sdma_ack(struct irq_data *d)
{ {
int irq; int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
out_be32(&sdma->IntPend, 1 << l2irq); out_be32(&sdma->IntPend, 1 << l2irq);
} }
......
...@@ -42,7 +42,7 @@ struct pq2ads_pci_pic { ...@@ -42,7 +42,7 @@ struct pq2ads_pci_pic {
static void pq2ads_pci_mask_irq(struct irq_data *d) static void pq2ads_pci_mask_irq(struct irq_data *d)
{ {
struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d); struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
int irq = NUM_IRQS - virq_to_hw(d->irq) - 1; int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
if (irq != -1) { if (irq != -1) {
unsigned long flags; unsigned long flags;
...@@ -58,7 +58,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d) ...@@ -58,7 +58,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d)
static void pq2ads_pci_unmask_irq(struct irq_data *d) static void pq2ads_pci_unmask_irq(struct irq_data *d)
{ {
struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d); struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
int irq = NUM_IRQS - virq_to_hw(d->irq) - 1; int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
if (irq != -1) { if (irq != -1) {
unsigned long flags; unsigned long flags;
......
...@@ -48,8 +48,6 @@ static struct socrates_fpga_irq_info fpga_irqs[SOCRATES_FPGA_NUM_IRQS] = { ...@@ -48,8 +48,6 @@ static struct socrates_fpga_irq_info fpga_irqs[SOCRATES_FPGA_NUM_IRQS] = {
[8] = {0, IRQ_TYPE_LEVEL_HIGH}, [8] = {0, IRQ_TYPE_LEVEL_HIGH},
}; };
#define socrates_fpga_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
static DEFINE_RAW_SPINLOCK(socrates_fpga_pic_lock); static DEFINE_RAW_SPINLOCK(socrates_fpga_pic_lock);
static void __iomem *socrates_fpga_pic_iobase; static void __iomem *socrates_fpga_pic_iobase;
...@@ -110,11 +108,9 @@ void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) ...@@ -110,11 +108,9 @@ void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
static void socrates_fpga_pic_ack(struct irq_data *d) static void socrates_fpga_pic_ack(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq, irq_line; unsigned int irq_line, hwirq = irqd_to_hwirq(d);
uint32_t mask; uint32_t mask;
hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line; irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
...@@ -127,12 +123,10 @@ static void socrates_fpga_pic_ack(struct irq_data *d) ...@@ -127,12 +123,10 @@ static void socrates_fpga_pic_ack(struct irq_data *d)
static void socrates_fpga_pic_mask(struct irq_data *d) static void socrates_fpga_pic_mask(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
int irq_line; int irq_line;
u32 mask; u32 mask;
hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line; irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
...@@ -145,12 +139,10 @@ static void socrates_fpga_pic_mask(struct irq_data *d) ...@@ -145,12 +139,10 @@ static void socrates_fpga_pic_mask(struct irq_data *d)
static void socrates_fpga_pic_mask_ack(struct irq_data *d) static void socrates_fpga_pic_mask_ack(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
int irq_line; int irq_line;
u32 mask; u32 mask;
hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line; irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
...@@ -164,12 +156,10 @@ static void socrates_fpga_pic_mask_ack(struct irq_data *d) ...@@ -164,12 +156,10 @@ static void socrates_fpga_pic_mask_ack(struct irq_data *d)
static void socrates_fpga_pic_unmask(struct irq_data *d) static void socrates_fpga_pic_unmask(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
int irq_line; int irq_line;
u32 mask; u32 mask;
hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line; irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
...@@ -182,12 +172,10 @@ static void socrates_fpga_pic_unmask(struct irq_data *d) ...@@ -182,12 +172,10 @@ static void socrates_fpga_pic_unmask(struct irq_data *d)
static void socrates_fpga_pic_eoi(struct irq_data *d) static void socrates_fpga_pic_eoi(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
int irq_line; int irq_line;
u32 mask; u32 mask;
hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line; irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line))
...@@ -201,12 +189,10 @@ static int socrates_fpga_pic_set_type(struct irq_data *d, ...@@ -201,12 +189,10 @@ static int socrates_fpga_pic_set_type(struct irq_data *d,
unsigned int flow_type) unsigned int flow_type)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
int polarity; int polarity;
u32 mask; u32 mask;
hwirq = socrates_fpga_irq_to_hw(d->irq);
if (fpga_irqs[hwirq].type != IRQ_TYPE_NONE) if (fpga_irqs[hwirq].type != IRQ_TYPE_NONE)
return -EINVAL; return -EINVAL;
......
...@@ -46,8 +46,6 @@ ...@@ -46,8 +46,6 @@
#define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0) #define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
#define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1) #define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
#define gef_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
static DEFINE_RAW_SPINLOCK(gef_pic_lock); static DEFINE_RAW_SPINLOCK(gef_pic_lock);
...@@ -113,11 +111,9 @@ void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) ...@@ -113,11 +111,9 @@ void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
static void gef_pic_mask(struct irq_data *d) static void gef_pic_mask(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
u32 mask; u32 mask;
hwirq = gef_irq_to_hw(d->irq);
raw_spin_lock_irqsave(&gef_pic_lock, flags); raw_spin_lock_irqsave(&gef_pic_lock, flags);
mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
mask &= ~(1 << hwirq); mask &= ~(1 << hwirq);
...@@ -136,11 +132,9 @@ static void gef_pic_mask_ack(struct irq_data *d) ...@@ -136,11 +132,9 @@ static void gef_pic_mask_ack(struct irq_data *d)
static void gef_pic_unmask(struct irq_data *d) static void gef_pic_unmask(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int hwirq; unsigned int hwirq = irqd_to_hwirq(d);
u32 mask; u32 mask;
hwirq = gef_irq_to_hw(d->irq);
raw_spin_lock_irqsave(&gef_pic_lock, flags); raw_spin_lock_irqsave(&gef_pic_lock, flags);
mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
mask |= (1 << hwirq); mask |= (1 << hwirq);
......
...@@ -150,7 +150,7 @@ void __init mpc8xx_calibrate_decr(void) ...@@ -150,7 +150,7 @@ void __init mpc8xx_calibrate_decr(void)
*/ */
cpu = of_find_node_by_type(NULL, "cpu"); cpu = of_find_node_by_type(NULL, "cpu");
virq= irq_of_parse_and_map(cpu, 0); virq= irq_of_parse_and_map(cpu, 0);
irq = irq_map[virq].hwirq; irq = virq_to_hw(virq);
sys_tmr2 = immr_map(im_sit); sys_tmr2 = immr_map(im_sit);
out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) | out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
......
...@@ -113,7 +113,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) ...@@ -113,7 +113,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
pr_devel("axon_msi: woff %x roff %x msi %x\n", pr_devel("axon_msi: woff %x roff %x msi %x\n",
write_offset, msic->read_offset, msi); write_offset, msic->read_offset, msi);
if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) { if (msi < NR_IRQS && virq_to_host(msi) == msic->irq_host) {
generic_handle_irq(msi); generic_handle_irq(msi);
msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
} else { } else {
......
...@@ -70,7 +70,7 @@ static struct spider_pic spider_pics[SPIDER_CHIP_COUNT]; ...@@ -70,7 +70,7 @@ static struct spider_pic spider_pics[SPIDER_CHIP_COUNT];
static struct spider_pic *spider_virq_to_pic(unsigned int virq) static struct spider_pic *spider_virq_to_pic(unsigned int virq)
{ {
return irq_map[virq].host->host_data; return virq_to_host(virq)->host_data;
} }
static void __iomem *spider_get_irq_config(struct spider_pic *pic, static void __iomem *spider_get_irq_config(struct spider_pic *pic,
...@@ -82,7 +82,7 @@ static void __iomem *spider_get_irq_config(struct spider_pic *pic, ...@@ -82,7 +82,7 @@ static void __iomem *spider_get_irq_config(struct spider_pic *pic,
static void spider_unmask_irq(struct irq_data *d) static void spider_unmask_irq(struct irq_data *d)
{ {
struct spider_pic *pic = spider_virq_to_pic(d->irq); struct spider_pic *pic = spider_virq_to_pic(d->irq);
void __iomem *cfg = spider_get_irq_config(pic, irq_map[d->irq].hwirq); void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));
out_be32(cfg, in_be32(cfg) | 0x30000000u); out_be32(cfg, in_be32(cfg) | 0x30000000u);
} }
...@@ -90,7 +90,7 @@ static void spider_unmask_irq(struct irq_data *d) ...@@ -90,7 +90,7 @@ static void spider_unmask_irq(struct irq_data *d)
static void spider_mask_irq(struct irq_data *d) static void spider_mask_irq(struct irq_data *d)
{ {
struct spider_pic *pic = spider_virq_to_pic(d->irq); struct spider_pic *pic = spider_virq_to_pic(d->irq);
void __iomem *cfg = spider_get_irq_config(pic, irq_map[d->irq].hwirq); void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));
out_be32(cfg, in_be32(cfg) & ~0x30000000u); out_be32(cfg, in_be32(cfg) & ~0x30000000u);
} }
...@@ -98,7 +98,7 @@ static void spider_mask_irq(struct irq_data *d) ...@@ -98,7 +98,7 @@ static void spider_mask_irq(struct irq_data *d)
static void spider_ack_irq(struct irq_data *d) static void spider_ack_irq(struct irq_data *d)
{ {
struct spider_pic *pic = spider_virq_to_pic(d->irq); struct spider_pic *pic = spider_virq_to_pic(d->irq);
unsigned int src = irq_map[d->irq].hwirq; unsigned int src = irqd_to_hwirq(d);
/* Reset edge detection logic if necessary /* Reset edge detection logic if necessary
*/ */
...@@ -117,7 +117,7 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) ...@@ -117,7 +117,7 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type)
{ {
unsigned int sense = type & IRQ_TYPE_SENSE_MASK; unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
struct spider_pic *pic = spider_virq_to_pic(d->irq); struct spider_pic *pic = spider_virq_to_pic(d->irq);
unsigned int hw = irq_map[d->irq].hwirq; unsigned int hw = irqd_to_hwirq(d);
void __iomem *cfg = spider_get_irq_config(pic, hw); void __iomem *cfg = spider_get_irq_config(pic, hw);
u32 old_mask; u32 old_mask;
u32 ic; u32 ic;
......
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
static void flipper_pic_mask_and_ack(struct irq_data *d) static void flipper_pic_mask_and_ack(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq; u32 mask = 1 << irq;
...@@ -59,7 +59,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d) ...@@ -59,7 +59,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d)
static void flipper_pic_ack(struct irq_data *d) static void flipper_pic_ack(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
/* this is at least needed for RSW */ /* this is at least needed for RSW */
...@@ -68,7 +68,7 @@ static void flipper_pic_ack(struct irq_data *d) ...@@ -68,7 +68,7 @@ static void flipper_pic_ack(struct irq_data *d)
static void flipper_pic_mask(struct irq_data *d) static void flipper_pic_mask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
clrbits32(io_base + FLIPPER_IMR, 1 << irq); clrbits32(io_base + FLIPPER_IMR, 1 << irq);
...@@ -76,7 +76,7 @@ static void flipper_pic_mask(struct irq_data *d) ...@@ -76,7 +76,7 @@ static void flipper_pic_mask(struct irq_data *d)
static void flipper_pic_unmask(struct irq_data *d) static void flipper_pic_unmask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
setbits32(io_base + FLIPPER_IMR, 1 << irq); setbits32(io_base + FLIPPER_IMR, 1 << irq);
......
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
static void hlwd_pic_mask_and_ack(struct irq_data *d) static void hlwd_pic_mask_and_ack(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq; u32 mask = 1 << irq;
...@@ -53,7 +53,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d) ...@@ -53,7 +53,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d)
static void hlwd_pic_ack(struct irq_data *d) static void hlwd_pic_ack(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
...@@ -61,7 +61,7 @@ static void hlwd_pic_ack(struct irq_data *d) ...@@ -61,7 +61,7 @@ static void hlwd_pic_ack(struct irq_data *d)
static void hlwd_pic_mask(struct irq_data *d) static void hlwd_pic_mask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
...@@ -69,7 +69,7 @@ static void hlwd_pic_mask(struct irq_data *d) ...@@ -69,7 +69,7 @@ static void hlwd_pic_mask(struct irq_data *d)
static void hlwd_pic_unmask(struct irq_data *d) static void hlwd_pic_unmask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d); void __iomem *io_base = irq_data_get_irq_chip_data(d);
setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
......
...@@ -171,7 +171,7 @@ static void iseries_enable_IRQ(struct irq_data *d) ...@@ -171,7 +171,7 @@ static void iseries_enable_IRQ(struct irq_data *d)
{ {
u32 bus, dev_id, function, mask; u32 bus, dev_id, function, mask;
const u32 sub_bus = 0; const u32 sub_bus = 0;
unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
/* The IRQ has already been locked by the caller */ /* The IRQ has already been locked by the caller */
bus = REAL_IRQ_TO_BUS(rirq); bus = REAL_IRQ_TO_BUS(rirq);
...@@ -188,7 +188,7 @@ static unsigned int iseries_startup_IRQ(struct irq_data *d) ...@@ -188,7 +188,7 @@ static unsigned int iseries_startup_IRQ(struct irq_data *d)
{ {
u32 bus, dev_id, function, mask; u32 bus, dev_id, function, mask;
const u32 sub_bus = 0; const u32 sub_bus = 0;
unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
bus = REAL_IRQ_TO_BUS(rirq); bus = REAL_IRQ_TO_BUS(rirq);
function = REAL_IRQ_TO_FUNC(rirq); function = REAL_IRQ_TO_FUNC(rirq);
...@@ -234,7 +234,7 @@ static void iseries_shutdown_IRQ(struct irq_data *d) ...@@ -234,7 +234,7 @@ static void iseries_shutdown_IRQ(struct irq_data *d)
{ {
u32 bus, dev_id, function, mask; u32 bus, dev_id, function, mask;
const u32 sub_bus = 0; const u32 sub_bus = 0;
unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
/* irq should be locked by the caller */ /* irq should be locked by the caller */
bus = REAL_IRQ_TO_BUS(rirq); bus = REAL_IRQ_TO_BUS(rirq);
...@@ -257,7 +257,7 @@ static void iseries_disable_IRQ(struct irq_data *d) ...@@ -257,7 +257,7 @@ static void iseries_disable_IRQ(struct irq_data *d)
{ {
u32 bus, dev_id, function, mask; u32 bus, dev_id, function, mask;
const u32 sub_bus = 0; const u32 sub_bus = 0;
unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
/* The IRQ has already been locked by the caller */ /* The IRQ has already been locked by the caller */
bus = REAL_IRQ_TO_BUS(rirq); bus = REAL_IRQ_TO_BUS(rirq);
...@@ -271,7 +271,7 @@ static void iseries_disable_IRQ(struct irq_data *d) ...@@ -271,7 +271,7 @@ static void iseries_disable_IRQ(struct irq_data *d)
static void iseries_end_IRQ(struct irq_data *d) static void iseries_end_IRQ(struct irq_data *d)
{ {
unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
HvCallPci_eoi(REAL_IRQ_TO_BUS(rirq), REAL_IRQ_TO_SUBBUS(rirq), HvCallPci_eoi(REAL_IRQ_TO_BUS(rirq), REAL_IRQ_TO_SUBBUS(rirq),
(REAL_IRQ_TO_IDSEL(rirq) << 4) + REAL_IRQ_TO_FUNC(rirq)); (REAL_IRQ_TO_IDSEL(rirq) << 4) + REAL_IRQ_TO_FUNC(rirq));
......
...@@ -84,7 +84,7 @@ static void __pmac_retrigger(unsigned int irq_nr) ...@@ -84,7 +84,7 @@ static void __pmac_retrigger(unsigned int irq_nr)
static void pmac_mask_and_ack_irq(struct irq_data *d) static void pmac_mask_and_ack_irq(struct irq_data *d)
{ {
unsigned int src = irq_map[d->irq].hwirq; unsigned int src = irqd_to_hwirq(d);
unsigned long bit = 1UL << (src & 0x1f); unsigned long bit = 1UL << (src & 0x1f);
int i = src >> 5; int i = src >> 5;
unsigned long flags; unsigned long flags;
...@@ -106,7 +106,7 @@ static void pmac_mask_and_ack_irq(struct irq_data *d) ...@@ -106,7 +106,7 @@ static void pmac_mask_and_ack_irq(struct irq_data *d)
static void pmac_ack_irq(struct irq_data *d) static void pmac_ack_irq(struct irq_data *d)
{ {
unsigned int src = irq_map[d->irq].hwirq; unsigned int src = irqd_to_hwirq(d);
unsigned long bit = 1UL << (src & 0x1f); unsigned long bit = 1UL << (src & 0x1f);
int i = src >> 5; int i = src >> 5;
unsigned long flags; unsigned long flags;
...@@ -152,7 +152,7 @@ static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) ...@@ -152,7 +152,7 @@ static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
static unsigned int pmac_startup_irq(struct irq_data *d) static unsigned int pmac_startup_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int src = irq_map[d->irq].hwirq; unsigned int src = irqd_to_hwirq(d);
unsigned long bit = 1UL << (src & 0x1f); unsigned long bit = 1UL << (src & 0x1f);
int i = src >> 5; int i = src >> 5;
...@@ -169,7 +169,7 @@ static unsigned int pmac_startup_irq(struct irq_data *d) ...@@ -169,7 +169,7 @@ static unsigned int pmac_startup_irq(struct irq_data *d)
static void pmac_mask_irq(struct irq_data *d) static void pmac_mask_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int src = irq_map[d->irq].hwirq; unsigned int src = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&pmac_pic_lock, flags); raw_spin_lock_irqsave(&pmac_pic_lock, flags);
__clear_bit(src, ppc_cached_irq_mask); __clear_bit(src, ppc_cached_irq_mask);
...@@ -180,7 +180,7 @@ static void pmac_mask_irq(struct irq_data *d) ...@@ -180,7 +180,7 @@ static void pmac_mask_irq(struct irq_data *d)
static void pmac_unmask_irq(struct irq_data *d) static void pmac_unmask_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
unsigned int src = irq_map[d->irq].hwirq; unsigned int src = irqd_to_hwirq(d);
raw_spin_lock_irqsave(&pmac_pic_lock, flags); raw_spin_lock_irqsave(&pmac_pic_lock, flags);
__set_bit(src, ppc_cached_irq_mask); __set_bit(src, ppc_cached_irq_mask);
...@@ -193,7 +193,7 @@ static int pmac_retrigger(struct irq_data *d) ...@@ -193,7 +193,7 @@ static int pmac_retrigger(struct irq_data *d)
unsigned long flags; unsigned long flags;
raw_spin_lock_irqsave(&pmac_pic_lock, flags); raw_spin_lock_irqsave(&pmac_pic_lock, flags);
__pmac_retrigger(irq_map[d->irq].hwirq); __pmac_retrigger(irqd_to_hwirq(d));
raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
return 1; return 1;
} }
......
...@@ -122,7 +122,7 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id) ...@@ -122,7 +122,7 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id)
status = rtas_call(ras_check_exception_token, 6, 1, NULL, status = rtas_call(ras_check_exception_token, 6, 1, NULL,
RTAS_VECTOR_EXTERNAL_INTERRUPT, RTAS_VECTOR_EXTERNAL_INTERRUPT,
irq_map[irq].hwirq, virq_to_hw(irq),
RTAS_EPOW_WARNING | RTAS_POWERMGM_EVENTS, RTAS_EPOW_WARNING | RTAS_POWERMGM_EVENTS,
critical, __pa(&ras_log_buf), critical, __pa(&ras_log_buf),
rtas_get_error_log_max()); rtas_get_error_log_max());
...@@ -157,7 +157,7 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id) ...@@ -157,7 +157,7 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
status = rtas_call(ras_check_exception_token, 6, 1, NULL, status = rtas_call(ras_check_exception_token, 6, 1, NULL,
RTAS_VECTOR_EXTERNAL_INTERRUPT, RTAS_VECTOR_EXTERNAL_INTERRUPT,
irq_map[irq].hwirq, virq_to_hw(irq),
RTAS_INTERNAL_ERROR, 1 /*Time Critical */, RTAS_INTERNAL_ERROR, 1 /*Time Critical */,
__pa(&ras_log_buf), __pa(&ras_log_buf),
rtas_get_error_log_max()); rtas_get_error_log_max());
......
...@@ -58,21 +58,21 @@ static struct irq_host *cpm_pic_host; ...@@ -58,21 +58,21 @@ static struct irq_host *cpm_pic_host;
static void cpm_mask_irq(struct irq_data *d) static void cpm_mask_irq(struct irq_data *d)
{ {
unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq; unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
} }
static void cpm_unmask_irq(struct irq_data *d) static void cpm_unmask_irq(struct irq_data *d)
{ {
unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq; unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
} }
static void cpm_end_irq(struct irq_data *d) static void cpm_end_irq(struct irq_data *d)
{ {
unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq; unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
} }
...@@ -157,7 +157,7 @@ unsigned int cpm_pic_init(void) ...@@ -157,7 +157,7 @@ unsigned int cpm_pic_init(void)
goto end; goto end;
/* Initialize the CPM interrupt controller. */ /* Initialize the CPM interrupt controller. */
hwirq = (unsigned int)irq_map[sirq].hwirq; hwirq = (unsigned int)virq_to_hw(sirq);
out_be32(&cpic_reg->cpic_cicr, out_be32(&cpic_reg->cpic_cicr,
(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
((hwirq/2) << 13) | CICR_HP_MASK); ((hwirq/2) << 13) | CICR_HP_MASK);
......
...@@ -81,7 +81,7 @@ static const u_char irq_to_siubit[] = { ...@@ -81,7 +81,7 @@ static const u_char irq_to_siubit[] = {
static void cpm2_mask_irq(struct irq_data *d) static void cpm2_mask_irq(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = virq_to_hw(d->irq); unsigned int irq_nr = irqd_to_hwirq(d);
bit = irq_to_siubit[irq_nr]; bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr]; word = irq_to_siureg[irq_nr];
...@@ -93,7 +93,7 @@ static void cpm2_mask_irq(struct irq_data *d) ...@@ -93,7 +93,7 @@ static void cpm2_mask_irq(struct irq_data *d)
static void cpm2_unmask_irq(struct irq_data *d) static void cpm2_unmask_irq(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = virq_to_hw(d->irq); unsigned int irq_nr = irqd_to_hwirq(d);
bit = irq_to_siubit[irq_nr]; bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr]; word = irq_to_siureg[irq_nr];
...@@ -105,7 +105,7 @@ static void cpm2_unmask_irq(struct irq_data *d) ...@@ -105,7 +105,7 @@ static void cpm2_unmask_irq(struct irq_data *d)
static void cpm2_ack(struct irq_data *d) static void cpm2_ack(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = virq_to_hw(d->irq); unsigned int irq_nr = irqd_to_hwirq(d);
bit = irq_to_siubit[irq_nr]; bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr]; word = irq_to_siureg[irq_nr];
...@@ -116,7 +116,7 @@ static void cpm2_ack(struct irq_data *d) ...@@ -116,7 +116,7 @@ static void cpm2_ack(struct irq_data *d)
static void cpm2_end_irq(struct irq_data *d) static void cpm2_end_irq(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = virq_to_hw(d->irq); unsigned int irq_nr = irqd_to_hwirq(d);
bit = irq_to_siubit[irq_nr]; bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr]; word = irq_to_siureg[irq_nr];
...@@ -133,7 +133,7 @@ static void cpm2_end_irq(struct irq_data *d) ...@@ -133,7 +133,7 @@ static void cpm2_end_irq(struct irq_data *d)
static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
{ {
unsigned int src = virq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned int vold, vnew, edibit; unsigned int vold, vnew, edibit;
/* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
......
...@@ -521,12 +521,10 @@ static inline struct ipic * ipic_from_irq(unsigned int virq) ...@@ -521,12 +521,10 @@ static inline struct ipic * ipic_from_irq(unsigned int virq)
return primary_ipic; return primary_ipic;
} }
#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
static void ipic_unmask_irq(struct irq_data *d) static void ipic_unmask_irq(struct irq_data *d)
{ {
struct ipic *ipic = ipic_from_irq(d->irq); struct ipic *ipic = ipic_from_irq(d->irq);
unsigned int src = ipic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 temp; u32 temp;
...@@ -542,7 +540,7 @@ static void ipic_unmask_irq(struct irq_data *d) ...@@ -542,7 +540,7 @@ static void ipic_unmask_irq(struct irq_data *d)
static void ipic_mask_irq(struct irq_data *d) static void ipic_mask_irq(struct irq_data *d)
{ {
struct ipic *ipic = ipic_from_irq(d->irq); struct ipic *ipic = ipic_from_irq(d->irq);
unsigned int src = ipic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 temp; u32 temp;
...@@ -562,7 +560,7 @@ static void ipic_mask_irq(struct irq_data *d) ...@@ -562,7 +560,7 @@ static void ipic_mask_irq(struct irq_data *d)
static void ipic_ack_irq(struct irq_data *d) static void ipic_ack_irq(struct irq_data *d)
{ {
struct ipic *ipic = ipic_from_irq(d->irq); struct ipic *ipic = ipic_from_irq(d->irq);
unsigned int src = ipic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 temp; u32 temp;
...@@ -581,7 +579,7 @@ static void ipic_ack_irq(struct irq_data *d) ...@@ -581,7 +579,7 @@ static void ipic_ack_irq(struct irq_data *d)
static void ipic_mask_irq_and_ack(struct irq_data *d) static void ipic_mask_irq_and_ack(struct irq_data *d)
{ {
struct ipic *ipic = ipic_from_irq(d->irq); struct ipic *ipic = ipic_from_irq(d->irq);
unsigned int src = ipic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 temp; u32 temp;
...@@ -604,7 +602,7 @@ static void ipic_mask_irq_and_ack(struct irq_data *d) ...@@ -604,7 +602,7 @@ static void ipic_mask_irq_and_ack(struct irq_data *d)
static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
{ {
struct ipic *ipic = ipic_from_irq(d->irq); struct ipic *ipic = ipic_from_irq(d->irq);
unsigned int src = ipic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned int vold, vnew, edibit; unsigned int vold, vnew, edibit;
if (flow_type == IRQ_TYPE_NONE) if (flow_type == IRQ_TYPE_NONE)
...@@ -793,7 +791,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags) ...@@ -793,7 +791,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
int ipic_set_priority(unsigned int virq, unsigned int priority) int ipic_set_priority(unsigned int virq, unsigned int priority)
{ {
struct ipic *ipic = ipic_from_irq(virq); struct ipic *ipic = ipic_from_irq(virq);
unsigned int src = ipic_irq_to_hw(virq); unsigned int src = virq_to_hw(virq);
u32 temp; u32 temp;
if (priority > 7) if (priority > 7)
...@@ -821,7 +819,7 @@ int ipic_set_priority(unsigned int virq, unsigned int priority) ...@@ -821,7 +819,7 @@ int ipic_set_priority(unsigned int virq, unsigned int priority)
void ipic_set_highest_priority(unsigned int virq) void ipic_set_highest_priority(unsigned int virq)
{ {
struct ipic *ipic = ipic_from_irq(virq); struct ipic *ipic = ipic_from_irq(virq);
unsigned int src = ipic_irq_to_hw(virq); unsigned int src = virq_to_hw(virq);
u32 temp; u32 temp;
temp = ipic_read(ipic->regs, IPIC_SICFR); temp = ipic_read(ipic->regs, IPIC_SICFR);
......
...@@ -28,7 +28,7 @@ int cpm_get_irq(struct pt_regs *regs); ...@@ -28,7 +28,7 @@ int cpm_get_irq(struct pt_regs *regs);
static void mpc8xx_unmask_irq(struct irq_data *d) static void mpc8xx_unmask_irq(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
bit = irq_nr & 0x1f; bit = irq_nr & 0x1f;
word = irq_nr >> 5; word = irq_nr >> 5;
...@@ -40,7 +40,7 @@ static void mpc8xx_unmask_irq(struct irq_data *d) ...@@ -40,7 +40,7 @@ static void mpc8xx_unmask_irq(struct irq_data *d)
static void mpc8xx_mask_irq(struct irq_data *d) static void mpc8xx_mask_irq(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
bit = irq_nr & 0x1f; bit = irq_nr & 0x1f;
word = irq_nr >> 5; word = irq_nr >> 5;
...@@ -52,7 +52,7 @@ static void mpc8xx_mask_irq(struct irq_data *d) ...@@ -52,7 +52,7 @@ static void mpc8xx_mask_irq(struct irq_data *d)
static void mpc8xx_ack(struct irq_data *d) static void mpc8xx_ack(struct irq_data *d)
{ {
int bit; int bit;
unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
bit = irq_nr & 0x1f; bit = irq_nr & 0x1f;
out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
...@@ -61,7 +61,7 @@ static void mpc8xx_ack(struct irq_data *d) ...@@ -61,7 +61,7 @@ static void mpc8xx_ack(struct irq_data *d)
static void mpc8xx_end_irq(struct irq_data *d) static void mpc8xx_end_irq(struct irq_data *d)
{ {
int bit, word; int bit, word;
unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
bit = irq_nr & 0x1f; bit = irq_nr & 0x1f;
word = irq_nr >> 5; word = irq_nr >> 5;
...@@ -73,7 +73,7 @@ static void mpc8xx_end_irq(struct irq_data *d) ...@@ -73,7 +73,7 @@ static void mpc8xx_end_irq(struct irq_data *d)
static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
{ {
if (flow_type & IRQ_TYPE_EDGE_FALLING) { if (flow_type & IRQ_TYPE_EDGE_FALLING) {
irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
unsigned int siel = in_be32(&siu_reg->sc_siel); unsigned int siel = in_be32(&siu_reg->sc_siel);
/* only external IRQ senses are programmable */ /* only external IRQ senses are programmable */
......
...@@ -163,7 +163,7 @@ static void mpc8xxx_irq_unmask(struct irq_data *d) ...@@ -163,7 +163,7 @@ static void mpc8xxx_irq_unmask(struct irq_data *d)
spin_lock_irqsave(&mpc8xxx_gc->lock, flags); spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq))); setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
} }
...@@ -176,7 +176,7 @@ static void mpc8xxx_irq_mask(struct irq_data *d) ...@@ -176,7 +176,7 @@ static void mpc8xxx_irq_mask(struct irq_data *d)
spin_lock_irqsave(&mpc8xxx_gc->lock, flags); spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq))); clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
} }
...@@ -186,7 +186,7 @@ static void mpc8xxx_irq_ack(struct irq_data *d) ...@@ -186,7 +186,7 @@ static void mpc8xxx_irq_ack(struct irq_data *d)
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(d->irq))); out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
} }
static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
...@@ -199,14 +199,14 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -199,14 +199,14 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_FALLING:
spin_lock_irqsave(&mpc8xxx_gc->lock, flags); spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
setbits32(mm->regs + GPIO_ICR, setbits32(mm->regs + GPIO_ICR,
mpc8xxx_gpio2mask(virq_to_hw(d->irq))); mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break; break;
case IRQ_TYPE_EDGE_BOTH: case IRQ_TYPE_EDGE_BOTH:
spin_lock_irqsave(&mpc8xxx_gc->lock, flags); spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
clrbits32(mm->regs + GPIO_ICR, clrbits32(mm->regs + GPIO_ICR,
mpc8xxx_gpio2mask(virq_to_hw(d->irq))); mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
break; break;
...@@ -221,7 +221,7 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -221,7 +221,7 @@ static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{ {
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
unsigned long gpio = virq_to_hw(d->irq); unsigned long gpio = irqd_to_hwirq(d);
void __iomem *reg; void __iomem *reg;
unsigned int shift; unsigned int shift;
unsigned long flags; unsigned long flags;
......
...@@ -607,8 +607,6 @@ static int irq_choose_cpu(const struct cpumask *mask) ...@@ -607,8 +607,6 @@ static int irq_choose_cpu(const struct cpumask *mask)
} }
#endif #endif
#define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
/* Find an mpic associated with a given linux interrupt */ /* Find an mpic associated with a given linux interrupt */
static struct mpic *mpic_find(unsigned int irq) static struct mpic *mpic_find(unsigned int irq)
{ {
...@@ -621,7 +619,7 @@ static struct mpic *mpic_find(unsigned int irq) ...@@ -621,7 +619,7 @@ static struct mpic *mpic_find(unsigned int irq)
/* Determine if the linux irq is an IPI */ /* Determine if the linux irq is an IPI */
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq) static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
{ {
unsigned int src = mpic_irq_to_hw(irq); unsigned int src = virq_to_hw(irq);
return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
} }
...@@ -674,7 +672,7 @@ void mpic_unmask_irq(struct irq_data *d) ...@@ -674,7 +672,7 @@ void mpic_unmask_irq(struct irq_data *d)
{ {
unsigned int loops = 100000; unsigned int loops = 100000;
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
...@@ -695,7 +693,7 @@ void mpic_mask_irq(struct irq_data *d) ...@@ -695,7 +693,7 @@ void mpic_mask_irq(struct irq_data *d)
{ {
unsigned int loops = 100000; unsigned int loops = 100000;
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
...@@ -733,7 +731,7 @@ void mpic_end_irq(struct irq_data *d) ...@@ -733,7 +731,7 @@ void mpic_end_irq(struct irq_data *d)
static void mpic_unmask_ht_irq(struct irq_data *d) static void mpic_unmask_ht_irq(struct irq_data *d)
{ {
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
mpic_unmask_irq(d); mpic_unmask_irq(d);
...@@ -744,7 +742,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d) ...@@ -744,7 +742,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d)
static unsigned int mpic_startup_ht_irq(struct irq_data *d) static unsigned int mpic_startup_ht_irq(struct irq_data *d)
{ {
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
mpic_unmask_irq(d); mpic_unmask_irq(d);
mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
...@@ -755,7 +753,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d) ...@@ -755,7 +753,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d)
static void mpic_shutdown_ht_irq(struct irq_data *d) static void mpic_shutdown_ht_irq(struct irq_data *d)
{ {
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
mpic_shutdown_ht_interrupt(mpic, src); mpic_shutdown_ht_interrupt(mpic, src);
mpic_mask_irq(d); mpic_mask_irq(d);
...@@ -764,7 +762,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d) ...@@ -764,7 +762,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d)
static void mpic_end_ht_irq(struct irq_data *d) static void mpic_end_ht_irq(struct irq_data *d)
{ {
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
#ifdef DEBUG_IRQ #ifdef DEBUG_IRQ
DBG("%s: end_irq: %d\n", mpic->name, d->irq); DBG("%s: end_irq: %d\n", mpic->name, d->irq);
...@@ -785,7 +783,7 @@ static void mpic_end_ht_irq(struct irq_data *d) ...@@ -785,7 +783,7 @@ static void mpic_end_ht_irq(struct irq_data *d)
static void mpic_unmask_ipi(struct irq_data *d) static void mpic_unmask_ipi(struct irq_data *d)
{ {
struct mpic *mpic = mpic_from_ipi(d); struct mpic *mpic = mpic_from_ipi(d);
unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0]; unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
...@@ -816,7 +814,7 @@ int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, ...@@ -816,7 +814,7 @@ int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
bool force) bool force)
{ {
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
if (mpic->flags & MPIC_SINGLE_DEST_CPU) { if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
int cpuid = irq_choose_cpu(cpumask); int cpuid = irq_choose_cpu(cpumask);
...@@ -862,7 +860,7 @@ static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) ...@@ -862,7 +860,7 @@ static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
{ {
struct mpic *mpic = mpic_from_irq_data(d); struct mpic *mpic = mpic_from_irq_data(d);
unsigned int src = mpic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned int vecpri, vold, vnew; unsigned int vecpri, vold, vnew;
DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
...@@ -898,7 +896,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) ...@@ -898,7 +896,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
void mpic_set_vector(unsigned int virq, unsigned int vector) void mpic_set_vector(unsigned int virq, unsigned int vector)
{ {
struct mpic *mpic = mpic_from_irq(virq); struct mpic *mpic = mpic_from_irq(virq);
unsigned int src = mpic_irq_to_hw(virq); unsigned int src = virq_to_hw(virq);
unsigned int vecpri; unsigned int vecpri;
DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
...@@ -916,7 +914,7 @@ void mpic_set_vector(unsigned int virq, unsigned int vector) ...@@ -916,7 +914,7 @@ void mpic_set_vector(unsigned int virq, unsigned int vector)
void mpic_set_destination(unsigned int virq, unsigned int cpuid) void mpic_set_destination(unsigned int virq, unsigned int cpuid)
{ {
struct mpic *mpic = mpic_from_irq(virq); struct mpic *mpic = mpic_from_irq(virq);
unsigned int src = mpic_irq_to_hw(virq); unsigned int src = virq_to_hw(virq);
DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
mpic, virq, src, cpuid); mpic, virq, src, cpuid);
...@@ -1427,7 +1425,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable) ...@@ -1427,7 +1425,7 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable)
void mpic_irq_set_priority(unsigned int irq, unsigned int pri) void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
{ {
struct mpic *mpic = mpic_find(irq); struct mpic *mpic = mpic_find(irq);
unsigned int src = mpic_irq_to_hw(irq); unsigned int src = virq_to_hw(irq);
unsigned long flags; unsigned long flags;
u32 reg; u32 reg;
......
...@@ -78,7 +78,7 @@ static struct irq_host *mv64x60_irq_host; ...@@ -78,7 +78,7 @@ static struct irq_host *mv64x60_irq_host;
static void mv64x60_mask_low(struct irq_data *d) static void mv64x60_mask_low(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
...@@ -91,7 +91,7 @@ static void mv64x60_mask_low(struct irq_data *d) ...@@ -91,7 +91,7 @@ static void mv64x60_mask_low(struct irq_data *d)
static void mv64x60_unmask_low(struct irq_data *d) static void mv64x60_unmask_low(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
...@@ -115,7 +115,7 @@ static struct irq_chip mv64x60_chip_low = { ...@@ -115,7 +115,7 @@ static struct irq_chip mv64x60_chip_low = {
static void mv64x60_mask_high(struct irq_data *d) static void mv64x60_mask_high(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
...@@ -128,7 +128,7 @@ static void mv64x60_mask_high(struct irq_data *d) ...@@ -128,7 +128,7 @@ static void mv64x60_mask_high(struct irq_data *d)
static void mv64x60_unmask_high(struct irq_data *d) static void mv64x60_unmask_high(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
...@@ -152,7 +152,7 @@ static struct irq_chip mv64x60_chip_high = { ...@@ -152,7 +152,7 @@ static struct irq_chip mv64x60_chip_high = {
static void mv64x60_mask_gpp(struct irq_data *d) static void mv64x60_mask_gpp(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
...@@ -165,7 +165,7 @@ static void mv64x60_mask_gpp(struct irq_data *d) ...@@ -165,7 +165,7 @@ static void mv64x60_mask_gpp(struct irq_data *d)
static void mv64x60_mask_ack_gpp(struct irq_data *d) static void mv64x60_mask_ack_gpp(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
...@@ -180,7 +180,7 @@ static void mv64x60_mask_ack_gpp(struct irq_data *d) ...@@ -180,7 +180,7 @@ static void mv64x60_mask_ack_gpp(struct irq_data *d)
static void mv64x60_unmask_gpp(struct irq_data *d) static void mv64x60_unmask_gpp(struct irq_data *d)
{ {
int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&mv64x60_lock, flags); spin_lock_irqsave(&mv64x60_lock, flags);
......
...@@ -197,12 +197,10 @@ static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) ...@@ -197,12 +197,10 @@ static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
return irq_data_get_irq_chip_data(d); return irq_data_get_irq_chip_data(d);
} }
#define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
static void qe_ic_unmask_irq(struct irq_data *d) static void qe_ic_unmask_irq(struct irq_data *d)
{ {
struct qe_ic *qe_ic = qe_ic_from_irq_data(d); struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
unsigned int src = virq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 temp; u32 temp;
...@@ -218,7 +216,7 @@ static void qe_ic_unmask_irq(struct irq_data *d) ...@@ -218,7 +216,7 @@ static void qe_ic_unmask_irq(struct irq_data *d)
static void qe_ic_mask_irq(struct irq_data *d) static void qe_ic_mask_irq(struct irq_data *d)
{ {
struct qe_ic *qe_ic = qe_ic_from_irq_data(d); struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
unsigned int src = virq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 temp; u32 temp;
......
...@@ -41,8 +41,6 @@ ...@@ -41,8 +41,6 @@
#define UIC_VR 0x7 #define UIC_VR 0x7
#define UIC_VCR 0x8 #define UIC_VCR 0x8
#define uic_irq_to_hw(virq) (irq_map[virq].hwirq)
struct uic *primary_uic; struct uic *primary_uic;
struct uic { struct uic {
...@@ -58,7 +56,7 @@ struct uic { ...@@ -58,7 +56,7 @@ struct uic {
static void uic_unmask_irq(struct irq_data *d) static void uic_unmask_irq(struct irq_data *d)
{ {
struct uic *uic = irq_data_get_irq_chip_data(d); struct uic *uic = irq_data_get_irq_chip_data(d);
unsigned int src = uic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 er, sr; u32 er, sr;
...@@ -76,7 +74,7 @@ static void uic_unmask_irq(struct irq_data *d) ...@@ -76,7 +74,7 @@ static void uic_unmask_irq(struct irq_data *d)
static void uic_mask_irq(struct irq_data *d) static void uic_mask_irq(struct irq_data *d)
{ {
struct uic *uic = irq_data_get_irq_chip_data(d); struct uic *uic = irq_data_get_irq_chip_data(d);
unsigned int src = uic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 er; u32 er;
...@@ -90,7 +88,7 @@ static void uic_mask_irq(struct irq_data *d) ...@@ -90,7 +88,7 @@ static void uic_mask_irq(struct irq_data *d)
static void uic_ack_irq(struct irq_data *d) static void uic_ack_irq(struct irq_data *d)
{ {
struct uic *uic = irq_data_get_irq_chip_data(d); struct uic *uic = irq_data_get_irq_chip_data(d);
unsigned int src = uic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&uic->lock, flags); spin_lock_irqsave(&uic->lock, flags);
...@@ -101,7 +99,7 @@ static void uic_ack_irq(struct irq_data *d) ...@@ -101,7 +99,7 @@ static void uic_ack_irq(struct irq_data *d)
static void uic_mask_ack_irq(struct irq_data *d) static void uic_mask_ack_irq(struct irq_data *d)
{ {
struct uic *uic = irq_data_get_irq_chip_data(d); struct uic *uic = irq_data_get_irq_chip_data(d);
unsigned int src = uic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
u32 er, sr; u32 er, sr;
...@@ -126,7 +124,7 @@ static void uic_mask_ack_irq(struct irq_data *d) ...@@ -126,7 +124,7 @@ static void uic_mask_ack_irq(struct irq_data *d)
static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
{ {
struct uic *uic = irq_data_get_irq_chip_data(d); struct uic *uic = irq_data_get_irq_chip_data(d);
unsigned int src = uic_irq_to_hw(d->irq); unsigned int src = irqd_to_hwirq(d);
unsigned long flags; unsigned long flags;
int trigger, polarity; int trigger, polarity;
u32 tr, pr, mask; u32 tr, pr, mask;
......
...@@ -58,7 +58,7 @@ static inline void icp_hv_set_qirr(int n_cpu , u8 value) ...@@ -58,7 +58,7 @@ static inline void icp_hv_set_qirr(int n_cpu , u8 value)
static void icp_hv_eoi(struct irq_data *d) static void icp_hv_eoi(struct irq_data *d)
{ {
unsigned int hw_irq = (unsigned int)irq_data_to_hw(d); unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
iosync(); iosync();
icp_hv_set_xirr((xics_pop_cppr() << 24) | hw_irq); icp_hv_set_xirr((xics_pop_cppr() << 24) | hw_irq);
......
...@@ -80,7 +80,7 @@ static void icp_native_set_cpu_priority(unsigned char cppr) ...@@ -80,7 +80,7 @@ static void icp_native_set_cpu_priority(unsigned char cppr)
static void icp_native_eoi(struct irq_data *d) static void icp_native_eoi(struct irq_data *d)
{ {
unsigned int hw_irq = (unsigned int)irq_data_to_hw(d); unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
iosync(); iosync();
icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq); icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq);
......
...@@ -38,7 +38,7 @@ static struct ics ics_rtas = { ...@@ -38,7 +38,7 @@ static struct ics ics_rtas = {
static void ics_rtas_unmask_irq(struct irq_data *d) static void ics_rtas_unmask_irq(struct irq_data *d)
{ {
unsigned int hw_irq = (unsigned int)irq_data_to_hw(d); unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
int call_status; int call_status;
int server; int server;
...@@ -109,7 +109,7 @@ static void ics_rtas_mask_real_irq(unsigned int hw_irq) ...@@ -109,7 +109,7 @@ static void ics_rtas_mask_real_irq(unsigned int hw_irq)
static void ics_rtas_mask_irq(struct irq_data *d) static void ics_rtas_mask_irq(struct irq_data *d)
{ {
unsigned int hw_irq = (unsigned int)irq_data_to_hw(d); unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
pr_devel("xics: mask virq %d [hw 0x%x]\n", d->irq, hw_irq); pr_devel("xics: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
...@@ -122,7 +122,7 @@ static int ics_rtas_set_affinity(struct irq_data *d, ...@@ -122,7 +122,7 @@ static int ics_rtas_set_affinity(struct irq_data *d,
const struct cpumask *cpumask, const struct cpumask *cpumask,
bool force) bool force)
{ {
unsigned int hw_irq = (unsigned int)irq_data_to_hw(d); unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
int status; int status;
int xics_status[2]; int xics_status[2];
int irq_server; int irq_server;
...@@ -171,7 +171,7 @@ static struct irq_chip ics_rtas_irq_chip = { ...@@ -171,7 +171,7 @@ static struct irq_chip ics_rtas_irq_chip = {
static int ics_rtas_map(struct ics *ics, unsigned int virq) static int ics_rtas_map(struct ics *ics, unsigned int virq)
{ {
unsigned int hw_irq = (unsigned int)irq_map[virq].hwirq; unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
int status[2]; int status[2];
int rc; int rc;
......
...@@ -240,9 +240,9 @@ void xics_migrate_irqs_away(void) ...@@ -240,9 +240,9 @@ void xics_migrate_irqs_away(void)
/* We can't set affinity on ISA interrupts */ /* We can't set affinity on ISA interrupts */
if (virq < NUM_ISA_INTERRUPTS) if (virq < NUM_ISA_INTERRUPTS)
continue; continue;
if (irq_map[virq].host != xics_host) if (virq_to_host(virq) != xics_host)
continue; continue;
irq = (unsigned int)irq_map[virq].hwirq; irq = (unsigned int)virq_to_hw(virq);
/* We need to get IPIs still. */ /* We need to get IPIs still. */
if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
continue; continue;
......
...@@ -71,7 +71,7 @@ static unsigned char xilinx_intc_map_senses[] = { ...@@ -71,7 +71,7 @@ static unsigned char xilinx_intc_map_senses[] = {
*/ */
static void xilinx_intc_mask(struct irq_data *d) static void xilinx_intc_mask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void * regs = irq_data_get_irq_chip_data(d); void * regs = irq_data_get_irq_chip_data(d);
pr_debug("mask: %d\n", irq); pr_debug("mask: %d\n", irq);
out_be32(regs + XINTC_CIE, 1 << irq); out_be32(regs + XINTC_CIE, 1 << irq);
...@@ -87,7 +87,7 @@ static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -87,7 +87,7 @@ static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
*/ */
static void xilinx_intc_level_unmask(struct irq_data *d) static void xilinx_intc_level_unmask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void * regs = irq_data_get_irq_chip_data(d); void * regs = irq_data_get_irq_chip_data(d);
pr_debug("unmask: %d\n", irq); pr_debug("unmask: %d\n", irq);
out_be32(regs + XINTC_SIE, 1 << irq); out_be32(regs + XINTC_SIE, 1 << irq);
...@@ -112,7 +112,7 @@ static struct irq_chip xilinx_intc_level_irqchip = { ...@@ -112,7 +112,7 @@ static struct irq_chip xilinx_intc_level_irqchip = {
*/ */
static void xilinx_intc_edge_unmask(struct irq_data *d) static void xilinx_intc_edge_unmask(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void *regs = irq_data_get_irq_chip_data(d); void *regs = irq_data_get_irq_chip_data(d);
pr_debug("unmask: %d\n", irq); pr_debug("unmask: %d\n", irq);
out_be32(regs + XINTC_SIE, 1 << irq); out_be32(regs + XINTC_SIE, 1 << irq);
...@@ -120,7 +120,7 @@ static void xilinx_intc_edge_unmask(struct irq_data *d) ...@@ -120,7 +120,7 @@ static void xilinx_intc_edge_unmask(struct irq_data *d)
static void xilinx_intc_edge_ack(struct irq_data *d) static void xilinx_intc_edge_ack(struct irq_data *d)
{ {
int irq = virq_to_hw(d->irq); int irq = irqd_to_hwirq(d);
void * regs = irq_data_get_irq_chip_data(d); void * regs = irq_data_get_irq_chip_data(d);
pr_debug("ack: %d\n", irq); pr_debug("ack: %d\n", irq);
out_be32(regs + XINTC_IAR, 1 << irq); out_be32(regs + XINTC_IAR, 1 << irq);
......
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