Merge branch 'davinci-for-linus' of...

Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci

* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci:
  davinci: dm646x EVM: Specify reserved EDMA channel/slots
  davinci: da8xx/omapl EVM: Specify reserved channels/slots
  davinci: support for EDMA resource sharing
  davinci: edma: provide ability to detect insufficient CC info data
  davinci: da8xx: sparse cleanup: remove duplicate entries in irq priorities
  davinci: DM365: fixed second serial port
  Davinci: tnetv107x evm board initial support
  Davinci: tnetv107x initial gpio support
  Davinci: tnetv107x soc support
  Davinci: tnetv107x decompresser uart definitions
  Davinci: generalized debug macros

arch/arm/mach-davinci/Kconfig

@@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365
 	select AINTC
 	select ARCH_DAVINCI_DMx
 
+config ARCH_DAVINCI_TNETV107X
+	select CPU_V6
+	select CP_INTC
+	bool "TNETV107X based system"
+
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
@@ -173,6 +178,13 @@ config DA850_UI_RMII
 
 endchoice
 
+config MACH_TNETV107X
+	bool "TI TNETV107X Reference Platform"
+	default ARCH_DAVINCI_TNETV107X
+	depends on ARCH_DAVINCI_TNETV107X
+	help
+	  Say Y here to select the TI TNETV107X Evaluation Module.
+
 config DAVINCI_MUX
 	bool "DAVINCI multiplexing support"
 	depends on ARCH_DAVINCI

arch/arm/mach-davinci/Makefile

@@ -16,6 +16,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
+obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += gpio-tnetv107x.o
 
 obj-$(CONFIG_AINTC)			+= irq.o
 obj-$(CONFIG_CP_INTC)			+= cp_intc.o
@@ -30,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
+obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o

arch/arm/mach-davinci/board-da830-evm.c

@@ -494,12 +494,42 @@ static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
 	.bus_delay	= 0,	/* usec */
 };
 
+/*
+ * The following EDMA channels/slots are not being used by drivers (for
+ * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
+ * they are being reserved for codecs on the DSP side.
+ */
+static const s16 da830_dma_rsv_chans[][2] = {
+	/* (offset, number) */
+	{ 8,  2},
+	{12,  2},
+	{24,  4},
+	{30,  2},
+	{-1, -1}
+};
+
+static const s16 da830_dma_rsv_slots[][2] = {
+	/* (offset, number) */
+	{ 8,  2},
+	{12,  2},
+	{24,  4},
+	{30, 26},
+	{-1, -1}
+};
+
+static struct edma_rsv_info da830_edma_rsv[] = {
+	{
+		.rsv_chans	= da830_dma_rsv_chans,
+		.rsv_slots	= da830_dma_rsv_slots,
+	},
+};
+
 static __init void da830_evm_init(void)
 {
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	int ret;
 
-	ret = da8xx_register_edma();
+	ret = da830_register_edma(da830_edma_rsv);
 	if (ret)
 		pr_warning("da830_evm_init: edma registration failed: %d\n",
 				ret);

arch/arm/mach-davinci/board-da850-evm.c

@@ -637,6 +637,56 @@ static int __init da850_evm_config_emac(void)
 }
 device_initcall(da850_evm_config_emac);
 
+/*
+ * The following EDMA channels/slots are not being used by drivers (for
+ * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
+ * they are being reserved for codecs on the DSP side.
+ */
+static const s16 da850_dma0_rsv_chans[][2] = {
+	/* (offset, number) */
+	{ 8,  6},
+	{24,  4},
+	{30,  2},
+	{-1, -1}
+};
+
+static const s16 da850_dma0_rsv_slots[][2] = {
+	/* (offset, number) */
+	{ 8,  6},
+	{24,  4},
+	{30, 50},
+	{-1, -1}
+};
+
+static const s16 da850_dma1_rsv_chans[][2] = {
+	/* (offset, number) */
+	{ 0, 28},
+	{30,  2},
+	{-1, -1}
+};
+
+static const s16 da850_dma1_rsv_slots[][2] = {
+	/* (offset, number) */
+	{ 0, 28},
+	{30, 90},
+	{-1, -1}
+};
+
+static struct edma_rsv_info da850_edma_cc0_rsv = {
+	.rsv_chans	= da850_dma0_rsv_chans,
+	.rsv_slots	= da850_dma0_rsv_slots,
+};
+
+static struct edma_rsv_info da850_edma_cc1_rsv = {
+	.rsv_chans	= da850_dma1_rsv_chans,
+	.rsv_slots	= da850_dma1_rsv_slots,
+};
+
+static struct edma_rsv_info *da850_edma_rsv[2] = {
+	&da850_edma_cc0_rsv,
+	&da850_edma_cc1_rsv,
+};
+
 static __init void da850_evm_init(void)
 {
 	int ret;
@@ -646,7 +696,7 @@ static __init void da850_evm_init(void)
 		pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
 				ret);
 
-	ret = da8xx_register_edma();
+	ret = da850_register_edma(da850_edma_rsv);
 	if (ret)
 		pr_warning("da850_evm_init: edma registration failed: %d\n",
 				ret);

arch/arm/mach-davinci/board-dm646x-evm.c

@@ -721,6 +721,39 @@ static struct davinci_uart_config uart_config __initdata = {
 #define DM646X_EVM_PHY_MASK		(0x2)
 #define DM646X_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */
 
+/*
+ * The following EDMA channels/slots are not being used by drivers (for
+ * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
+ * reserved for codecs on the DSP side.
+ */
+static const s16 dm646x_dma_rsv_chans[][2] = {
+	/* (offset, number) */
+	{ 0,  4},
+	{13,  3},
+	{24,  4},
+	{30,  2},
+	{54,  3},
+	{-1, -1}
+};
+
+static const s16 dm646x_dma_rsv_slots[][2] = {
+	/* (offset, number) */
+	{ 0,  4},
+	{13,  3},
+	{24,  4},
+	{30,  2},
+	{54,  3},
+	{128, 384},
+	{-1, -1}
+};
+
+static struct edma_rsv_info dm646x_edma_rsv[] = {
+	{
+		.rsv_chans	= dm646x_dma_rsv_chans,
+		.rsv_slots	= dm646x_dma_rsv_slots,
+	},
+};
+
 static __init void evm_init(void)
 {
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -732,6 +765,8 @@ static __init void evm_init(void)
 
 	platform_device_register(&davinci_nand_device);
 
+	dm646x_init_edma(dm646x_edma_rsv);
+
 	if (HAS_ATA)
 		davinci_init_ide();
 

arch/arm/mach-davinci/board-tnetv107x-evm.c

+/*
+ * Texas Instruments TNETV107X EVM Board Support
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/ratelimit.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/mux.h>
+#include <mach/cp_intc.h>
+#include <mach/tnetv107x.h>
+
+#define EVM_MMC_WP_GPIO		21
+#define EVM_MMC_CD_GPIO		24
+
+static int initialize_gpio(int gpio, char *desc)
+{
+	int ret;
+
+	ret = gpio_request(gpio, desc);
+	if (ret < 0) {
+		pr_err_ratelimited("cannot open %s gpio\n", desc);
+		return -ENOSYS;
+	}
+	gpio_direction_input(gpio);
+	return gpio;
+}
+
+static int mmc_get_cd(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 0 : 1;
+}
+
+static int mmc_get_ro(int index)
+{
+	static int gpio;
+
+	if (!gpio)
+		gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
+
+	if (gpio < 0)
+		return gpio;
+
+	return gpio_get_value(gpio) ? 1 : 0;
+}
+
+static struct davinci_mmc_config mmc_config = {
+	.get_cd		= mmc_get_cd,
+	.get_ro		= mmc_get_ro,
+	.wires		= 4,
+	.max_freq	= 50000000,
+	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.version	= MMC_CTLR_VERSION_1,
+};
+
+static const short sdio1_pins[] __initdata = {
+	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
+	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
+	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
+	TNETV107X_GPIO21,		TNETV107X_GPIO24,
+	-1
+};
+
+static const short uart1_pins[] __initdata = {
+	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
+	-1
+};
+
+static struct mtd_partition nand_partitions[] = {
+	/* bootloader (U-Boot, etc) in first 12 sectors */
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= (12*SZ_128K),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* bootloader params in the next sector */
+	{
+		.name		= "params",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	/* kernel */
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= SZ_4M,
+		.mask_flags	= 0,
+	},
+	/* file system */
+	{
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= MTDPART_SIZ_FULL,
+		.mask_flags	= 0,
+	}
+};
+
+static struct davinci_nand_pdata nand_config = {
+	.mask_cle	= 0x4000,
+	.mask_ale	= 0x2000,
+	.parts		= nand_partitions,
+	.nr_parts	= ARRAY_SIZE(nand_partitions),
+	.ecc_mode	= NAND_ECC_HW,
+	.options	= NAND_USE_FLASH_BBT,
+	.ecc_bits	= 1,
+};
+
+static struct davinci_uart_config serial_config __initconst = {
+	.enabled_uarts	= BIT(1),
+};
+
+static struct tnetv107x_device_info evm_device_info __initconst = {
+	.serial_config		= &serial_config,
+	.mmc_config[1]		= &mmc_config,	/* controller 1 */
+	.nand_config[0]		= &nand_config,	/* chip select 0 */
+};
+
+static __init void tnetv107x_evm_board_init(void)
+{
+	davinci_cfg_reg_list(sdio1_pins);
+	davinci_cfg_reg_list(uart1_pins);
+
+	tnetv107x_devices_init(&evm_device_info);
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init tnetv107x_evm_console_init(void)
+{
+	return add_preferred_console("ttyS", 0, "115200");
+}
+console_initcall(tnetv107x_evm_console_init);
+#endif
+
+MACHINE_START(TNETV107X, "TNETV107X EVM")
+	.phys_io	= TNETV107X_IO_BASE,
+	.io_pg_offst	= (TNETV107X_IO_VIRT >> 18) & 0xfffc,
+	.boot_params	= (TNETV107X_DDR_BASE + 0x100),
+	.map_io		= tnetv107x_init,
+	.init_irq	= cp_intc_init,
+	.timer		= &davinci_timer,
+	.init_machine	= tnetv107x_evm_board_init,
+MACHINE_END

arch/arm/mach-davinci/da830.c

@@ -1024,7 +1024,6 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
 	[IRQ_DA8XX_EVTOUT4]		= 7,
 	[IRQ_DA8XX_EVTOUT5]		= 7,
 	[IRQ_DA8XX_EVTOUT6]		= 7,
-	[IRQ_DA8XX_EVTOUT6]		= 7,
 	[IRQ_DA8XX_EVTOUT7]		= 7,
 	[IRQ_DA8XX_CCINT0]		= 7,
 	[IRQ_DA8XX_CCERRINT]		= 7,
@@ -1042,11 +1041,7 @@ static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
 	[IRQ_DA8XX_TINT34_1]		= 7,
 	[IRQ_DA8XX_UARTINT0]		= 7,
 	[IRQ_DA8XX_KEYMGRINT]		= 7,
-	[IRQ_DA8XX_SECINT]		= 7,
-	[IRQ_DA8XX_SECKEYERR]		= 7,
 	[IRQ_DA830_MPUERR]		= 7,
-	[IRQ_DA830_IOPUERR]		= 7,
-	[IRQ_DA830_BOOTCFGERR]		= 7,
 	[IRQ_DA8XX_CHIPINT0]		= 7,
 	[IRQ_DA8XX_CHIPINT1]		= 7,
 	[IRQ_DA8XX_CHIPINT2]		= 7,

arch/arm/mach-davinci/da850.c

@@ -643,7 +643,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 	[IRQ_DA8XX_EVTOUT4]		= 7,
 	[IRQ_DA8XX_EVTOUT5]		= 7,
 	[IRQ_DA8XX_EVTOUT6]		= 7,
-	[IRQ_DA8XX_EVTOUT6]		= 7,
 	[IRQ_DA8XX_EVTOUT7]		= 7,
 	[IRQ_DA8XX_CCINT0]		= 7,
 	[IRQ_DA8XX_CCERRINT]		= 7,
@@ -661,27 +660,7 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 	[IRQ_DA8XX_TINT34_1]		= 7,
 	[IRQ_DA8XX_UARTINT0]		= 7,
 	[IRQ_DA8XX_KEYMGRINT]		= 7,
-	[IRQ_DA8XX_SECINT]		= 7,
-	[IRQ_DA8XX_SECKEYERR]		= 7,
 	[IRQ_DA850_MPUADDRERR0]		= 7,
-	[IRQ_DA850_MPUPROTERR0]		= 7,
-	[IRQ_DA850_IOPUADDRERR0]	= 7,
-	[IRQ_DA850_IOPUPROTERR0]	= 7,
-	[IRQ_DA850_IOPUADDRERR1]	= 7,
-	[IRQ_DA850_IOPUPROTERR1]	= 7,
-	[IRQ_DA850_IOPUADDRERR2]	= 7,
-	[IRQ_DA850_IOPUPROTERR2]	= 7,
-	[IRQ_DA850_BOOTCFG_ADDR_ERR]	= 7,
-	[IRQ_DA850_BOOTCFG_PROT_ERR]	= 7,
-	[IRQ_DA850_MPUADDRERR1]		= 7,
-	[IRQ_DA850_MPUPROTERR1]		= 7,
-	[IRQ_DA850_IOPUADDRERR3]	= 7,
-	[IRQ_DA850_IOPUPROTERR3]	= 7,
-	[IRQ_DA850_IOPUADDRERR4]	= 7,
-	[IRQ_DA850_IOPUPROTERR4]	= 7,
-	[IRQ_DA850_IOPUADDRERR5]	= 7,
-	[IRQ_DA850_IOPUPROTERR5]	= 7,
-	[IRQ_DA850_MIOPU_BOOTCFG_ERR]	= 7,
 	[IRQ_DA8XX_CHIPINT0]		= 7,
 	[IRQ_DA8XX_CHIPINT1]		= 7,
 	[IRQ_DA8XX_CHIPINT2]		= 7,
@@ -722,8 +701,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 	[IRQ_DA8XX_EHRPWM1]		= 7,
 	[IRQ_DA8XX_EHRPWM1TZ]		= 7,
 	[IRQ_DA850_SATAINT]		= 7,
-	[IRQ_DA850_TINT12_2]		= 7,
-	[IRQ_DA850_TINT34_2]		= 7,
 	[IRQ_DA850_TINTALL_2]		= 7,
 	[IRQ_DA8XX_ECAP0]		= 7,
 	[IRQ_DA8XX_ECAP1]		= 7,
@@ -751,8 +728,6 @@ static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 	[IRQ_DA850_CCINT1]		= 7,
 	[IRQ_DA850_CCERRINT1]		= 7,
 	[IRQ_DA850_TCERRINT2]		= 7,
-	[IRQ_DA850_TINT12_3]		= 7,
-	[IRQ_DA850_TINT34_3]		= 7,
 	[IRQ_DA850_TINTALL_3]		= 7,
 	[IRQ_DA850_MCBSP0RINT]		= 7,
 	[IRQ_DA850_MCBSP0XINT]		= 7,

arch/arm/mach-davinci/devices-da8xx.c

@@ -111,19 +111,21 @@ static const s8 da850_queue_priority_mapping[][2] = {
 	{-1, -1}
 };
 
-static struct edma_soc_info da830_edma_info[] = {
-	{
-		.n_channel		= 32,
-		.n_region		= 4,
-		.n_slot			= 128,
-		.n_tc			= 2,
-		.n_cc			= 1,
-		.queue_tc_mapping	= da8xx_queue_tc_mapping,
-		.queue_priority_mapping	= da8xx_queue_priority_mapping,
-	},
+static struct edma_soc_info da830_edma_cc0_info = {
+	.n_channel		= 32,
+	.n_region		= 4,
+	.n_slot			= 128,
+	.n_tc			= 2,
+	.n_cc			= 1,
+	.queue_tc_mapping	= da8xx_queue_tc_mapping,
+	.queue_priority_mapping	= da8xx_queue_priority_mapping,
+};
+
+static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
+	&da830_edma_cc0_info,
 };
 
-static struct edma_soc_info da850_edma_info[] = {
+static struct edma_soc_info da850_edma_cc_info[] = {
 	{
 		.n_channel		= 32,
 		.n_region		= 4,
@@ -144,6 +146,11 @@ static struct edma_soc_info da850_edma_info[] = {
 	},
 };
 
+static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
+	&da850_edma_cc_info[0],
+	&da850_edma_cc_info[1],
+};
+
 static struct resource da830_edma_resources[] = {
 	{
 		.name	= "edma_cc0",
@@ -248,18 +255,21 @@ static struct platform_device da850_edma_device = {
 	.resource	= da850_edma_resources,
 };
 
-int __init da8xx_register_edma(void)
+int __init da830_register_edma(struct edma_rsv_info *rsv)
 {
-	struct platform_device *pdev;
+	da830_edma_cc0_info.rsv = rsv;
 
-	if (cpu_is_davinci_da830())
-		pdev = &da830_edma_device;
-	else if (cpu_is_davinci_da850())
-		pdev = &da850_edma_device;
-	else
-		return -ENODEV;
+	return platform_device_register(&da830_edma_device);
+}
 
-	return platform_device_register(pdev);
+int __init da850_register_edma(struct edma_rsv_info *rsv[2])
+{
+	if (rsv) {
+		da850_edma_cc_info[0].rsv = rsv[0];
+		da850_edma_cc_info[1].rsv = rsv[1];
+	}
+
+	return platform_device_register(&da850_edma_device);
 }
 
 static struct resource da8xx_i2c_resources0[] = {

arch/arm/mach-davinci/devices-tnetv107x.c

+/*
+ * Texas Instruments TNETV107X SoC devices
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/tnetv107x.h>
+
+#include "clock.h"
+
+/* Base addresses for on-chip devices */
+#define TNETV107X_TPCC_BASE			0x01c00000
+#define TNETV107X_TPTC0_BASE			0x01c10000
+#define TNETV107X_TPTC1_BASE			0x01c10400
+#define TNETV107X_WDOG_BASE			0x08086700
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+
+/* TNETV107X specific EDMA3 information */
+#define EDMA_TNETV107X_NUM_DMACH	64
+#define EDMA_TNETV107X_NUM_TCC		64
+#define EDMA_TNETV107X_NUM_PARAMENTRY	128
+#define EDMA_TNETV107X_NUM_EVQUE	2
+#define EDMA_TNETV107X_NUM_TC		2
+#define EDMA_TNETV107X_CHMAP_EXIST	0
+#define EDMA_TNETV107X_NUM_REGIONS	4
+#define TNETV107X_DMACH2EVENT_MAP0	0x3C0CE000u
+#define TNETV107X_DMACH2EVENT_MAP1	0x000FFFFFu
+
+#define TNETV107X_DMACH_SDIO0_RX		26
+#define TNETV107X_DMACH_SDIO0_TX		27
+#define TNETV107X_DMACH_SDIO1_RX		28
+#define TNETV107X_DMACH_SDIO1_TX		29
+
+static const s8 edma_tc_mapping[][2] = {
+	/* event queue no	TC no	*/
+	{	 0,		 0	},
+	{	 1,		 1	},
+	{	-1,		-1	}
+};
+
+static const s8 edma_priority_mapping[][2] = {
+	/* event queue no	Prio	*/
+	{	 0,		 3	},
+	{	 1,		 7	},
+	{	-1,		-1	}
+};
+
+static struct edma_soc_info edma_cc0_info = {
+	.n_channel		= EDMA_TNETV107X_NUM_DMACH,
+	.n_region		= EDMA_TNETV107X_NUM_REGIONS,
+	.n_slot			= EDMA_TNETV107X_NUM_PARAMENTRY,
+	.n_tc			= EDMA_TNETV107X_NUM_TC,
+	.n_cc			= 1,
+	.queue_tc_mapping	= edma_tc_mapping,
+	.queue_priority_mapping	= edma_priority_mapping,
+};
+
+static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
+	&edma_cc0_info,
+};
+
+static struct resource edma_resources[] = {
+	{
+		.name	= "edma_cc0",
+		.start	= TNETV107X_TPCC_BASE,
+		.end	= TNETV107X_TPCC_BASE + SZ_32K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc0",
+		.start	= TNETV107X_TPTC0_BASE,
+		.end	= TNETV107X_TPTC0_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma_tc1",
+		.start	= TNETV107X_TPTC1_BASE,
+		.end	= TNETV107X_TPTC1_BASE + SZ_1K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "edma0",
+		.start	= IRQ_TNETV107X_TPCC,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "edma0_err",
+		.start	= IRQ_TNETV107X_TPCC_ERR,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device edma_device = {
+	.name		= "edma",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(edma_resources),
+	.resource	= edma_resources,
+	.dev.platform_data = tnetv107x_edma_info,
+};
+
+static struct plat_serial8250_port serial_data[] = {
+	{
+		.mapbase	= TNETV107X_UART0_BASE,
+		.irq		= IRQ_TNETV107X_UART0,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART1_BASE,
+		.irq		= IRQ_TNETV107X_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.mapbase	= TNETV107X_UART2_BASE,
+		.irq		= IRQ_TNETV107X_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+					UPF_FIXED_TYPE | UPF_IOREMAP,
+		.type		= PORT_AR7,
+		.iotype		= UPIO_MEM32,
+		.regshift	= 2,
+	},
+	{
+		.flags	= 0,
+	},
+};
+
+struct platform_device tnetv107x_serial_device = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= serial_data,
+};
+
+static struct resource mmc0_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO0_BASE,
+		.end	= TNETV107X_SDIO0_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO0,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static struct resource mmc1_resources[] = {
+	{ /* Memory mapped registers */
+		.start	= TNETV107X_SDIO1_BASE,
+		.end	= TNETV107X_SDIO1_BASE + 0x0ff,
+		.flags	= IORESOURCE_MEM
+	},
+	{ /* MMC interrupt */
+		.start	= IRQ_TNETV107X_MMC1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* SDIO interrupt */
+		.start	= IRQ_TNETV107X_SDIO1,
+		.flags	= IORESOURCE_IRQ
+	},
+	{ /* DMA RX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
+		.flags	= IORESOURCE_DMA
+	},
+	{ /* DMA TX */
+		.start	= EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
+		.flags	= IORESOURCE_DMA
+	},
+};
+
+static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
+static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device mmc_devices[2] = {
+	{
+		.name		= "davinci_mmc",
+		.id		= 0,
+		.dev		= {
+			.dma_mask		= &mmc0_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc0_resources),
+		.resource	= mmc0_resources
+	},
+	{
+		.name		= "davinci_mmc",
+		.id		= 1,
+		.dev		= {
+			.dma_mask		= &mmc1_dma_mask,
+			.coherent_dma_mask	= DMA_BIT_MASK(32),
+		},
+		.num_resources	= ARRAY_SIZE(mmc1_resources),
+		.resource	= mmc1_resources
+	},
+};
+
+static const u32 emif_windows[] = {
+	TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
+	TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
+};
+
+static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
+
+static struct resource wdt_resources[] = {
+	{
+		.start	= TNETV107X_WDOG_BASE,
+		.end	= TNETV107X_WDOG_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device tnetv107x_wdt_device = {
+	.name		= "tnetv107x_wdt",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(wdt_resources),
+	.resource	= wdt_resources,
+};
+
+static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
+{
+	struct resource res[2];
+	struct platform_device *pdev;
+	u32	range;
+	int	ret;
+
+	/* Figure out the resource range from the ale/cle masks */
+	range = max(data->mask_cle, data->mask_ale);
+	range = PAGE_ALIGN(range + 4) - 1;
+
+	if (range >= emif_window_sizes[chipsel])
+		return -EINVAL;
+
+	pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+	if (!pdev)
+		return -ENOMEM;
+
+	pdev->name		= "davinci_nand";
+	pdev->id		= chipsel;
+	pdev->dev.platform_data	= data;
+
+	memset(res, 0, sizeof(res));
+
+	res[0].start	= emif_windows[chipsel];
+	res[0].end	= res[0].start + range;
+	res[0].flags	= IORESOURCE_MEM;
+
+	res[1].start	= TNETV107X_ASYNC_EMIF_CNTRL_BASE;
+	res[1].end	= res[1].start + SZ_4K - 1;
+	res[1].flags	= IORESOURCE_MEM;
+
+	ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+	if (ret < 0) {
+		kfree(pdev);
+		return ret;
+	}
+
+	return platform_device_register(pdev);
+}
+
+void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
+{
+	int i;
+
+	platform_device_register(&edma_device);
+	platform_device_register(&tnetv107x_wdt_device);
+
+	if (info->serial_config)
+		davinci_serial_init(info->serial_config);
+
+	for (i = 0; i < 2; i++)
+		if (info->mmc_config[i]) {
+			mmc_devices[i].dev.platform_data = info->mmc_config[i];
+			platform_device_register(&mmc_devices[i]);
+		}
+
+	for (i = 0; i < 4; i++)
+		if (info->nand_config[i])
+			nand_init(i, info->nand_config[i]);
+}

arch/arm/mach-davinci/dm355.c

@@ -591,16 +591,18 @@ queue_priority_mapping[][2] = {
 	{-1, -1},
 };
 
-static struct edma_soc_info dm355_edma_info[] = {
-	{
-		.n_channel		= 64,
-		.n_region		= 4,
-		.n_slot			= 128,
-		.n_tc			= 2,
-		.n_cc			= 1,
-		.queue_tc_mapping	= queue_tc_mapping,
-		.queue_priority_mapping	= queue_priority_mapping,
-	},
+static struct edma_soc_info edma_cc0_info = {
+	.n_channel		= 64,
+	.n_region		= 4,
+	.n_slot			= 128,
+	.n_tc			= 2,
+	.n_cc			= 1,
+	.queue_tc_mapping	= queue_tc_mapping,
+	.queue_priority_mapping	= queue_priority_mapping,
+};
+
+static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
+       &edma_cc0_info,
 };
 
 static struct resource edma_resources[] = {

arch/arm/mach-davinci/dm365.c

@@ -822,17 +822,19 @@ dm365_queue_priority_mapping[][2] = {
 	{-1, -1},
 };
 
-static struct edma_soc_info dm365_edma_info[] = {
-	{
-		.n_channel		= 64,
-		.n_region		= 4,
-		.n_slot			= 256,
-		.n_tc			= 4,
-		.n_cc			= 1,
-		.queue_tc_mapping	= dm365_queue_tc_mapping,
-		.queue_priority_mapping	= dm365_queue_priority_mapping,
-		.default_queue		= EVENTQ_3,
-	},
+static struct edma_soc_info edma_cc0_info = {
+	.n_channel		= 64,
+	.n_region		= 4,
+	.n_slot			= 256,
+	.n_tc			= 4,
+	.n_cc			= 1,
+	.queue_tc_mapping	= dm365_queue_tc_mapping,
+	.queue_priority_mapping	= dm365_queue_priority_mapping,
+	.default_queue		= EVENTQ_3,
+};
+
+static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
+	&edma_cc0_info,
 };
 
 static struct resource edma_resources[] = {
@@ -1020,6 +1022,8 @@ static struct davinci_timer_info dm365_timer_info = {
 	.clocksource_id	= T0_TOP,
 };
 
+#define DM365_UART1_BASE	(IO_PHYS + 0x106000)
+
 static struct plat_serial8250_port dm365_serial_platform_data[] = {
 	{
 		.mapbase	= DAVINCI_UART0_BASE,
@@ -1030,7 +1034,7 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
 		.regshift	= 2,
 	},
 	{
-		.mapbase	= DAVINCI_UART1_BASE,
+		.mapbase	= DM365_UART1_BASE,
 		.irq		= IRQ_UARTINT1,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 				  UPF_IOREMAP,

arch/arm/mach-davinci/dm644x.c

@@ -492,16 +492,18 @@ queue_priority_mapping[][2] = {
 	{-1, -1},
 };
 
-static struct edma_soc_info dm644x_edma_info[] = {
-	{
-		.n_channel		= 64,
-		.n_region		= 4,
-		.n_slot			= 128,
-		.n_tc			= 2,
-		.n_cc			= 1,
-		.queue_tc_mapping	= queue_tc_mapping,
-		.queue_priority_mapping	= queue_priority_mapping,
-	},
+static struct edma_soc_info edma_cc0_info = {
+	.n_channel		= 64,
+	.n_region		= 4,
+	.n_slot			= 128,
+	.n_tc			= 2,
+	.n_cc			= 1,
+	.queue_tc_mapping	= queue_tc_mapping,
+	.queue_priority_mapping	= queue_priority_mapping,
+};
+
+static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
+	&edma_cc0_info,
 };
 
 static struct resource edma_resources[] = {

arch/arm/mach-davinci/dm646x.c

@@ -529,16 +529,18 @@ dm646x_queue_priority_mapping[][2] = {
 	{-1, -1},
 };
 
-static struct edma_soc_info dm646x_edma_info[] = {
-	{
-		.n_channel		= 64,
-		.n_region		= 6,	/* 0-1, 4-7 */
-		.n_slot			= 512,
-		.n_tc			= 4,
-		.n_cc			= 1,
-		.queue_tc_mapping	= dm646x_queue_tc_mapping,
-		.queue_priority_mapping	= dm646x_queue_priority_mapping,
-	},
+static struct edma_soc_info edma_cc0_info = {
+	.n_channel		= 64,
+	.n_region		= 6,	/* 0-1, 4-7 */
+	.n_slot			= 512,
+	.n_tc			= 4,
+	.n_cc			= 1,
+	.queue_tc_mapping	= dm646x_queue_tc_mapping,
+	.queue_priority_mapping	= dm646x_queue_priority_mapping,
+};
+
+static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
+	&edma_cc0_info,
 };
 
 static struct resource edma_resources[] = {
@@ -877,6 +879,13 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
 	platform_device_register(&vpif_capture_dev);
 }
 
+int __init dm646x_init_edma(struct edma_rsv_info *rsv)
+{
+	edma_cc0_info.rsv = rsv;
+
+	return platform_device_register(&dm646x_edma_device);
+}
+
 void __init dm646x_init(void)
 {
 	dm646x_board_setup_refclk(&ref_clk);
@@ -888,7 +897,6 @@ static int __init dm646x_init_devices(void)
 	if (!cpu_is_davinci_dm646x())
 		return 0;
 
-	platform_device_register(&dm646x_edma_device);
 	platform_device_register(&dm646x_emac_device);
 	return 0;
 }

arch/arm/mach-davinci/dma.c

@@ -99,8 +99,6 @@
 
 #define EDMA_MAX_DMACH           64
 #define EDMA_MAX_PARAMENTRY     512
-#define EDMA_MAX_CC               2
-
 
 /*****************************************************************************/
 
@@ -207,6 +205,18 @@ static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
 	edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
 }
 
+static inline void set_bits(int offset, int len, unsigned long *p)
+{
+	for (; len > 0; len--)
+		set_bit(offset + (len - 1), p);
+}
+
+static inline void clear_bits(int offset, int len, unsigned long *p)
+{
+	for (; len > 0; len--)
+		clear_bit(offset + (len - 1), p);
+}
+
 /*****************************************************************************/
 
 /* actual number of DMA channels and slots on this silicon */
@@ -1376,11 +1386,13 @@ EXPORT_SYMBOL(edma_clear_event);
 
 static int __init edma_probe(struct platform_device *pdev)
 {
-	struct edma_soc_info	*info = pdev->dev.platform_data;
+	struct edma_soc_info	**info = pdev->dev.platform_data;
 	const s8		(*queue_priority_mapping)[2];
 	const s8		(*queue_tc_mapping)[2];
-	int			i, j, found = 0;
+	int			i, j, off, ln, found = 0;
 	int			status = -1;
+	const s16		(*rsv_chans)[2];
+	const s16		(*rsv_slots)[2];
 	int			irq[EDMA_MAX_CC] = {0, 0};
 	int			err_irq[EDMA_MAX_CC] = {0, 0};
 	struct resource		*r[EDMA_MAX_CC] = {NULL};
@@ -1395,7 +1407,7 @@ static int __init edma_probe(struct platform_device *pdev)
 		sprintf(res_name, "edma_cc%d", j);
 		r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 						res_name);
-		if (!r[j]) {
+		if (!r[j] || !info[j]) {
 			if (found)
 				break;
 			else
@@ -1426,13 +1438,14 @@ static int __init edma_probe(struct platform_device *pdev)
 		}
 		memset(edma_cc[j], 0, sizeof(struct edma));
 
-		edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
+		edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
 							EDMA_MAX_DMACH);
-		edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
+		edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
 							EDMA_MAX_PARAMENTRY);
-		edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
+		edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
+							EDMA_MAX_CC);
 
-		edma_cc[j]->default_queue = info[j].default_queue;
+		edma_cc[j]->default_queue = info[j]->default_queue;
 		if (!edma_cc[j]->default_queue)
 			edma_cc[j]->default_queue = EVENTQ_1;
 
@@ -1447,6 +1460,31 @@ static int __init edma_probe(struct platform_device *pdev)
 		memset(edma_cc[j]->edma_unused, 0xff,
 			sizeof(edma_cc[j]->edma_unused));
 
+		if (info[j]->rsv) {
+
+			/* Clear the reserved channels in unused list */
+			rsv_chans = info[j]->rsv->rsv_chans;
+			if (rsv_chans) {
+				for (i = 0; rsv_chans[i][0] != -1; i++) {
+					off = rsv_chans[i][0];
+					ln = rsv_chans[i][1];
+					clear_bits(off, ln,
+						edma_cc[j]->edma_unused);
+				}
+			}
+
+			/* Set the reserved slots in inuse list */
+			rsv_slots = info[j]->rsv->rsv_slots;
+			if (rsv_slots) {
+				for (i = 0; rsv_slots[i][0] != -1; i++) {
+					off = rsv_slots[i][0];
+					ln = rsv_slots[i][1];
+					set_bits(off, ln,
+						edma_cc[j]->edma_inuse);
+				}
+			}
+		}
+
 		sprintf(irq_name, "edma%d", j);
 		irq[j] = platform_get_irq_byname(pdev, irq_name);
 		edma_cc[j]->irq_res_start = irq[j];
@@ -1476,8 +1514,8 @@ static int __init edma_probe(struct platform_device *pdev)
 		for (i = 0; i < edma_cc[j]->num_channels; i++)
 			map_dmach_queue(j, i, EVENTQ_1);
 
-		queue_tc_mapping = info[j].queue_tc_mapping;
-		queue_priority_mapping = info[j].queue_priority_mapping;
+		queue_tc_mapping = info[j]->queue_tc_mapping;
+		queue_priority_mapping = info[j]->queue_priority_mapping;
 
 		/* Event queue to TC mapping */
 		for (i = 0; queue_tc_mapping[i][0] != -1; i++)
@@ -1496,7 +1534,7 @@ static int __init edma_probe(struct platform_device *pdev)
 		if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
 			map_dmach_param(j);
 
-		for (i = 0; i < info[j].n_region; i++) {
+		for (i = 0; i < info[j]->n_region; i++) {
 			edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
 			edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
 			edma_write_array(j, EDMA_QRAE, i, 0x0);

arch/arm/mach-davinci/gpio-tnetv107x.c

+/*
+ * Texas Instruments TNETV107X GPIO Controller
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <mach/common.h>
+#include <mach/tnetv107x.h>
+
+struct tnetv107x_gpio_regs {
+	u32	idver;
+	u32	data_in[3];
+	u32	data_out[3];
+	u32	direction[3];
+	u32	enable[3];
+};
+
+#define gpio_reg_index(gpio)	((gpio) >> 5)
+#define gpio_reg_bit(gpio)	BIT((gpio) & 0x1f)
+
+#define gpio_reg_rmw(reg, mask, val)	\
+	__raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg))
+
+#define gpio_reg_set_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio))
+
+#define gpio_reg_clear_bit(reg, gpio)	\
+	gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0)
+
+#define gpio_reg_get_bit(reg, gpio)	\
+	(__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio))
+
+#define chip2controller(chip)		\
+	container_of(chip, struct davinci_gpio_controller, chip)
+
+#define TNETV107X_GPIO_CTLRS	DIV_ROUND_UP(TNETV107X_N_GPIO, 32)
+
+static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS];
+
+static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_clear_bit(&regs->enable, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	gpio_reg_set_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	gpio_reg_clear_bit(&regs->direction, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+
+	return 0;
+}
+
+static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	int ret;
+
+	ret = gpio_reg_get_bit(&regs->data_in, gpio);
+
+	return ret ? 1 : 0;
+}
+
+static void tnetv107x_gpio_set(struct gpio_chip *chip,
+		unsigned offset, int value)
+{
+	struct davinci_gpio_controller *ctlr = chip2controller(chip);
+	struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs;
+	unsigned gpio = chip->base + offset;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctlr->lock, flags);
+
+	if (value)
+		gpio_reg_set_bit(&regs->data_out, gpio);
+	else
+		gpio_reg_clear_bit(&regs->data_out, gpio);
+
+	spin_unlock_irqrestore(&ctlr->lock, flags);
+}
+
+static int __init tnetv107x_gpio_setup(void)
+{
+	int i, base;
+	unsigned ngpio;
+	struct davinci_soc_info *soc_info = &davinci_soc_info;
+	struct tnetv107x_gpio_regs *regs;
+	struct davinci_gpio_controller *ctlr;
+
+	if (soc_info->gpio_type != GPIO_TYPE_TNETV107X)
+		return 0;
+
+	ngpio = soc_info->gpio_num;
+	if (ngpio == 0) {
+		pr_err("GPIO setup:  how many GPIOs?\n");
+		return -EINVAL;
+	}
+
+	if (WARN_ON(TNETV107X_N_GPIO < ngpio))
+		ngpio = TNETV107X_N_GPIO;
+
+	regs = ioremap(soc_info->gpio_base, SZ_4K);
+	if (WARN_ON(!regs))
+		return -EINVAL;
+
+	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
+		ctlr = &chips[i];
+
+		ctlr->chip.label	= "tnetv107x";
+		ctlr->chip.can_sleep	= 0;
+		ctlr->chip.base		= base;
+		ctlr->chip.ngpio	= ngpio - base;
+		if (ctlr->chip.ngpio > 32)
+			ctlr->chip.ngpio = 32;
+
+		ctlr->chip.request		= tnetv107x_gpio_request;
+		ctlr->chip.free			= tnetv107x_gpio_free;
+		ctlr->chip.direction_input	= tnetv107x_gpio_dir_in;
+		ctlr->chip.get			= tnetv107x_gpio_get;
+		ctlr->chip.direction_output	= tnetv107x_gpio_dir_out;
+		ctlr->chip.set			= tnetv107x_gpio_set;
+
+		spin_lock_init(&ctlr->lock);
+
+		ctlr->regs	= regs;
+		ctlr->set_data	= &regs->data_out[i];
+		ctlr->clr_data	= &regs->data_out[i];
+		ctlr->in_data	= &regs->data_in[i];
+
+		gpiochip_add(&ctlr->chip);
+	}
+
+	soc_info->gpio_ctlrs = chips;
+	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+	return 0;
+}
+pure_initcall(tnetv107x_gpio_setup);

arch/arm/mach-davinci/include/mach/da8xx.h

@@ -67,7 +67,8 @@ extern void __iomem *da8xx_syscfg1_base;
 void __init da830_init(void);
 void __init da850_init(void);
 
-int da8xx_register_edma(void);
+int da830_register_edma(struct edma_rsv_info *rsv);
+int da850_register_edma(struct edma_rsv_info *rsv[2]);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);

arch/arm/mach-davinci/include/mach/debug-macro.S

@@ -17,22 +17,50 @@
  */
 
 #include <linux/serial_reg.h>
+
+#include <asm/memory.h>
+
+#include <mach/serial.h>
+
 #define UART_SHIFT	2
 
+		.pushsection .data
+davinci_uart_phys:	.word	0
+davinci_uart_virt:	.word	0
+		.popsection
+
 		.macro addruart, rx, tmp
+
+		/* Use davinci_uart_phys/virt if already configured */
+10:		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1			@ MMU enabled?
+		ldreq	\rx, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\rx, =davinci_uart_virt
+		ldr	\rx, [\rx]
+		cmp	\rx, #0			@ is port configured?
+		bne	99f			@ already configured
+
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ MMU enabled?
-		moveq	\rx, #0x01000000	@ physical base address
-		movne	\rx, #0xfe000000	@ virtual base
-#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
-#error Cannot enable DaVinci and DA8XX platforms concurrently
-#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
-	defined(CONFIG_MACH_DAVINCI_DA850_EVM)
-		orr	\rx, \rx, #0x00d00000	@ physical base address
-		orr	\rx, \rx, #0x0000d000	@ of UART 2
-#else
-		orr	\rx, \rx, #0x00c20000   @ UART 0
-#endif
+
+		/* Copy uart phys address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_phys)
+		ldrne	\tmp, =davinci_uart_phys
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #0]
+		str	\rx, [\tmp]
+
+		/* Copy uart virt address from decompressor uart info */
+		ldreq	\tmp, =__virt_to_phys(davinci_uart_virt)
+		ldrne	\tmp, =davinci_uart_virt
+		ldreq	\rx, =DAVINCI_UART_INFO
+		ldrne	\rx, =__phys_to_virt(DAVINCI_UART_INFO)
+		ldr	\rx, [\rx, #4]
+		str	\rx, [\tmp]
+
+		b	10b
+99:
 		.endm
 
 		.macro	senduart,rd,rx

arch/arm/mach-davinci/include/mach/dm646x.h

@@ -32,6 +32,7 @@ void __init dm646x_init(void);
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
 void __init dm646x_board_setup_refclk(struct clk *clk);
+int __init dm646x_init_edma(struct edma_rsv_info *rsv);
 
 void dm646x_video_init(void);
 

arch/arm/mach-davinci/include/mach/edma.h

@@ -230,6 +230,8 @@ enum sync_dimension {
 #define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
 
+#define EDMA_MAX_CC               2
+
 /* alloc/free DMA channels and their dedicated parameter RAM slots */
 int edma_alloc_channel(int channel,
 	void (*callback)(unsigned channel, u16 ch_status, void *data),
@@ -269,6 +271,12 @@ void edma_clear_event(unsigned channel);
 void edma_pause(unsigned channel);
 void edma_resume(unsigned channel);
 
+struct edma_rsv_info {
+
+	const s16	(*rsv_chans)[2];
+	const s16	(*rsv_slots)[2];
+};
+
 /* platform_data for EDMA driver */
 struct edma_soc_info {
 
@@ -280,6 +288,9 @@ struct edma_soc_info {
 	unsigned	n_cc;
 	enum dma_event_q	default_queue;
 
+	/* Resource reservation for other cores */
+	struct edma_rsv_info	*rsv;
+
 	const s8	(*queue_tc_mapping)[2];
 	const s8	(*queue_priority_mapping)[2];
 };

arch/arm/mach-davinci/include/mach/gpio.h

@@ -25,6 +25,7 @@
 
 enum davinci_gpio_type {
 	GPIO_TYPE_DAVINCI = 0,
+	GPIO_TYPE_TNETV107X,
 };
 
 /*
@@ -87,9 +88,13 @@ static inline u32 __gpio_mask(unsigned gpio)
 	return 1 << (gpio % 32);
 }
 
-/* The get/set/clear functions will inline when called with constant
+/*
+ * The get/set/clear functions will inline when called with constant
  * parameters referencing built-in GPIOs, for low-overhead bitbanging.
  *
+ * gpio_set_value() will inline only on traditional Davinci style controllers
+ * with distinct set/clear registers.
+ *
  * Otherwise, calls with variable parameters or referencing external
  * GPIOs (e.g. on GPIO expander chips) use outlined functions.
  */
@@ -100,12 +105,15 @@ static inline void gpio_set_value(unsigned gpio, int value)
 		u32				mask;
 
 		ctlr = __gpio_to_controller(gpio);
-		mask = __gpio_mask(gpio);
-		if (value)
-			__raw_writel(mask, ctlr->set_data);
-		else
-			__raw_writel(mask, ctlr->clr_data);
-		return;
+
+		if (ctlr->set_data != ctlr->clr_data) {
+			mask = __gpio_mask(gpio);
+			if (value)
+				__raw_writel(mask, ctlr->set_data);
+			else
+				__raw_writel(mask, ctlr->clr_data);
+			return;
+		}
 	}
 
 	__gpio_set_value(gpio, value);

arch/arm/mach-davinci/include/mach/serial.h

@@ -11,8 +11,19 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
+#include <asm/memory.h>
+
 #include <mach/hardware.h>
 
+/*
+ * Stolen area that contains debug uart physical and virtual addresses.  These
+ * addresses are filled in by the uncompress.h code, and are used by the debug
+ * macros in debug-macro.S.
+ *
+ * This area sits just below the page tables (see arch/arm/kernel/head.S).
+ */
+#define DAVINCI_UART_INFO	(PHYS_OFFSET + 0x3ff8)
+
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
@@ -21,16 +32,26 @@
 #define DA8XX_UART1_BASE	(IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE	(IO_PHYS + 0x10d000)
 
+#define TNETV107X_UART0_BASE	0x08108100
+#define TNETV107X_UART1_BASE	0x08088400
+#define TNETV107X_UART2_BASE	0x08108300
+
+#define TNETV107X_UART0_VIRT	IOMEM(0xfee08100)
+#define TNETV107X_UART1_VIRT	IOMEM(0xfed88400)
+#define TNETV107X_UART2_VIRT	IOMEM(0xfee08300)
+
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU		0x0c
 #define UART_DM646X_SCR			0x10
 #define UART_DM646X_SCR_TX_WATERMARK	0x08
 
+#ifndef __ASSEMBLY__
 struct davinci_uart_config {
 	/* Bit field of UARTs present; bit 0 --> UART1 */
 	unsigned int enabled_uarts;
 };
 
 extern int davinci_serial_init(struct davinci_uart_config *);
+#endif
 
 #endif /* __ASM_ARCH_SERIAL_H */

arch/arm/mach-davinci/include/mach/tnetv107x.h

+/*
+ * Texas Instruments TNETV107X SoC Specific Defines
+ *
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
+#define __ASM_ARCH_DAVINCI_TNETV107X_H
+
+#include <asm/sizes.h>
+
+#define TNETV107X_DDR_BASE	0x80000000
+
+/*
+ * Fixed mapping for early init starts here. If low-level debug is enabled,
+ * this area also gets mapped via io_pg_offset and io_phys by the boot code.
+ * To fit in with the io_pg_offset calculation, the io base address selected
+ * here _must_ be a multiple of 2^20.
+ */
+#define TNETV107X_IO_BASE	0x08000000
+#define TNETV107X_IO_VIRT	(IO_VIRT + SZ_1M)
+
+#define TNETV107X_N_GPIO	65
+
+#ifndef __ASSEMBLY__
+
+#include <linux/serial_8250.h>
+#include <mach/mmc.h>
+#include <mach/nand.h>
+#include <mach/serial.h>
+
+struct tnetv107x_device_info {
+	struct davinci_uart_config	*serial_config;
+	struct davinci_mmc_config	*mmc_config[2];  /* 2 controllers */
+	struct davinci_nand_pdata	*nand_config[4]; /* 4 chipsels */
+};
+
+extern struct platform_device tnetv107x_wdt_device;
+extern struct platform_device tnetv107x_serial_device;
+
+extern void __init tnetv107x_init(void);
+extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void __init tnetv107x_irq_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */

arch/arm/mach-davinci/include/mach/uncompress.h

 /*
  * Serial port stubs for kernel decompress status messages
  *
- *  Author:     Anant Gole
- * (C) Copyright (C) 2006, Texas Instruments, Inc
+ * Initially based on:
+ * arch/arm/plat-omap/include/mach/uncompress.h
+ *
+ * Original copyrights follow.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -11,30 +20,17 @@
 
 #include <linux/types.h>
 #include <linux/serial_reg.h>
-#include <mach/serial.h>
 
 #include <asm/mach-types.h>
 
-extern unsigned int __machine_arch_type;
+#include <mach/serial.h>
 
 static u32 *uart;
-
-static u32 *get_uart_base(void)
-{
-	if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM ||
-		__machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM)
-		return (u32 *)DA8XX_UART2_BASE;
-	else
-		return (u32 *)DAVINCI_UART0_BASE;
-}
+static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
 
 /* PORT_16C550A, in polled non-fifo mode */
-
 static void putc(char c)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 	uart[UART_TX] = c;
@@ -42,12 +38,61 @@ static void putc(char c)
 
 static inline void flush(void)
 {
-	if (!uart)
-		uart = get_uart_base();
-
 	while (!(uart[UART_LSR] & UART_LSR_THRE))
 		barrier();
 }
 
-#define arch_decomp_setup()
+static inline void set_uart_info(u32 phys, void * __iomem virt)
+{
+	uart = (u32 *)phys;
+	uart_info[0] = phys;
+	uart_info[1] = (u32)virt;
+}
+
+#define _DEBUG_LL_ENTRY(machine, phys, virt)			\
+	if (machine_is_##machine()) {				\
+		set_uart_info(phys, virt);			\
+		break;						\
+	}
+
+#define DEBUG_LL_DAVINCI(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE,	\
+			IO_ADDRESS(DAVINCI_UART##port##_BASE))
+
+#define DEBUG_LL_DA8XX(machine, port)				\
+	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
+			IO_ADDRESS(DA8XX_UART##port##_BASE))
+
+#define DEBUG_LL_TNETV107X(machine, port)			\
+	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE,	\
+			TNETV107X_UART##port##_VIRT)
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+	/*
+	 * Initialize the port based on the machine ID from the bootloader.
+	 * Note that we're using macros here instead of switch statement
+	 * as machine_is functions are optimized out for the boards that
+	 * are not selected.
+	 */
+	do {
+		/* Davinci boards */
+		DEBUG_LL_DAVINCI(davinci_evm,		0);
+		DEBUG_LL_DAVINCI(sffsdr,		0);
+		DEBUG_LL_DAVINCI(neuros_osd2,		0);
+		DEBUG_LL_DAVINCI(davinci_dm355_evm,	0);
+		DEBUG_LL_DAVINCI(dm355_leopard,		0);
+		DEBUG_LL_DAVINCI(davinci_dm6467_evm,	0);
+		DEBUG_LL_DAVINCI(davinci_dm365_evm,	0);
+
+		/* DA8xx boards */
+		DEBUG_LL_DA8XX(davinci_da830_evm,	2);
+		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
+
+		/* TNETV107x boards */
+		DEBUG_LL_TNETV107X(tnetv107x,		1);
+	} while (0);
+}
+
+#define arch_decomp_setup()	__arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()