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4277ff5e
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体验新版 GitCode,发现更多精彩内容 >>
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4277ff5e
编写于
6月 03, 2006
作者:
R
Ralf Baechle
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[MIPS] Fix use of ehb instruction for non-R2 configurations.
Signed-off-by:
N
Ralf Baechle
<
ralf@linux-mips.org
>
上级
b4ab24e1
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
27 addition
and
26 deletion
+27
-26
arch/mips/kernel/entry.S
arch/mips/kernel/entry.S
+3
-3
arch/mips/kernel/gdb-low.S
arch/mips/kernel/gdb-low.S
+2
-2
arch/mips/kernel/genex.S
arch/mips/kernel/genex.S
+1
-1
arch/mips/kernel/head.S
arch/mips/kernel/head.S
+1
-1
arch/mips/kernel/r4k_switch.S
arch/mips/kernel/r4k_switch.S
+3
-3
arch/mips/kernel/smtc-asm.S
arch/mips/kernel/smtc-asm.S
+5
-5
include/asm-mips/asmmacro.h
include/asm-mips/asmmacro.h
+2
-2
include/asm-mips/mipsregs.h
include/asm-mips/mipsregs.h
+2
-1
include/asm-mips/stackframe.h
include/asm-mips/stackframe.h
+8
-8
未找到文件。
arch/mips/kernel/entry.S
浏览文件 @
4277ff5e
...
...
@@ -87,7 +87,7 @@ FEXPORT(restore_all) # restore full frame
ori
v1
,
v0
,
TCSTATUS_IXMT
mtc0
v1
,
CP0_TCSTATUS
andi
v0
,
TCSTATUS_IXMT
ehb
_
ehb
mfc0
t0
,
CP0_TCCONTEXT
DMT
9
#
dmt
t1
jal
mips_ihb
...
...
@@ -95,7 +95,7 @@ FEXPORT(restore_all) # restore full frame
andi
t3
,
t0
,
0xff00
or
t2
,
t2
,
t3
mtc0
t2
,
CP0_STATUS
ehb
_
ehb
andi
t1
,
t1
,
VPECONTROL_TE
beqz
t1
,
1
f
EMT
...
...
@@ -105,7 +105,7 @@ FEXPORT(restore_all) # restore full frame
xori
v1
,
v1
,
TCSTATUS_IXMT
or
v1
,
v0
,
v1
mtc0
v1
,
CP0_TCSTATUS
ehb
_
ehb
xor
t0
,
t0
,
t3
mtc0
t0
,
CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC */
...
...
arch/mips/kernel/gdb-low.S
浏览文件 @
4277ff5e
...
...
@@ -291,7 +291,7 @@
ori
t1
,
t2
,
TCSTATUS_IXMT
mtc0
t1
,
CP0_TCSTATUS
andi
t2
,
t2
,
TCSTATUS_IXMT
ehb
_
ehb
DMT
9
#
dmt
t1
jal
mips_ihb
nop
...
...
@@ -310,7 +310,7 @@
xori
t1
,
t1
,
TCSTATUS_IXMT
or
t1
,
t1
,
t2
mtc0
t1
,
CP0_TCSTATUS
ehb
_
ehb
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_L
v0
,
GDB_FR_STATUS
(
sp
)
LONG_L
v1
,
GDB_FR_EPC
(
sp
)
...
...
arch/mips/kernel/genex.S
浏览文件 @
4277ff5e
...
...
@@ -214,7 +214,7 @@ NESTED(except_vec_vi_handler, 0, sp)
mtc0
t0
,
CP0_TCCONTEXT
xor
t1
,
t1
,
t0
mtc0
t1
,
CP0_STATUS
ehb
_
ehb
#endif /* CONFIG_MIPS_MT_SMTC */
CLI
move
a0
,
sp
...
...
arch/mips/kernel/head.S
浏览文件 @
4277ff5e
...
...
@@ -96,7 +96,7 @@
/
*
Clear
TKSU
,
leave
IXMT
*/
xori
t0
,
0x00001800
mtc0
t0
,
CP0_TCSTATUS
ehb
_
ehb
/
*
We
need
to
leave
the
global
IE
bit
set
,
but
clear
EXL
...
*/
mfc0
t0
,
CP0_STATUS
or
t0
,
ST0_CU0
| ST0_EXL |
ST0_ERL
| \set |
\
clr
...
...
arch/mips/kernel/r4k_switch.S
浏览文件 @
4277ff5e
...
...
@@ -94,7 +94,7 @@
ori
t1
,
t2
,
TCSTATUS_IXMT
mtc0
t1
,
CP0_TCSTATUS
andi
t2
,
t2
,
TCSTATUS_IXMT
ehb
_
ehb
DMT
8
#
dmt
t0
move
t1
,
ra
jal
mips_ihb
...
...
@@ -109,7 +109,7 @@
or
a2
,
t1
mtc0
a2
,
CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
ehb
_
ehb
andi
t0
,
t0
,
VPECONTROL_TE
beqz
t0
,
1
f
emt
...
...
@@ -118,7 +118,7 @@
xori
t1
,
t1
,
TCSTATUS_IXMT
or
t1
,
t1
,
t2
mtc0
t1
,
CP0_TCSTATUS
ehb
_
ehb
#endif /* CONFIG_MIPS_MT_SMTC */
move
v0
,
a0
jr
ra
...
...
arch/mips/kernel/smtc-asm.S
浏览文件 @
4277ff5e
...
...
@@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector)
.
set
noat
/
*
Disable
thread
scheduling
to
make
Status
update
atomic
*/
DMT
27
#
dmt
k1
ehb
_
ehb
/
*
Set
EXL
*/
mfc0
k0
,
CP0_STATUS
ori
k0
,
k0
,
ST0_EXL
mtc0
k0
,
CP0_STATUS
ehb
_
ehb
/
*
Thread
scheduling
now
inhibited
by
EXL
.
Restore
TE
state
.
*/
andi
k1
,
k1
,
VPECONTROL_TE
beqz
k1
,
1
f
...
...
@@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector)
li
k1
,
ST0_CU0
or
k1
,
k1
,
k0
mtc0
k1
,
CP0_STATUS
ehb
_
ehb
get_saved_sp
/
*
Interrupting
TC
will
have
pre
-
set
values
in
slots
in
the
new
frame
*/
2
:
subu
k1
,
k1
,
PT_SIZE
...
...
@@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector)
lw
k0
,
PT_TCSTATUS
(
k1
)
/
*
Write
it
to
TCStatus
to
restore
CU
/
KSU
/
IXMT
state
*/
mtc0
k0
,
$
2
,
1
ehb
_
ehb
lw
k0
,
PT_EPC
(
k1
)
mtc0
k0
,
CP0_EPC
/
*
Save
all
will
redundantly
recompute
the
SP
,
but
use
it
for
now
*/
...
...
@@ -116,7 +116,7 @@ LEAF(self_ipi)
mfc0
t0
,
CP0_TCSTATUS
ori
t1
,
t0
,
TCSTATUS_IXMT
mtc0
t1
,
CP0_TCSTATUS
ehb
_
ehb
/
*
We
know
we
're in kernel mode, so prepare stack frame */
subu
t1
,
sp
,
PT_SIZE
sw
ra
,
PT_EPC
(
t1
)
...
...
include/asm-mips/asmmacro.h
浏览文件 @
4277ff5e
...
...
@@ -26,14 +26,14 @@
ori
\
reg
,
\
reg
,
TCSTATUS_IXMT
xori
\
reg
,
\
reg
,
TCSTATUS_IXMT
mtc0
\
reg
,
CP0_TCSTATUS
ehb
_
ehb
.
endm
.
macro
local_irq_disable
reg
=
t0
mfc0
\
reg
,
CP0_TCSTATUS
ori
\
reg
,
\
reg
,
TCSTATUS_IXMT
mtc0
\
reg
,
CP0_TCSTATUS
ehb
_
ehb
.
endm
#else
.
macro
local_irq_enable
reg
=
t0
...
...
include/asm-mips/mipsregs.h
浏览文件 @
4277ff5e
...
...
@@ -1459,7 +1459,8 @@ static inline void __emt(unsigned int previous)
static
inline
void
__ehb
(
void
)
{
__asm__
__volatile__
(
" ehb
\n
"
);
" .set mips32r2
\n
"
" ehb
\n
"
" .set mips0
\n
"
);
}
/*
...
...
include/asm-mips/stackframe.h
浏览文件 @
4277ff5e
...
...
@@ -304,7 +304,7 @@
mfc0
v0
,
CP0_TCSTATUS
ori
v0
,
TCSTATUS_IXMT
mtc0
v0
,
CP0_TCSTATUS
ehb
_
ehb
DMT
5
#
dmt
a1
jal
mips_ihb
#endif
/* CONFIG_MIPS_MT_SMTC */
...
...
@@ -325,14 +325,14 @@
* restore TCStatus.IXMT.
*/
LONG_L
v1
,
PT_TCSTATUS
(
sp
)
ehb
_
ehb
mfc0
v0
,
CP0_TCSTATUS
andi
v1
,
TCSTATUS_IXMT
/* We know that TCStatua.IXMT should be set from above */
xori
v0
,
v0
,
TCSTATUS_IXMT
or
v0
,
v0
,
v1
mtc0
v0
,
CP0_TCSTATUS
ehb
_
ehb
andi
a1
,
a1
,
VPECONTROL_TE
beqz
a1
,
1
f
emt
...
...
@@ -411,7 +411,7 @@
/* Clear TKSU, leave IXMT */
xori
t0
,
0x00001800
mtc0
t0
,
CP0_TCSTATUS
ehb
_
ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0
t0
,
CP0_STATUS
ori
t0
,
ST0_EXL
|
ST0_ERL
...
...
@@ -438,7 +438,7 @@
* and enable interrupts only for the
* current TC, using the TCStatus register.
*/
ehb
_
ehb
mfc0
t0
,
CP0_TCSTATUS
/* Fortunately CU 0 is in the same place in both registers */
/* Set TCU0, TKSU (for later inversion) and IXMT */
...
...
@@ -447,7 +447,7 @@
/* Clear TKSU *and* IXMT */
xori
t0
,
0x00001c00
mtc0
t0
,
CP0_TCSTATUS
ehb
_
ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0
t0
,
CP0_STATUS
ori
t0
,
ST0_EXL
...
...
@@ -479,7 +479,7 @@
andi
v1
,
v0
,
TCSTATUS_IXMT
ori
v0
,
TCSTATUS_IXMT
mtc0
v0
,
CP0_TCSTATUS
ehb
_
ehb
DMT
2
#
dmt
v0
/*
* We don't know a priori if ra is "live"
...
...
@@ -495,7 +495,7 @@
xori
t0
,
0x1e
mtc0
t0
,
CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
ehb
_
ehb
andi
v0
,
v0
,
VPECONTROL_TE
beqz
v0
,
2
f
nop
/* delay slot */
...
...
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