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提交 3f9ab1ee 编写于 作者: M Mike McCormack 提交者： Greg Kroah-Hartman
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staging: rtl8192e: Use private structure in IO functions 

The current ieee80211 library does not pass net_device structures
around. Switch code to use private data structure to get I/O addresses.
Signed-off-by: NMike McCormack <mikem@ring3k.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 427bf120
展开全部 隐藏空白更改
内联 并排
Showing with 397 addition and 376 deletion
drivers/staging/rtl8192e/r8180_93cx6.c
浏览文件 @ 3f9ab1ee
...@@ -20,49 +20,49 @@ ...@@ -20,49 +20,49 @@
#include "r8180_93cx6.h" #include "r8180_93cx6.h"
static void eprom_cs(struct net_device *dev, short bit) static void eprom_cs(struct r8192_priv *priv, short bit)
{ {
if (bit) if (bit)
write_nic_byte(dev, EPROM_CMD, write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CS_SHIFT) | (1<<EPROM_CS_SHIFT) |
read_nic_byte(dev, EPROM_CMD)); //enable EPROM read_nic_byte(priv, EPROM_CMD)); //enable EPROM
else else
write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD) write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_CS_SHIFT)); //disable EPROM &~(1<<EPROM_CS_SHIFT)); //disable EPROM
udelay(EPROM_DELAY); udelay(EPROM_DELAY);
} }
static void eprom_ck_cycle(struct net_device *dev) static void eprom_ck_cycle(struct r8192_priv *priv)
{ {
write_nic_byte(dev, EPROM_CMD, write_nic_byte(priv, EPROM_CMD,
(1<<EPROM_CK_SHIFT) | read_nic_byte(dev, EPROM_CMD)); (1<<EPROM_CK_SHIFT) | read_nic_byte(priv, EPROM_CMD));
udelay(EPROM_DELAY); udelay(EPROM_DELAY);
write_nic_byte(dev, EPROM_CMD, write_nic_byte(priv, EPROM_CMD,
read_nic_byte(dev, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT)); read_nic_byte(priv, EPROM_CMD) & ~(1<<EPROM_CK_SHIFT));
udelay(EPROM_DELAY); udelay(EPROM_DELAY);
} }
static void eprom_w(struct net_device *dev, short bit) static void eprom_w(struct r8192_priv *priv, short bit)
{ {
if (bit) if (bit)
write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | write_nic_byte(priv, EPROM_CMD, (1<<EPROM_W_SHIFT) |
read_nic_byte(dev, EPROM_CMD)); read_nic_byte(priv, EPROM_CMD));
else else
write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD) write_nic_byte(priv, EPROM_CMD, read_nic_byte(priv, EPROM_CMD)
&~(1<<EPROM_W_SHIFT)); &~(1<<EPROM_W_SHIFT));
udelay(EPROM_DELAY); udelay(EPROM_DELAY);
} }
static short eprom_r(struct net_device *dev) static short eprom_r(struct r8192_priv *priv)
{ {
short bit; short bit;
bit = (read_nic_byte(dev, EPROM_CMD) & (1<<EPROM_R_SHIFT)); bit = (read_nic_byte(priv, EPROM_CMD) & (1<<EPROM_R_SHIFT));
udelay(EPROM_DELAY); udelay(EPROM_DELAY);
if (bit) if (bit)
...@@ -71,13 +71,13 @@ static short eprom_r(struct net_device *dev) ...@@ -71,13 +71,13 @@ static short eprom_r(struct net_device *dev)
} }
static void eprom_send_bits_string(struct net_device *dev, short b[], int len) static void eprom_send_bits_string(struct r8192_priv *priv, short b[], int len)
{ {
int i; int i;
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
eprom_w(dev, b[i]); eprom_w(priv, b[i]);
eprom_ck_cycle(dev); eprom_ck_cycle(priv);
} }
} }
...@@ -93,7 +93,7 @@ u32 eprom_read(struct net_device *dev, u32 addr) ...@@ -93,7 +93,7 @@ u32 eprom_read(struct net_device *dev, u32 addr)
ret = 0; ret = 0;
//enable EPROM programming //enable EPROM programming
write_nic_byte(dev, EPROM_CMD, write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT)); (EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
udelay(EPROM_DELAY); udelay(EPROM_DELAY);
...@@ -116,27 +116,27 @@ u32 eprom_read(struct net_device *dev, u32 addr) ...@@ -116,27 +116,27 @@ u32 eprom_read(struct net_device *dev, u32 addr)
addr_str[0] = addr & (1<<5); addr_str[0] = addr & (1<<5);
addr_len = 6; addr_len = 6;
} }
eprom_cs(dev, 1); eprom_cs(priv, 1);
eprom_ck_cycle(dev); eprom_ck_cycle(priv);
eprom_send_bits_string(dev, read_cmd, 3); eprom_send_bits_string(priv, read_cmd, 3);
eprom_send_bits_string(dev, addr_str, addr_len); eprom_send_bits_string(priv, addr_str, addr_len);
//keep chip pin D to low state while reading. //keep chip pin D to low state while reading.
//I'm unsure if it is necessary, but anyway shouldn't hurt //I'm unsure if it is necessary, but anyway shouldn't hurt
eprom_w(dev, 0); eprom_w(priv, 0);
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
//eeprom needs a clk cycle between writing opcode&adr //eeprom needs a clk cycle between writing opcode&adr
//and reading data. (eeprom outs a dummy 0) //and reading data. (eeprom outs a dummy 0)
eprom_ck_cycle(dev); eprom_ck_cycle(priv);
ret |= (eprom_r(dev)<<(15-i)); ret |= (eprom_r(priv)<<(15-i));
} }
eprom_cs(dev, 0); eprom_cs(priv, 0);
eprom_ck_cycle(dev); eprom_ck_cycle(priv);
//disable EPROM programming //disable EPROM programming
write_nic_byte(dev, EPROM_CMD, write_nic_byte(priv, EPROM_CMD,
(EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT)); (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
return ret; return ret;
} }
drivers/staging/rtl8192e/r8190_rtl8256.c
浏览文件 @ 3f9ab1ee
...@@ -273,7 +273,7 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel) ...@@ -273,7 +273,7 @@ void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
} }
} }
TxAGC = (byte1<<8) |byte0; TxAGC = (byte1<<8) |byte0;
write_nic_dword(dev, CCK_TXAGC, TxAGC); write_nic_dword(priv, CCK_TXAGC, TxAGC);
#else #else
#ifdef RTL8192E #ifdef RTL8192E
...@@ -364,8 +364,8 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel) ...@@ -364,8 +364,8 @@ void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
//DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp); //DbgPrint("TxAGC2_tmp = 0x%x\n", TxAGC2_tmp);
//DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2); //DbgPrint("TxAGC1/TxAGC2 = 0x%x/0x%x\n", TxAGC1, TxAGC2);
write_nic_dword(dev, MCS_TXAGC, TxAGC1); write_nic_dword(priv, MCS_TXAGC, TxAGC1);
write_nic_dword(dev, MCS_TXAGC+4, TxAGC2); write_nic_dword(priv, MCS_TXAGC+4, TxAGC2);
#else #else
#ifdef RTL8192E #ifdef RTL8192E
u32 writeVal, powerBase0, powerBase1, writeVal_tmp; u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
...@@ -513,8 +513,8 @@ SetRFPowerState8190( ...@@ -513,8 +513,8 @@ SetRFPowerState8190(
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} else { } else {
write_nic_byte(dev, ANAPAR, 0x37);//160MHz write_nic_byte(priv, ANAPAR, 0x37);//160MHz
//write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403 //write_nic_byte(priv, MacBlkCtrl, 0x17); // 0x403
mdelay(1); mdelay(1);
//enable clock 80/88 MHz //enable clock 80/88 MHz
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2] rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
...@@ -536,7 +536,7 @@ SetRFPowerState8190( ...@@ -536,7 +536,7 @@ SetRFPowerState8190(
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
// Baseband reset 2008.09.30 add // Baseband reset 2008.09.30 add
//write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0)); //write_nic_byte(priv, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0));
//2 AFE //2 AFE
// 2008.09.30 add // 2008.09.30 add
...@@ -774,12 +774,12 @@ MgntDisconnectIBSS( ...@@ -774,12 +774,12 @@ MgntDisconnectIBSS(
// PlatformZeroMemory( pMgntInfo->Bssid, 6 ); // PlatformZeroMemory( pMgntInfo->Bssid, 6 );
for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55; for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i]= 0x55;
priv->OpMode = RT_OP_MODE_NO_LINK; priv->OpMode = RT_OP_MODE_NO_LINK;
write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]); write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]); write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
{ {
RT_OP_MODE OpMode = priv->OpMode; RT_OP_MODE OpMode = priv->OpMode;
//LED_CTL_MODE LedAction = LED_CTL_NO_LINK; //LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
u8 btMsr = read_nic_byte(dev, MSR); u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc; btMsr &= 0xfc;
...@@ -805,7 +805,7 @@ MgntDisconnectIBSS( ...@@ -805,7 +805,7 @@ MgntDisconnectIBSS(
break; break;
} }
write_nic_byte(dev, MSR, btMsr); write_nic_byte(priv, MSR, btMsr);
// LED control // LED control
//Adapter->HalFunc.LedControlHandler(Adapter, LedAction); //Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
...@@ -817,7 +817,7 @@ MgntDisconnectIBSS( ...@@ -817,7 +817,7 @@ MgntDisconnectIBSS(
{ {
u32 RegRCR, Type; u32 RegRCR, Type;
Type = bFilterOutNonAssociatedBSSID; Type = bFilterOutNonAssociatedBSSID;
RegRCR = read_nic_dword(dev,RCR); RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR; priv->ReceiveConfig = RegRCR;
if (Type == true) if (Type == true)
RegRCR |= (RCR_CBSSID); RegRCR |= (RCR_CBSSID);
...@@ -825,7 +825,7 @@ MgntDisconnectIBSS( ...@@ -825,7 +825,7 @@ MgntDisconnectIBSS(
RegRCR &= (~RCR_CBSSID); RegRCR &= (~RCR_CBSSID);
{ {
write_nic_dword(dev, RCR,RegRCR); write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR; priv->ReceiveConfig = RegRCR;
} }
...@@ -862,7 +862,7 @@ MlmeDisassociateRequest( ...@@ -862,7 +862,7 @@ MlmeDisassociateRequest(
{ {
RT_OP_MODE OpMode = priv->OpMode; RT_OP_MODE OpMode = priv->OpMode;
//LED_CTL_MODE LedAction = LED_CTL_NO_LINK; //LED_CTL_MODE LedAction = LED_CTL_NO_LINK;
u8 btMsr = read_nic_byte(dev, MSR); u8 btMsr = read_nic_byte(priv, MSR);
btMsr &= 0xfc; btMsr &= 0xfc;
...@@ -888,15 +888,15 @@ MlmeDisassociateRequest( ...@@ -888,15 +888,15 @@ MlmeDisassociateRequest(
break; break;
} }
write_nic_byte(dev, MSR, btMsr); write_nic_byte(priv, MSR, btMsr);
// LED control // LED control
//Adapter->HalFunc.LedControlHandler(Adapter, LedAction); //Adapter->HalFunc.LedControlHandler(Adapter, LedAction);
} }
ieee80211_disassociate(priv->ieee80211); ieee80211_disassociate(priv->ieee80211);
write_nic_word(dev, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]); write_nic_word(priv, BSSIDR, ((u16*)priv->ieee80211->current_network.bssid)[0]);
write_nic_dword(dev, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]); write_nic_dword(priv, BSSIDR+2, ((u32*)(priv->ieee80211->current_network.bssid+2))[0]);
} }
...@@ -935,7 +935,7 @@ MgntDisconnectAP( ...@@ -935,7 +935,7 @@ MgntDisconnectAP(
Type = bFilterOutNonAssociatedBSSID; Type = bFilterOutNonAssociatedBSSID;
//Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RCR, (pu1Byte)(&RegRCR)); //Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RCR, (pu1Byte)(&RegRCR));
RegRCR = read_nic_dword(dev,RCR); RegRCR = read_nic_dword(priv, RCR);
priv->ReceiveConfig = RegRCR; priv->ReceiveConfig = RegRCR;
if (Type == true) if (Type == true)
...@@ -943,7 +943,7 @@ MgntDisconnectAP( ...@@ -943,7 +943,7 @@ MgntDisconnectAP(
else if (Type == false) else if (Type == false)
RegRCR &= (~RCR_CBSSID); RegRCR &= (~RCR_CBSSID);
write_nic_dword(dev, RCR,RegRCR); write_nic_dword(priv, RCR, RegRCR);
priv->ReceiveConfig = RegRCR; priv->ReceiveConfig = RegRCR;
......
drivers/staging/rtl8192e/r8192E.h
浏览文件 @ 3f9ab1ee
...@@ -1052,16 +1052,16 @@ typedef struct r8192_priv ...@@ -1052,16 +1052,16 @@ typedef struct r8192_priv
bool init_firmware(struct net_device *dev); bool init_firmware(struct net_device *dev);
short rtl8192_tx(struct net_device *dev, struct sk_buff* skb); short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
u32 read_cam(struct net_device *dev, u8 addr); u32 read_cam(struct r8192_priv *priv, u8 addr);
void write_cam(struct net_device *dev, u8 addr, u32 data); void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
u8 read_nic_byte(struct net_device *dev, int x); u8 read_nic_byte(struct r8192_priv *priv, int x);
u8 read_nic_byte_E(struct net_device *dev, int x); u8 read_nic_byte_E(struct net_device *dev, int x);
u32 read_nic_dword(struct net_device *dev, int x); u32 read_nic_dword(struct r8192_priv *priv, int x);
u16 read_nic_word(struct net_device *dev, int x) ; u16 read_nic_word(struct r8192_priv *priv, int x) ;
void write_nic_byte(struct net_device *dev, int x,u8 y); void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
void write_nic_byte_E(struct net_device *dev, int x,u8 y); void write_nic_byte_E(struct net_device *priv, int x,u8 y);
void write_nic_word(struct net_device *dev, int x,u16 y); void write_nic_word(struct r8192_priv *priv, int x,u16 y);
void write_nic_dword(struct net_device *dev, int x,u32 y); void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
void rtl8192_halt_adapter(struct net_device *dev, bool reset); void rtl8192_halt_adapter(struct net_device *dev, bool reset);
void rtl8192_rx_enable(struct net_device *); void rtl8192_rx_enable(struct net_device *);
......
drivers/staging/rtl8192e/r8192E_wx.c
浏览文件 @ 3f9ab1ee
...@@ -985,7 +985,7 @@ static int r8192_wx_set_enc_ext(struct net_device *dev, ...@@ -985,7 +985,7 @@ static int r8192_wx_set_enc_ext(struct net_device *dev,
else //pairwise key else //pairwise key
{ {
if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){ if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport){
write_nic_byte(dev, 0x173, 1); //fix aes bug write_nic_byte(priv, 0x173, 1); //fix aes bug
} }
setKey( dev, setKey( dev,
4,//EntryNo 4,//EntryNo
......
drivers/staging/rtl8192e/r8192_pm.c
浏览文件 @ 3f9ab1ee
...@@ -43,7 +43,7 @@ int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state) ...@@ -43,7 +43,7 @@ int rtl8192E_suspend (struct pci_dev *pdev, pm_message_t state)
ieee80211_softmac_stop_protocol(priv->ieee80211); ieee80211_softmac_stop_protocol(priv->ieee80211);
write_nic_byte(dev,MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE); write_nic_byte(priv, MSR,(read_nic_byte(dev,MSR)&0xfc)|MSR_LINK_NONE);
if(!priv->ieee80211->bSupportRemoteWakeUp) { if(!priv->ieee80211->bSupportRemoteWakeUp) {
/* disable tx/rx. In 8185 we write 0x10 (Reset bit), /* disable tx/rx. In 8185 we write 0x10 (Reset bit),
* but here we make reference to WMAC and wirte 0x0. * but here we make reference to WMAC and wirte 0x0.
...@@ -76,24 +76,24 @@ pHalData->bHwRfOffAction = 2; ...@@ -76,24 +76,24 @@ pHalData->bHwRfOffAction = 2;
if(!priv->ieee80211->bSupportRemoteWakeUp) { if(!priv->ieee80211->bSupportRemoteWakeUp) {
MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT); MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_INIT);
// 2006.11.30. System reset bit // 2006.11.30. System reset bit
ulRegRead = read_nic_dword(dev, CPU_GEN); ulRegRead = read_nic_dword(priv, CPU_GEN);
ulRegRead|=CPU_GEN_SYSTEM_RESET; ulRegRead|=CPU_GEN_SYSTEM_RESET;
write_nic_dword(dev, CPU_GEN, ulRegRead); write_nic_dword(priv, CPU_GEN, ulRegRead);
} else { } else {
//2008.06.03 for WOL //2008.06.03 for WOL
write_nic_dword(dev, WFCRC0, 0xffffffff); write_nic_dword(priv, WFCRC0, 0xffffffff);
write_nic_dword(dev, WFCRC1, 0xffffffff); write_nic_dword(priv, WFCRC1, 0xffffffff);
write_nic_dword(dev, WFCRC2, 0xffffffff); write_nic_dword(priv, WFCRC2, 0xffffffff);
#ifdef RTL8190P #ifdef RTL8190P
//GPIO 0 = TRUE //GPIO 0 = TRUE
ucRegRead = read_nic_byte(dev, GPO); ucRegRead = read_nic_byte(priv, GPO);
ucRegRead |= BIT0; ucRegRead |= BIT0;
write_nic_byte(dev, GPO, ucRegRead); write_nic_byte(priv, GPO, ucRegRead);
#endif #endif
//Write PMR register //Write PMR register
write_nic_byte(dev, PMR, 0x5); write_nic_byte(priv, PMR, 0x5);
//Disable tx, enanble rx //Disable tx, enanble rx
write_nic_byte(dev, MacBlkCtrl, 0xa); write_nic_byte(priv, MacBlkCtrl, 0xa);
} }
out_pci_suspend: out_pci_suspend:
......
drivers/staging/rtl8192e/r819xE_firmware.c
浏览文件 @ 3f9ab1ee
...@@ -115,6 +115,7 @@ static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, ...@@ -115,6 +115,7 @@ static bool fw_download_code(struct net_device *dev, u8 *code_virtual_address,
*/ */
static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
{ {
struct r8192_priv *priv = ieee80211_priv(dev);
unsigned long timeout; unsigned long timeout;
bool rt_status = true; bool rt_status = true;
u32 CPU_status = 0; u32 CPU_status = 0;
...@@ -122,7 +123,7 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) ...@@ -122,7 +123,7 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
/* Check whether put code OK */ /* Check whether put code OK */
timeout = jiffies + msecs_to_jiffies(20); timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
CPU_status = read_nic_dword(dev, CPU_GEN); CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_PUT_CODE_OK) if (CPU_status & CPU_GEN_PUT_CODE_OK)
break; break;
...@@ -137,15 +138,15 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) ...@@ -137,15 +138,15 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
} }
/* Turn On CPU */ /* Turn On CPU */
CPU_status = read_nic_dword(dev, CPU_GEN); CPU_status = read_nic_dword(priv, CPU_GEN);
write_nic_byte(dev, CPU_GEN, write_nic_byte(priv, CPU_GEN,
(u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff)); (u8)((CPU_status | CPU_GEN_PWR_STB_CPU) & 0xff));
mdelay(1); mdelay(1);
/* Check whether CPU boot OK */ /* Check whether CPU boot OK */
timeout = jiffies + msecs_to_jiffies(20); timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
CPU_status = read_nic_dword(dev, CPU_GEN); CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_BOOT_RDY) if (CPU_status & CPU_GEN_BOOT_RDY)
break; break;
...@@ -167,6 +168,7 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev) ...@@ -167,6 +168,7 @@ static bool CPUcheck_maincodeok_turnonCPU(struct net_device *dev)
static bool CPUcheck_firmware_ready(struct net_device *dev) static bool CPUcheck_firmware_ready(struct net_device *dev)
{ {
struct r8192_priv *priv = ieee80211_priv(dev);
unsigned long timeout; unsigned long timeout;
bool rt_status = true; bool rt_status = true;
u32 CPU_status = 0; u32 CPU_status = 0;
...@@ -174,7 +176,7 @@ static bool CPUcheck_firmware_ready(struct net_device *dev) ...@@ -174,7 +176,7 @@ static bool CPUcheck_firmware_ready(struct net_device *dev)
/* Check Firmware Ready */ /* Check Firmware Ready */
timeout = jiffies + msecs_to_jiffies(20); timeout = jiffies + msecs_to_jiffies(20);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
CPU_status = read_nic_dword(dev, CPU_GEN); CPU_status = read_nic_dword(priv, CPU_GEN);
if (CPU_status & CPU_GEN_FIRM_RDY) if (CPU_status & CPU_GEN_FIRM_RDY)
break; break;
......
drivers/staging/rtl8192e/r819xE_phy.c
浏览文件 @ 3f9ab1ee
...@@ -1466,17 +1466,17 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) ...@@ -1466,17 +1466,17 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
* ****************************************************************************/ * ****************************************************************************/
void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
{ {
struct r8192_priv *priv = ieee80211_priv(dev);
u32 OriginalValue, BitShift, NewValue; u32 OriginalValue, BitShift, NewValue;
if(dwBitMask!= bMaskDWord) if(dwBitMask!= bMaskDWord)
{//if not "double word" write {//if not "double word" write
OriginalValue = read_nic_dword(dev, dwRegAddr); OriginalValue = read_nic_dword(priv, dwRegAddr);
BitShift = rtl8192_CalculateBitShift(dwBitMask); BitShift = rtl8192_CalculateBitShift(dwBitMask);
NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
write_nic_dword(dev, dwRegAddr, NewValue); write_nic_dword(priv, dwRegAddr, NewValue);
}else }else
write_nic_dword(dev, dwRegAddr, dwData); write_nic_dword(priv, dwRegAddr, dwData);
} }
/****************************************************************************** /******************************************************************************
*function: This function reads specific bits from BB register *function: This function reads specific bits from BB register
...@@ -1489,9 +1489,10 @@ void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 ...@@ -1489,9 +1489,10 @@ void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32
* ****************************************************************************/ * ****************************************************************************/
u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
{ {
struct r8192_priv *priv = ieee80211_priv(dev);
u32 OriginalValue, BitShift; u32 OriginalValue, BitShift;
OriginalValue = read_nic_dword(dev, dwRegAddr); OriginalValue = read_nic_dword(priv, dwRegAddr);
BitShift = rtl8192_CalculateBitShift(dwBitMask); BitShift = rtl8192_CalculateBitShift(dwBitMask);
return (OriginalValue & dwBitMask) >> BitShift; return (OriginalValue & dwBitMask) >> BitShift;
} }
...@@ -1808,6 +1809,7 @@ static u32 phy_FwRFSerialRead( ...@@ -1808,6 +1809,7 @@ static u32 phy_FwRFSerialRead(
RF90_RADIO_PATH_E eRFPath, RF90_RADIO_PATH_E eRFPath,
u32 Offset ) u32 Offset )
{ {
struct r8192_priv *priv = ieee80211_priv(dev);
u32 Data = 0; u32 Data = 0;
u8 time = 0; u8 time = 0;
//DbgPrint("FW RF CTRL\n\r"); //DbgPrint("FW RF CTRL\n\r");
...@@ -1825,7 +1827,7 @@ static u32 phy_FwRFSerialRead( ...@@ -1825,7 +1827,7 @@ static u32 phy_FwRFSerialRead(
// 5. Trigger Fw to operate the command. bit 31 // 5. Trigger Fw to operate the command. bit 31
Data |= 0x80000000; Data |= 0x80000000;
// 6. We can not execute read operation if bit 31 is 1. // 6. We can not execute read operation if bit 31 is 1.
while (read_nic_dword(dev, QPNR)&0x80000000) while (read_nic_dword(priv, QPNR)&0x80000000)
{ {
// If FW can not finish RF-R/W for more than ?? times. We must reset FW. // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100) if (time++ < 100)
...@@ -1837,9 +1839,9 @@ static u32 phy_FwRFSerialRead( ...@@ -1837,9 +1839,9 @@ static u32 phy_FwRFSerialRead(
break; break;
} }
// 7. Execute read operation. // 7. Execute read operation.
write_nic_dword(dev, QPNR, Data); write_nic_dword(priv, QPNR, Data);
// 8. Check if firmawre send back RF content. // 8. Check if firmawre send back RF content.
while (read_nic_dword(dev, QPNR)&0x80000000) while (read_nic_dword(priv, QPNR)&0x80000000)
{ {
// If FW can not finish RF-R/W for more than ?? times. We must reset FW. // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100) if (time++ < 100)
...@@ -1850,7 +1852,7 @@ static u32 phy_FwRFSerialRead( ...@@ -1850,7 +1852,7 @@ static u32 phy_FwRFSerialRead(
else else
return 0; return 0;
} }
return read_nic_dword(dev, RF_DATA); return read_nic_dword(priv, RF_DATA);
} }
/****************************************************************************** /******************************************************************************
...@@ -1867,6 +1869,7 @@ phy_FwRFSerialWrite( ...@@ -1867,6 +1869,7 @@ phy_FwRFSerialWrite(
u32 Offset, u32 Offset,
u32 Data ) u32 Data )
{ {
struct r8192_priv *priv = ieee80211_priv(dev);
u8 time = 0; u8 time = 0;
//DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
...@@ -1886,7 +1889,7 @@ phy_FwRFSerialWrite( ...@@ -1886,7 +1889,7 @@ phy_FwRFSerialWrite(
Data |= 0x80000000; Data |= 0x80000000;
// 6. Write operation. We can not write if bit 31 is 1. // 6. Write operation. We can not write if bit 31 is 1.
while (read_nic_dword(dev, QPNR)&0x80000000) while (read_nic_dword(priv, QPNR)&0x80000000)
{ {
// If FW can not finish RF-R/W for more than ?? times. We must reset FW. // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
if (time++ < 100) if (time++ < 100)
...@@ -1899,7 +1902,7 @@ phy_FwRFSerialWrite( ...@@ -1899,7 +1902,7 @@ phy_FwRFSerialWrite(
} }
// 7. No matter check bit. We always force the write. Because FW will // 7. No matter check bit. We always force the write. Because FW will
// not accept the command. // not accept the command.
write_nic_dword(dev, QPNR, Data); write_nic_dword(priv, QPNR, Data);
/* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
to finish RF write operation. */ to finish RF write operation. */
/* 2008/01/17 MH We support delay in firmware side now. */ /* 2008/01/17 MH We support delay in firmware side now. */
...@@ -2151,7 +2154,7 @@ static void rtl8192_InitBBRFRegDef(struct net_device* dev) ...@@ -2151,7 +2154,7 @@ static void rtl8192_InitBBRFRegDef(struct net_device* dev)
* ***************************************************************************/ * ***************************************************************************/
RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
{ {
//struct r8192_priv *priv = ieee80211_priv(dev); struct r8192_priv *priv = ieee80211_priv(dev);
// BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
RT_STATUS ret = RT_STATUS_SUCCESS; RT_STATUS ret = RT_STATUS_SUCCESS;
u32 i, CheckTimes = 4, dwRegRead = 0; u32 i, CheckTimes = 4, dwRegRead = 0;
...@@ -2177,8 +2180,8 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo ...@@ -2177,8 +2180,8 @@ RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlo
case HW90_BLOCK_PHY0: case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1: case HW90_BLOCK_PHY1:
write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
break; break;
case HW90_BLOCK_RF: case HW90_BLOCK_RF:
...@@ -2230,12 +2233,12 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) ...@@ -2230,12 +2233,12 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
**************************************/ **************************************/
/*--set BB Global Reset--*/ /*--set BB Global Reset--*/
bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
/*---set BB reset Active---*/ /*---set BB reset Active---*/
dwRegValue = read_nic_dword(dev, CPU_GEN); dwRegValue = read_nic_dword(priv, CPU_GEN);
write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
/*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
// TODO: this function should be removed on ASIC , Emily 2007.2.2 // TODO: this function should be removed on ASIC , Emily 2007.2.2
...@@ -2255,8 +2258,8 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev) ...@@ -2255,8 +2258,8 @@ static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
/*----Set BB reset de-Active----*/ /*----Set BB reset de-Active----*/
dwRegValue = read_nic_dword(dev, CPU_GEN); dwRegValue = read_nic_dword(priv, CPU_GEN);
write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
/*----BB AGC table Initialization----*/ /*----BB AGC table Initialization----*/
//==m==>Set PHY REG From Header<==m== //==m==>Set PHY REG From Header<==m==
...@@ -2324,44 +2327,44 @@ void rtl8192_phy_getTxPower(struct net_device* dev) ...@@ -2324,44 +2327,44 @@ void rtl8192_phy_getTxPower(struct net_device* dev)
struct r8192_priv *priv = ieee80211_priv(dev); struct r8192_priv *priv = ieee80211_priv(dev);
#ifdef RTL8190P #ifdef RTL8190P
priv->MCSTxPowerLevelOriginalOffset[0] = priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(dev, MCS_TXAGC); read_nic_dword(priv, MCS_TXAGC);
priv->MCSTxPowerLevelOriginalOffset[1] = priv->MCSTxPowerLevelOriginalOffset[1] =
read_nic_dword(dev, (MCS_TXAGC+4)); read_nic_dword(priv, (MCS_TXAGC+4));
priv->CCKTxPowerLevelOriginalOffset = priv->CCKTxPowerLevelOriginalOffset =
read_nic_dword(dev, CCK_TXAGC); read_nic_dword(priv, CCK_TXAGC);
#else #else
#ifdef RTL8192E #ifdef RTL8192E
priv->MCSTxPowerLevelOriginalOffset[0] = priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(dev, rTxAGC_Rate18_06); read_nic_dword(priv, rTxAGC_Rate18_06);
priv->MCSTxPowerLevelOriginalOffset[1] = priv->MCSTxPowerLevelOriginalOffset[1] =
read_nic_dword(dev, rTxAGC_Rate54_24); read_nic_dword(priv, rTxAGC_Rate54_24);
priv->MCSTxPowerLevelOriginalOffset[2] = priv->MCSTxPowerLevelOriginalOffset[2] =
read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
priv->MCSTxPowerLevelOriginalOffset[3] = priv->MCSTxPowerLevelOriginalOffset[3] =
read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
priv->MCSTxPowerLevelOriginalOffset[4] = priv->MCSTxPowerLevelOriginalOffset[4] =
read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
priv->MCSTxPowerLevelOriginalOffset[5] = priv->MCSTxPowerLevelOriginalOffset[5] =
read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
#endif #endif
#endif #endif
// read rx initial gain // read rx initial gain
priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
// read framesync // read framesync
priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
rOFDM0_RxDetector3, priv->framesync); rOFDM0_RxDetector3, priv->framesync);
// read SIFS (save the value read fome MACPHY_REG.txt) // read SIFS (save the value read fome MACPHY_REG.txt)
priv->SifsTime = read_nic_word(dev, SIFS); priv->SifsTime = read_nic_word(priv, SIFS);
} }
/****************************************************************************** /******************************************************************************
...@@ -2807,13 +2810,13 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s ...@@ -2807,13 +2810,13 @@ static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* s
rtl8192_SetTxPowerLevel(dev,channel); rtl8192_SetTxPowerLevel(dev,channel);
break; break;
case CmdID_WritePortUlong: case CmdID_WritePortUlong:
write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
break; break;
case CmdID_WritePortUshort: case CmdID_WritePortUshort:
write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
break; break;
case CmdID_WritePortUchar: case CmdID_WritePortUchar:
write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
break; break;
case CmdID_RF_WriteReg: case CmdID_RF_WriteReg:
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
...@@ -3080,20 +3083,20 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) ...@@ -3080,20 +3083,20 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
return; return;
} }
//<1>Set MAC register //<1>Set MAC register
regBwOpMode = read_nic_byte(dev, BW_OPMODE); regBwOpMode = read_nic_byte(priv, BW_OPMODE);
switch(priv->CurrentChannelBW) switch(priv->CurrentChannelBW)
{ {
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ; regBwOpMode |= BW_OPMODE_20MHZ;
// 2007/02/07 Mark by Emily becasue we have not verify whether this register works // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
write_nic_byte(dev, BW_OPMODE, regBwOpMode); write_nic_byte(priv, BW_OPMODE, regBwOpMode);
break; break;
case HT_CHANNEL_WIDTH_20_40: case HT_CHANNEL_WIDTH_20_40:
regBwOpMode &= ~BW_OPMODE_20MHZ; regBwOpMode &= ~BW_OPMODE_20MHZ;
// 2007/02/07 Mark by Emily becasue we have not verify whether this register works // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
write_nic_byte(dev, BW_OPMODE, regBwOpMode); write_nic_byte(priv, BW_OPMODE, regBwOpMode);
break; break;
default: default:
...@@ -3116,9 +3119,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) ...@@ -3116,9 +3119,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
// write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
if(!priv->btxpower_tracking) if(!priv->btxpower_tracking)
{ {
write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
} }
else else
CCK_Tx_Power_Track_BW_Switch(dev); CCK_Tx_Power_Track_BW_Switch(dev);
...@@ -3147,9 +3150,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) ...@@ -3147,9 +3150,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
//write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
if(!priv->btxpower_tracking) if(!priv->btxpower_tracking)
{ {
write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000); write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e); write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
write_nic_dword(dev, rCCK0_DebugPort, 0x00000409); write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
} }
else else
CCK_Tx_Power_Track_BW_Switch(dev); CCK_Tx_Power_Track_BW_Switch(dev);
...@@ -3288,12 +3291,12 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation) ...@@ -3288,12 +3291,12 @@ void InitialGain819xPci(struct net_device *dev, u8 Operation)
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
break; break;
case IG_Restore: case IG_Restore:
RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
......
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