提交 3a1ce8aa 编写于 作者: M Marcelo Tosatti 提交者: Linus Torvalds

[PATCH] ppc32: 8xx: update DataTLBMiss exception comment

On PPC 8xx, the DataTLBMiss handler does not jump directly to the page
fault handler, as was the case in v2.4.

It instead loads an invalid TLB which causes a subsequent DataTLBError
exception.

The comment on top of it haven't been update to reflect the change, though.
Signed-off-by: NMarcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
上级 13e886c3
...@@ -288,13 +288,11 @@ SystemCall: ...@@ -288,13 +288,11 @@ SystemCall:
* For the MPC8xx, this is a software tablewalk to load the instruction * For the MPC8xx, this is a software tablewalk to load the instruction
* TLB. It is modelled after the example in the Motorola manual. The task * TLB. It is modelled after the example in the Motorola manual. The task
* switch loads the M_TWB register with the pointer to the first level table. * switch loads the M_TWB register with the pointer to the first level table.
* If we discover there is no second level table (the value is zero), the * If we discover there is no second level table (value is zero) or if there
* plan was to load that into the TLB, which causes another fault into the * is an invalid pte, we load that into the TLB, which causes another fault
* TLB Error interrupt where we can handle such problems. However, that did * into the TLB Error interrupt where we can handle such problems.
* not work, so if we discover there is no second level table, we restore * We have to use the MD_xxx registers for the tablewalk because the
* registers and branch to the error exception. We have to use the MD_xxx * equivalent MI_xxx registers only perform the attribute functions.
* registers for the tablewalk because the equivalent MI_xxx registers
* only perform the attribute functions.
*/ */
InstructionTLBMiss: InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6 #ifdef CONFIG_8xx_CPU6
......
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