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35bcf5d5
编写于
4月 30, 2012
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau: move flip-related channel setup to software engine
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
20abd163
变更
8
隐藏空白更改
内联
并排
Showing
8 changed file
with
84 addition
and
62 deletion
+84
-62
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_drv.h
+0
-2
drivers/gpu/drm/nouveau/nouveau_object.c
drivers/gpu/drm/nouveau/nouveau_object.c
+3
-55
drivers/gpu/drm/nouveau/nouveau_software.h
drivers/gpu/drm/nouveau/nouveau_software.h
+1
-0
drivers/gpu/drm/nouveau/nv04_software.c
drivers/gpu/drm/nouveau/nv04_software.c
+1
-0
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nv50_display.c
+2
-1
drivers/gpu/drm/nouveau/nv50_software.c
drivers/gpu/drm/nouveau/nv50_software.c
+26
-2
drivers/gpu/drm/nouveau/nvc0_software.c
drivers/gpu/drm/nouveau/nvc0_software.c
+48
-1
drivers/gpu/drm/nouveau/nvd0_display.c
drivers/gpu/drm/nouveau/nvd0_display.c
+3
-1
未找到文件。
drivers/gpu/drm/nouveau/nouveau_drv.h
浏览文件 @
35bcf5d5
...
@@ -295,8 +295,6 @@ struct nouveau_channel {
...
@@ -295,8 +295,6 @@ struct nouveau_channel {
uint32_t
sw_subchannel
[
8
];
uint32_t
sw_subchannel
[
8
];
struct
nouveau_vma
dispc_vma
[
4
];
struct
{
struct
{
bool
active
;
bool
active
;
char
name
[
32
];
char
name
[
32
];
...
...
drivers/gpu/drm/nouveau/nouveau_object.c
浏览文件 @
35bcf5d5
...
@@ -37,7 +37,6 @@
...
@@ -37,7 +37,6 @@
#include "nouveau_ramht.h"
#include "nouveau_ramht.h"
#include "nouveau_software.h"
#include "nouveau_software.h"
#include "nouveau_vm.h"
#include "nouveau_vm.h"
#include "nv50_display.h"
struct
nouveau_gpuobj_method
{
struct
nouveau_gpuobj_method
{
struct
list_head
head
;
struct
list_head
head
;
...
@@ -556,11 +555,10 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
...
@@ -556,11 +555,10 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
static
int
static
int
nvc0_gpuobj_channel_init
(
struct
nouveau_channel
*
chan
,
struct
nouveau_vm
*
vm
)
nvc0_gpuobj_channel_init
(
struct
nouveau_channel
*
chan
,
struct
nouveau_vm
*
vm
)
{
{
struct
drm_nouveau_private
*
dev_priv
=
chan
->
dev
->
dev_private
;
struct
drm_device
*
dev
=
chan
->
dev
;
struct
drm_device
*
dev
=
chan
->
dev
;
struct
nouveau_gpuobj
*
pgd
=
NULL
;
struct
nouveau_gpuobj
*
pgd
=
NULL
;
struct
nouveau_vm_pgd
*
vpgd
;
struct
nouveau_vm_pgd
*
vpgd
;
int
ret
,
i
;
int
ret
;
ret
=
nouveau_gpuobj_new
(
dev
,
NULL
,
4096
,
0x1000
,
0
,
&
chan
->
ramin
);
ret
=
nouveau_gpuobj_new
(
dev
,
NULL
,
4096
,
0x1000
,
0
,
&
chan
->
ramin
);
if
(
ret
)
if
(
ret
)
...
@@ -585,19 +583,6 @@ nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm)
...
@@ -585,19 +583,6 @@ nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm)
nv_wo32
(
chan
->
ramin
,
0x0208
,
0xffffffff
);
nv_wo32
(
chan
->
ramin
,
0x0208
,
0xffffffff
);
nv_wo32
(
chan
->
ramin
,
0x020c
,
0x000000ff
);
nv_wo32
(
chan
->
ramin
,
0x020c
,
0x000000ff
);
/* map display semaphore buffers into channel's vm */
for
(
i
=
0
;
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nouveau_bo
*
bo
;
if
(
dev_priv
->
card_type
>=
NV_D0
)
bo
=
nvd0_display_crtc_sema
(
dev
,
i
);
else
bo
=
nv50_display
(
dev
)
->
crtc
[
i
].
sem
.
bo
;
ret
=
nouveau_bo_vma_add
(
bo
,
chan
->
vm
,
&
chan
->
dispc_vma
[
i
]);
if
(
ret
)
return
ret
;
}
return
0
;
return
0
;
}
}
...
@@ -610,7 +595,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
...
@@ -610,7 +595,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
struct
nouveau_fpriv
*
fpriv
=
nouveau_fpriv
(
chan
->
file_priv
);
struct
nouveau_fpriv
*
fpriv
=
nouveau_fpriv
(
chan
->
file_priv
);
struct
nouveau_vm
*
vm
=
fpriv
?
fpriv
->
vm
:
dev_priv
->
chan_vm
;
struct
nouveau_vm
*
vm
=
fpriv
?
fpriv
->
vm
:
dev_priv
->
chan_vm
;
struct
nouveau_gpuobj
*
vram
=
NULL
,
*
tt
=
NULL
;
struct
nouveau_gpuobj
*
vram
=
NULL
,
*
tt
=
NULL
;
int
ret
,
i
;
int
ret
;
NV_DEBUG
(
dev
,
"ch%d vram=0x%08x tt=0x%08x
\n
"
,
chan
->
id
,
vram_h
,
tt_h
);
NV_DEBUG
(
dev
,
"ch%d vram=0x%08x tt=0x%08x
\n
"
,
chan
->
id
,
vram_h
,
tt_h
);
if
(
dev_priv
->
card_type
>=
NV_C0
)
if
(
dev_priv
->
card_type
>=
NV_C0
)
...
@@ -658,25 +643,6 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
...
@@ -658,25 +643,6 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
nouveau_gpuobj_ref
(
NULL
,
&
ramht
);
nouveau_gpuobj_ref
(
NULL
,
&
ramht
);
if
(
ret
)
if
(
ret
)
return
ret
;
return
ret
;
/* dma objects for display sync channel semaphore blocks */
for
(
i
=
0
;
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nouveau_gpuobj
*
sem
=
NULL
;
struct
nv50_display_crtc
*
dispc
=
&
nv50_display
(
dev
)
->
crtc
[
i
];
u64
offset
=
dispc
->
sem
.
bo
->
bo
.
offset
;
ret
=
nouveau_gpuobj_dma_new
(
chan
,
0x3d
,
offset
,
0xfff
,
NV_MEM_ACCESS_RW
,
NV_MEM_TARGET_VRAM
,
&
sem
);
if
(
ret
)
return
ret
;
ret
=
nouveau_ramht_insert
(
chan
,
NvEvoSema0
+
i
,
sem
);
nouveau_gpuobj_ref
(
NULL
,
&
sem
);
if
(
ret
)
return
ret
;
}
}
}
/* VRAM ctxdma */
/* VRAM ctxdma */
...
@@ -736,25 +702,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
...
@@ -736,25 +702,7 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
void
void
nouveau_gpuobj_channel_takedown
(
struct
nouveau_channel
*
chan
)
nouveau_gpuobj_channel_takedown
(
struct
nouveau_channel
*
chan
)
{
{
struct
drm_device
*
dev
=
chan
->
dev
;
NV_DEBUG
(
chan
->
dev
,
"ch%d
\n
"
,
chan
->
id
);
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
int
i
;
NV_DEBUG
(
dev
,
"ch%d
\n
"
,
chan
->
id
);
if
(
dev_priv
->
card_type
>=
NV_D0
)
{
for
(
i
=
0
;
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nouveau_bo
*
bo
=
nvd0_display_crtc_sema
(
dev
,
i
);
nouveau_bo_vma_del
(
bo
,
&
chan
->
dispc_vma
[
i
]);
}
}
else
if
(
dev_priv
->
card_type
>=
NV_50
)
{
struct
nv50_display
*
disp
=
nv50_display
(
dev
);
for
(
i
=
0
;
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nv50_display_crtc
*
dispc
=
&
disp
->
crtc
[
i
];
nouveau_bo_vma_del
(
dispc
->
sem
.
bo
,
&
chan
->
dispc_vma
[
i
]);
}
}
nouveau_vm_ref
(
NULL
,
&
chan
->
vm
,
chan
->
vm_pd
);
nouveau_vm_ref
(
NULL
,
&
chan
->
vm
,
chan
->
vm_pd
);
nouveau_gpuobj_ref
(
NULL
,
&
chan
->
vm_pd
);
nouveau_gpuobj_ref
(
NULL
,
&
chan
->
vm_pd
);
...
...
drivers/gpu/drm/nouveau/nouveau_software.h
浏览文件 @
35bcf5d5
...
@@ -64,5 +64,6 @@ nouveau_software_class(struct drm_device *dev)
...
@@ -64,5 +64,6 @@ nouveau_software_class(struct drm_device *dev)
int
nv04_software_create
(
struct
drm_device
*
);
int
nv04_software_create
(
struct
drm_device
*
);
int
nv50_software_create
(
struct
drm_device
*
);
int
nv50_software_create
(
struct
drm_device
*
);
int
nvc0_software_create
(
struct
drm_device
*
);
int
nvc0_software_create
(
struct
drm_device
*
);
u64
nvc0_software_crtc
(
struct
nouveau_channel
*
,
int
crtc
);
#endif
#endif
drivers/gpu/drm/nouveau/nv04_software.c
浏览文件 @
35bcf5d5
...
@@ -23,6 +23,7 @@
...
@@ -23,6 +23,7 @@
*/
*/
#include "drmP.h"
#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_drv.h"
#include "nouveau_ramht.h"
#include "nouveau_ramht.h"
#include "nouveau_software.h"
#include "nouveau_software.h"
...
...
drivers/gpu/drm/nouveau/nv50_display.c
浏览文件 @
35bcf5d5
...
@@ -32,6 +32,7 @@
...
@@ -32,6 +32,7 @@
#include "nouveau_fb.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nouveau_fbcon.h"
#include "nouveau_ramht.h"
#include "nouveau_ramht.h"
#include "nouveau_software.h"
#include "drm_crtc_helper.h"
#include "drm_crtc_helper.h"
static
void
nv50_display_isr
(
struct
drm_device
*
);
static
void
nv50_display_isr
(
struct
drm_device
*
);
...
@@ -491,7 +492,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
...
@@ -491,7 +492,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
else
else
OUT_RING
(
chan
,
chan
->
vram_handle
);
OUT_RING
(
chan
,
chan
->
vram_handle
);
}
else
{
}
else
{
u64
offset
=
chan
->
dispc_vma
[
nv_crtc
->
index
].
offset
;
u64
offset
=
nvc0_software_crtc
(
chan
,
nv_crtc
->
index
)
;
offset
+=
dispc
->
sem
.
offset
;
offset
+=
dispc
->
sem
.
offset
;
BEGIN_NVC0
(
chan
,
0
,
0x0010
,
4
);
BEGIN_NVC0
(
chan
,
0
,
0x0010
,
4
);
OUT_RING
(
chan
,
upper_32_bits
(
offset
));
OUT_RING
(
chan
,
upper_32_bits
(
offset
));
...
...
drivers/gpu/drm/nouveau/nv50_software.c
浏览文件 @
35bcf5d5
...
@@ -23,10 +23,13 @@
...
@@ -23,10 +23,13 @@
*/
*/
#include "drmP.h"
#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_drv.h"
#include "nouveau_ramht.h"
#include "nouveau_ramht.h"
#include "nouveau_software.h"
#include "nouveau_software.h"
#include "nv50_display.h"
struct
nv50_software_priv
{
struct
nv50_software_priv
{
struct
nouveau_software_priv
base
;
struct
nouveau_software_priv
base
;
};
};
...
@@ -103,7 +106,10 @@ mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
...
@@ -103,7 +106,10 @@ mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
static
int
static
int
nv50_software_context_new
(
struct
nouveau_channel
*
chan
,
int
engine
)
nv50_software_context_new
(
struct
nouveau_channel
*
chan
,
int
engine
)
{
{
struct
nv50_software_priv
*
psw
=
nv_engine
(
chan
->
dev
,
NVOBJ_ENGINE_SW
);
struct
nv50_display
*
pdisp
=
nv50_display
(
chan
->
dev
);
struct
nv50_software_chan
*
pch
;
struct
nv50_software_chan
*
pch
;
int
ret
=
0
,
i
;
pch
=
kzalloc
(
sizeof
(
*
pch
),
GFP_KERNEL
);
pch
=
kzalloc
(
sizeof
(
*
pch
),
GFP_KERNEL
);
if
(
!
pch
)
if
(
!
pch
)
...
@@ -111,9 +117,27 @@ nv50_software_context_new(struct nouveau_channel *chan, int engine)
...
@@ -111,9 +117,27 @@ nv50_software_context_new(struct nouveau_channel *chan, int engine)
nouveau_software_context_new
(
&
pch
->
base
);
nouveau_software_context_new
(
&
pch
->
base
);
pch
->
base
.
vblank
.
bo
=
chan
->
notifier_bo
;
pch
->
base
.
vblank
.
bo
=
chan
->
notifier_bo
;
chan
->
engctx
[
engine
]
=
pch
;
chan
->
engctx
[
engine
]
=
pch
;
return
0
;
/* dma objects for display sync channel semaphore blocks */
for
(
i
=
0
;
i
<
chan
->
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nv50_display_crtc
*
dispc
=
&
pdisp
->
crtc
[
i
];
struct
nouveau_gpuobj
*
obj
=
NULL
;
ret
=
nouveau_gpuobj_dma_new
(
chan
,
NV_CLASS_DMA_IN_MEMORY
,
dispc
->
sem
.
bo
->
bo
.
offset
,
0x1000
,
NV_MEM_ACCESS_RW
,
NV_MEM_TARGET_VRAM
,
&
obj
);
if
(
ret
)
break
;
ret
=
nouveau_ramht_insert
(
chan
,
NvEvoSema0
+
i
,
obj
);
nouveau_gpuobj_ref
(
NULL
,
&
obj
);
}
if
(
ret
)
psw
->
base
.
base
.
context_del
(
chan
,
engine
);
return
ret
;
}
}
static
void
static
void
...
...
drivers/gpu/drm/nouveau/nvc0_software.c
浏览文件 @
35bcf5d5
...
@@ -23,22 +23,37 @@
...
@@ -23,22 +23,37 @@
*/
*/
#include "drmP.h"
#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_drv.h"
#include "nouveau_ramht.h"
#include "nouveau_ramht.h"
#include "nouveau_software.h"
#include "nouveau_software.h"
#include "nv50_display.h"
struct
nvc0_software_priv
{
struct
nvc0_software_priv
{
struct
nouveau_software_priv
base
;
struct
nouveau_software_priv
base
;
};
};
struct
nvc0_software_chan
{
struct
nvc0_software_chan
{
struct
nouveau_software_chan
base
;
struct
nouveau_software_chan
base
;
struct
nouveau_vma
dispc_vma
[
4
];
};
};
u64
nvc0_software_crtc
(
struct
nouveau_channel
*
chan
,
int
crtc
)
{
struct
nvc0_software_chan
*
pch
=
chan
->
engctx
[
NVOBJ_ENGINE_SW
];
return
pch
->
dispc_vma
[
crtc
].
offset
;
}
static
int
static
int
nvc0_software_context_new
(
struct
nouveau_channel
*
chan
,
int
engine
)
nvc0_software_context_new
(
struct
nouveau_channel
*
chan
,
int
engine
)
{
{
struct
drm_device
*
dev
=
chan
->
dev
;
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
struct
nvc0_software_priv
*
psw
=
nv_engine
(
dev
,
NVOBJ_ENGINE_SW
);
struct
nvc0_software_chan
*
pch
;
struct
nvc0_software_chan
*
pch
;
int
ret
=
0
,
i
;
pch
=
kzalloc
(
sizeof
(
*
pch
),
GFP_KERNEL
);
pch
=
kzalloc
(
sizeof
(
*
pch
),
GFP_KERNEL
);
if
(
!
pch
)
if
(
!
pch
)
...
@@ -46,13 +61,45 @@ nvc0_software_context_new(struct nouveau_channel *chan, int engine)
...
@@ -46,13 +61,45 @@ nvc0_software_context_new(struct nouveau_channel *chan, int engine)
nouveau_software_context_new
(
&
pch
->
base
);
nouveau_software_context_new
(
&
pch
->
base
);
chan
->
engctx
[
engine
]
=
pch
;
chan
->
engctx
[
engine
]
=
pch
;
return
0
;
/* map display semaphore buffers into channel's vm */
for
(
i
=
0
;
!
ret
&&
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nouveau_bo
*
bo
;
if
(
dev_priv
->
card_type
>=
NV_D0
)
bo
=
nvd0_display_crtc_sema
(
dev
,
i
);
else
bo
=
nv50_display
(
dev
)
->
crtc
[
i
].
sem
.
bo
;
ret
=
nouveau_bo_vma_add
(
bo
,
chan
->
vm
,
&
pch
->
dispc_vma
[
i
]);
}
if
(
ret
)
psw
->
base
.
base
.
context_del
(
chan
,
engine
);
return
ret
;
}
}
static
void
static
void
nvc0_software_context_del
(
struct
nouveau_channel
*
chan
,
int
engine
)
nvc0_software_context_del
(
struct
nouveau_channel
*
chan
,
int
engine
)
{
{
struct
drm_device
*
dev
=
chan
->
dev
;
struct
drm_nouveau_private
*
dev_priv
=
dev
->
dev_private
;
struct
nvc0_software_chan
*
pch
=
chan
->
engctx
[
engine
];
struct
nvc0_software_chan
*
pch
=
chan
->
engctx
[
engine
];
int
i
;
if
(
dev_priv
->
card_type
>=
NV_D0
)
{
for
(
i
=
0
;
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nouveau_bo
*
bo
=
nvd0_display_crtc_sema
(
dev
,
i
);
nouveau_bo_vma_del
(
bo
,
&
pch
->
dispc_vma
[
i
]);
}
}
else
if
(
dev_priv
->
card_type
>=
NV_50
)
{
struct
nv50_display
*
disp
=
nv50_display
(
dev
);
for
(
i
=
0
;
i
<
dev
->
mode_config
.
num_crtc
;
i
++
)
{
struct
nv50_display_crtc
*
dispc
=
&
disp
->
crtc
[
i
];
nouveau_bo_vma_del
(
dispc
->
sem
.
bo
,
&
pch
->
dispc_vma
[
i
]);
}
}
chan
->
engctx
[
engine
]
=
NULL
;
chan
->
engctx
[
engine
]
=
NULL
;
kfree
(
pch
);
kfree
(
pch
);
}
}
...
...
drivers/gpu/drm/nouveau/nvd0_display.c
浏览文件 @
35bcf5d5
...
@@ -33,6 +33,7 @@
...
@@ -33,6 +33,7 @@
#include "nouveau_crtc.h"
#include "nouveau_crtc.h"
#include "nouveau_dma.h"
#include "nouveau_dma.h"
#include "nouveau_fb.h"
#include "nouveau_fb.h"
#include "nouveau_software.h"
#include "nv50_display.h"
#include "nv50_display.h"
#define EVO_DMA_NR 9
#define EVO_DMA_NR 9
...
@@ -298,7 +299,8 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
...
@@ -298,7 +299,8 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
if
(
ret
)
if
(
ret
)
return
ret
;
return
ret
;
offset
=
chan
->
dispc_vma
[
nv_crtc
->
index
].
offset
;
offset
=
nvc0_software_crtc
(
chan
,
nv_crtc
->
index
);
offset
+=
evo
->
sem
.
offset
;
offset
+=
evo
->
sem
.
offset
;
BEGIN_NVC0
(
chan
,
0
,
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
,
4
);
BEGIN_NVC0
(
chan
,
0
,
NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH
,
4
);
...
...
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