Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
大约 1 年 前同步成功

通知 153
Star 36
Fork 7
cloud-kernel
cloud-kernel

体验新版 GitCode，发现更多精彩内容 >>

提交 305282ba 编写于 作者: J Jay Cliburn 提交者： Jeff Garzik
浏览文件
操作

atl1: move common functions to atlx files 

The future atl2 driver and the existing atl1 driver can share certain
functions and definitions.  Move these shareable functions and definitions
out of atl1-specific files and into atlx.c and atlx.h.  Some transitory
hackery will be present until atl2 is merged.

Reduce the number of source files by moving ethtool, hw, and param
functions from separate files into atl1_main.c, then rename it to just
atl1.c.

Move all atl1-specific definitions from atl1_hw.h to atl1.h.

Finally, clean up to make checkpatch.pl happy.
Signed-off-by: NChris Snook <csnook@redhat.com>
Signed-off-by: NJay Cliburn <jacliburn@bellsouth.net>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
上级 2e5071bc
展开全部 隐藏空白更改
内联 并排
Showing with 2751 addition and 2507 deletion
drivers/net/atlx/Makefile
浏览文件 @ 305282ba
obj-$(CONFIG_ATL1) += atl1.o
atl1-y += atl1_main.o atl1_hw.o atl1_ethtool.o atl1_param.o
drivers/net/atlx/atl1.h
浏览文件 @ 305282ba
此差异已折叠。
drivers/net/atlx/atl1_ethtool.c 已删除 100644 → 0
浏览文件 @ 2e5071bc
/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/mii.h>
#include <asm/uaccess.h>
#include "atl1.h"
struct atl1_stats {
char stat_string[ETH_GSTRING_LEN];
int sizeof_stat;
int stat_offset;
};
#define ATL1_STAT(m) sizeof(((struct atl1_adapter *)0)->m), \
offsetof(struct atl1_adapter, m)
static struct atl1_stats atl1_gstrings_stats[] = {
{"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
{"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
{"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
{"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
{"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
{"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
{"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
{"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
{"multicast", ATL1_STAT(soft_stats.multicast)},
{"collisions", ATL1_STAT(soft_stats.collisions)},
{"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
{"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
{"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
{"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
{"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
{"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
{"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
{"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
{"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
{"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
{"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
{"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
{"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
{"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
{"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
{"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
{"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
{"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
{"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
{"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
{"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
};
static void atl1_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *stats, u64 *data)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
int i;
char *p;
for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
}
}
static int atl1_get_sset_count(struct net_device *netdev, int sset)
{
switch (sset) {
case ETH_SS_STATS:
return ARRAY_SIZE(atl1_gstrings_stats);
default:
return -EOPNOTSUPP;
}
}
static int atl1_get_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
ecmd->supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full |
SUPPORTED_Autoneg | SUPPORTED_TP);
ecmd->advertising = ADVERTISED_TP;
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
ecmd->advertising |= ADVERTISED_Autoneg;
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->advertising |=
(ADVERTISED_10baseT_Half |
ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_1000baseT_Full);
}
else
ecmd->advertising |= (ADVERTISED_1000baseT_Full);
}
ecmd->port = PORT_TP;
ecmd->phy_address = 0;
ecmd->transceiver = XCVR_INTERNAL;
if (netif_carrier_ok(adapter->netdev)) {
u16 link_speed, link_duplex;
atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
ecmd->speed = link_speed;
if (link_duplex == FULL_DUPLEX)
ecmd->duplex = DUPLEX_FULL;
else
ecmd->duplex = DUPLEX_HALF;
} else {
ecmd->speed = -1;
ecmd->duplex = -1;
}
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL)
ecmd->autoneg = AUTONEG_ENABLE;
else
ecmd->autoneg = AUTONEG_DISABLE;
return 0;
}
static int atl1_set_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
u16 phy_data;
int ret_val = 0;
u16 old_media_type = hw->media_type;
if (netif_running(adapter->netdev)) {
dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
atl1_down(adapter);
}
if (ecmd->autoneg == AUTONEG_ENABLE)
hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
else {
if (ecmd->speed == SPEED_1000) {
if (ecmd->duplex != DUPLEX_FULL) {
dev_warn(&adapter->pdev->dev,
"can't force to 1000M half duplex\n");
ret_val = -EINVAL;
goto exit_sset;
}
hw->media_type = MEDIA_TYPE_1000M_FULL;
} else if (ecmd->speed == SPEED_100) {
if (ecmd->duplex == DUPLEX_FULL) {
hw->media_type = MEDIA_TYPE_100M_FULL;
} else
hw->media_type = MEDIA_TYPE_100M_HALF;
} else {
if (ecmd->duplex == DUPLEX_FULL)
hw->media_type = MEDIA_TYPE_10M_FULL;
else
hw->media_type = MEDIA_TYPE_10M_HALF;
}
}
switch (hw->media_type) {
case MEDIA_TYPE_AUTO_SENSOR:
ecmd->advertising =
ADVERTISED_10baseT_Half |
ADVERTISED_10baseT_Full |
ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_1000baseT_Full |
ADVERTISED_Autoneg | ADVERTISED_TP;
break;
case MEDIA_TYPE_1000M_FULL:
ecmd->advertising =
ADVERTISED_1000baseT_Full |
ADVERTISED_Autoneg | ADVERTISED_TP;
break;
default:
ecmd->advertising = 0;
break;
}
if (atl1_phy_setup_autoneg_adv(hw)) {
ret_val = -EINVAL;
dev_warn(&adapter->pdev->dev,
"invalid ethtool speed/duplex setting\n");
goto exit_sset;
}
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL)
phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
else {
switch (hw->media_type) {
case MEDIA_TYPE_100M_FULL:
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
MII_CR_RESET;
break;
case MEDIA_TYPE_100M_HALF:
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
break;
case MEDIA_TYPE_10M_FULL:
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
break;
default: /* MEDIA_TYPE_10M_HALF: */
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
break;
}
}
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
exit_sset:
if (ret_val)
hw->media_type = old_media_type;
if (netif_running(adapter->netdev)) {
dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
atl1_up(adapter);
} else if (!ret_val) {
dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
atl1_reset(adapter);
}
return ret_val;
}
static void atl1_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
strncpy(drvinfo->driver, atl1_driver_name, sizeof(drvinfo->driver));
strncpy(drvinfo->version, atl1_driver_version,
sizeof(drvinfo->version));
strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
sizeof(drvinfo->bus_info));
drvinfo->eedump_len = ATL1_EEDUMP_LEN;
}
static void atl1_get_wol(struct net_device *netdev,
struct ethtool_wolinfo *wol)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
wol->wolopts = 0;
if (adapter->wol & ATL1_WUFC_EX)
wol->wolopts |= WAKE_UCAST;
if (adapter->wol & ATL1_WUFC_MC)
wol->wolopts |= WAKE_MCAST;
if (adapter->wol & ATL1_WUFC_BC)
wol->wolopts |= WAKE_BCAST;
if (adapter->wol & ATL1_WUFC_MAG)
wol->wolopts |= WAKE_MAGIC;
return;
}
static int atl1_set_wol(struct net_device *netdev,
struct ethtool_wolinfo *wol)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
return -EOPNOTSUPP;
adapter->wol = 0;
if (wol->wolopts & WAKE_UCAST)
adapter->wol |= ATL1_WUFC_EX;
if (wol->wolopts & WAKE_MCAST)
adapter->wol |= ATL1_WUFC_MC;
if (wol->wolopts & WAKE_BCAST)
adapter->wol |= ATL1_WUFC_BC;
if (wol->wolopts & WAKE_MAGIC)
adapter->wol |= ATL1_WUFC_MAG;
return 0;
}
static void atl1_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
ring->rx_max_pending = ATL1_MAX_RFD;
ring->tx_max_pending = ATL1_MAX_TPD;
ring->rx_mini_max_pending = 0;
ring->rx_jumbo_max_pending = 0;
ring->rx_pending = rxdr->count;
ring->tx_pending = txdr->count;
ring->rx_mini_pending = 0;
ring->rx_jumbo_pending = 0;
}
static int atl1_set_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
struct atl1_tpd_ring tpd_old, tpd_new;
struct atl1_rfd_ring rfd_old, rfd_new;
struct atl1_rrd_ring rrd_old, rrd_new;
struct atl1_ring_header rhdr_old, rhdr_new;
int err;
tpd_old = adapter->tpd_ring;
rfd_old = adapter->rfd_ring;
rrd_old = adapter->rrd_ring;
rhdr_old = adapter->ring_header;
if (netif_running(adapter->netdev))
atl1_down(adapter);
rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
rfdr->count;
rfdr->count = (rfdr->count + 3) & ~3;
rrdr->count = rfdr->count;
tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
tpdr->count;
tpdr->count = (tpdr->count + 3) & ~3;
if (netif_running(adapter->netdev)) {
/* try to get new resources before deleting old */
err = atl1_setup_ring_resources(adapter);
if (err)
goto err_setup_ring;
/*
* save the new, restore the old in order to free it,
* then restore the new back again
*/
rfd_new = adapter->rfd_ring;
rrd_new = adapter->rrd_ring;
tpd_new = adapter->tpd_ring;
rhdr_new = adapter->ring_header;
adapter->rfd_ring = rfd_old;
adapter->rrd_ring = rrd_old;
adapter->tpd_ring = tpd_old;
adapter->ring_header = rhdr_old;
atl1_free_ring_resources(adapter);
adapter->rfd_ring = rfd_new;
adapter->rrd_ring = rrd_new;
adapter->tpd_ring = tpd_new;
adapter->ring_header = rhdr_new;
err = atl1_up(adapter);
if (err)
return err;
}
return 0;
err_setup_ring:
adapter->rfd_ring = rfd_old;
adapter->rrd_ring = rrd_old;
adapter->tpd_ring = tpd_old;
adapter->ring_header = rhdr_old;
atl1_up(adapter);
return err;
}
static void atl1_get_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *epause)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
epause->autoneg = AUTONEG_ENABLE;
} else {
epause->autoneg = AUTONEG_DISABLE;
}
epause->rx_pause = 1;
epause->tx_pause = 1;
}
static int atl1_set_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *epause)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
epause->autoneg = AUTONEG_ENABLE;
} else {
epause->autoneg = AUTONEG_DISABLE;
}
epause->rx_pause = 1;
epause->tx_pause = 1;
return 0;
}
static u32 atl1_get_rx_csum(struct net_device *netdev)
{
return 1;
}
static void atl1_get_strings(struct net_device *netdev, u32 stringset,
u8 *data)
{
u8 *p = data;
int i;
switch (stringset) {
case ETH_SS_STATS:
for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
memcpy(p, atl1_gstrings_stats[i].stat_string,
ETH_GSTRING_LEN);
p += ETH_GSTRING_LEN;
}
break;
}
}
static int atl1_nway_reset(struct net_device *netdev)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
if (netif_running(netdev)) {
u16 phy_data;
atl1_down(adapter);
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
} else {
switch (hw->media_type) {
case MEDIA_TYPE_100M_FULL:
phy_data = MII_CR_FULL_DUPLEX |
MII_CR_SPEED_100 | MII_CR_RESET;
break;
case MEDIA_TYPE_100M_HALF:
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
break;
case MEDIA_TYPE_10M_FULL:
phy_data = MII_CR_FULL_DUPLEX |
MII_CR_SPEED_10 | MII_CR_RESET;
break;
default: /* MEDIA_TYPE_10M_HALF */
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
}
}
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
atl1_up(adapter);
}
return 0;
}
const struct ethtool_ops atl1_ethtool_ops = {
.get_settings = atl1_get_settings,
.set_settings = atl1_set_settings,
.get_drvinfo = atl1_get_drvinfo,
.get_wol = atl1_get_wol,
.set_wol = atl1_set_wol,
.get_ringparam = atl1_get_ringparam,
.set_ringparam = atl1_set_ringparam,
.get_pauseparam = atl1_get_pauseparam,
.set_pauseparam = atl1_set_pauseparam,
.get_rx_csum = atl1_get_rx_csum,
.set_tx_csum = ethtool_op_set_tx_hw_csum,
.get_link = ethtool_op_get_link,
.set_sg = ethtool_op_set_sg,
.get_strings = atl1_get_strings,
.nway_reset = atl1_nway_reset,
.get_ethtool_stats = atl1_get_ethtool_stats,
.get_sset_count = atl1_get_sset_count,
.set_tso = ethtool_op_set_tso,
};
drivers/net/atlx/atl1_hw.c 已删除 100644 → 0
浏览文件 @ 2e5071bc
/*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/if_vlan.h>
#include <linux/etherdevice.h>
#include <linux/crc32.h>
#include <asm/byteorder.h>
#include "atl1.h"
/*
* Reset the transmit and receive units; mask and clear all interrupts.
* hw - Struct containing variables accessed by shared code
* return : ATL1_SUCCESS or idle status (if error)
*/
s32 atl1_reset_hw(struct atl1_hw *hw)
{
struct pci_dev *pdev = hw->back->pdev;
u32 icr;
int i;
/*
* Clear Interrupt mask to stop board from generating
* interrupts & Clear any pending interrupt events
*/
/*
* iowrite32(0, hw->hw_addr + REG_IMR);
* iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
*/
/*
* Issue Soft Reset to the MAC. This will reset the chip's
* transmit, receive, DMA. It will not effect
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
ioread32(hw->hw_addr + REG_MASTER_CTRL);
iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
ioread16(hw->hw_addr + REG_GPHY_ENABLE);
msleep(1); /* delay about 1ms */
/* Wait at least 10ms for All module to be Idle */
for (i = 0; i < 10; i++) {
icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
if (!icr)
break;
msleep(1); /* delay 1 ms */
cpu_relax(); /* FIXME: is this still the right way to do this? */
}
if (icr) {
dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
return icr;
}
return ATL1_SUCCESS;
}
/* function about EEPROM
*
* check_eeprom_exist
* return 0 if eeprom exist
*/
static int atl1_check_eeprom_exist(struct atl1_hw *hw)
{
u32 value;
value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
if (value & SPI_FLASH_CTRL_EN_VPD) {
value &= ~SPI_FLASH_CTRL_EN_VPD;
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
}
value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
}
static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
{
int i;
u32 control;
if (offset & 3)
return false; /* address do not align */
iowrite32(0, hw->hw_addr + REG_VPD_DATA);
control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
iowrite32(control, hw->hw_addr + REG_VPD_CAP);
ioread32(hw->hw_addr + REG_VPD_CAP);
for (i = 0; i < 10; i++) {
msleep(2);
control = ioread32(hw->hw_addr + REG_VPD_CAP);
if (control & VPD_CAP_VPD_FLAG)
break;
}
if (control & VPD_CAP_VPD_FLAG) {
*p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
return true;
}
return false; /* timeout */
}
/*
* Reads the value from a PHY register
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
*/
s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
{
u32 val;
int i;
val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
MDIO_CLK_SEL_SHIFT;
iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
ioread32(hw->hw_addr + REG_MDIO_CTRL);
for (i = 0; i < MDIO_WAIT_TIMES; i++) {
udelay(2);
val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
if (!(val & (MDIO_START | MDIO_BUSY)))
break;
}
if (!(val & (MDIO_START | MDIO_BUSY))) {
*phy_data = (u16) val;
return ATL1_SUCCESS;
}
return ATL1_ERR_PHY;
}
#define CUSTOM_SPI_CS_SETUP 2
#define CUSTOM_SPI_CLK_HI 2
#define CUSTOM_SPI_CLK_LO 2
#define CUSTOM_SPI_CS_HOLD 2
#define CUSTOM_SPI_CS_HI 3
static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
{
int i;
u32 value;
iowrite32(0, hw->hw_addr + REG_SPI_DATA);
iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
value = SPI_FLASH_CTRL_WAIT_READY |
(CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
SPI_FLASH_CTRL_CLK_HI_MASK) <<
SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
SPI_FLASH_CTRL_CLK_LO_MASK) <<
SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
SPI_FLASH_CTRL_CS_HOLD_MASK) <<
SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
SPI_FLASH_CTRL_CS_HI_MASK) <<
SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
SPI_FLASH_CTRL_INS_SHIFT;
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
value |= SPI_FLASH_CTRL_START;
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
for (i = 0; i < 10; i++) {
msleep(1); /* 1ms */
value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
if (!(value & SPI_FLASH_CTRL_START))
break;
}
if (value & SPI_FLASH_CTRL_START)
return false;
*buf = ioread32(hw->hw_addr + REG_SPI_DATA);
return true;
}
/*
* get_permanent_address
* return 0 if get valid mac address,
*/
static int atl1_get_permanent_address(struct atl1_hw *hw)
{
u32 addr[2];
u32 i, control;
u16 reg;
u8 eth_addr[ETH_ALEN];
bool key_valid;
if (is_valid_ether_addr(hw->perm_mac_addr))
return 0;
/* init */
addr[0] = addr[1] = 0;
if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
reg = 0;
key_valid = false;
/* Read out all EEPROM content */
i = 0;
while (1) {
if (atl1_read_eeprom(hw, i + 0x100, &control)) {
if (key_valid) {
if (reg == REG_MAC_STA_ADDR)
addr[0] = control;
else if (reg == (REG_MAC_STA_ADDR + 4))
addr[1] = control;
key_valid = false;
} else if ((control & 0xff) == 0x5A) {
key_valid = true;
reg = (u16) (control >> 16);
} else
break; /* assume data end while encount an invalid KEYWORD */
} else
break; /* read error */
i += 4;
}
*(u32 *) &eth_addr[2] = swab32(addr[0]);
*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
if (is_valid_ether_addr(eth_addr)) {
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
return 0;
}
return 1;
}
/* see if SPI FLAGS exist ? */
addr[0] = addr[1] = 0;
reg = 0;
key_valid = false;
i = 0;
while (1) {
if (atl1_spi_read(hw, i + 0x1f000, &control)) {
if (key_valid) {
if (reg == REG_MAC_STA_ADDR)
addr[0] = control;
else if (reg == (REG_MAC_STA_ADDR + 4))
addr[1] = control;
key_valid = false;
} else if ((control & 0xff) == 0x5A) {
key_valid = true;
reg = (u16) (control >> 16);
} else
break; /* data end */
} else
break; /* read error */
i += 4;
}
*(u32 *) &eth_addr[2] = swab32(addr[0]);
*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
if (is_valid_ether_addr(eth_addr)) {
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
return 0;
}
/*
* On some motherboards, the MAC address is written by the
* BIOS directly to the MAC register during POST, and is
* not stored in eeprom. If all else thus far has failed
* to fetch the permanent MAC address, try reading it directly.
*/
addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
*(u32 *) &eth_addr[2] = swab32(addr[0]);
*(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
if (is_valid_ether_addr(eth_addr)) {
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
return 0;
}
return 1;
}
/*
* Reads the adapter's MAC address from the EEPROM
* hw - Struct containing variables accessed by shared code
*/
s32 atl1_read_mac_addr(struct atl1_hw *hw)
{
u16 i;
if (atl1_get_permanent_address(hw))
random_ether_addr(hw->perm_mac_addr);
for (i = 0; i < ETH_ALEN; i++)
hw->mac_addr[i] = hw->perm_mac_addr[i];
return ATL1_SUCCESS;
}
/*
* Hashes an address to determine its location in the multicast table
* hw - Struct containing variables accessed by shared code
* mc_addr - the multicast address to hash
*
* atl1_hash_mc_addr
* purpose
* set hash value for a multicast address
* hash calcu processing :
* 1. calcu 32bit CRC for multicast address
* 2. reverse crc with MSB to LSB
*/
u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
{
u32 crc32, value = 0;
int i;
crc32 = ether_crc_le(6, mc_addr);
for (i = 0; i < 32; i++)
value |= (((crc32 >> i) & 1) << (31 - i));
return value;
}
/*
* Sets the bit in the multicast table corresponding to the hash value.
* hw - Struct containing variables accessed by shared code
* hash_value - Multicast address hash value
*/
void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
{
u32 hash_bit, hash_reg;
u32 mta;
/*
* The HASH Table is a register array of 2 32-bit registers.
* It is treated like an array of 64 bits. We want to set
* bit BitArray[hash_value]. So we figure out what register
* the bit is in, read it, OR in the new bit, then write
* back the new value. The register is determined by the
* upper 7 bits of the hash value and the bit within that
* register are determined by the lower 5 bits of the value.
*/
hash_reg = (hash_value >> 31) & 0x1;
hash_bit = (hash_value >> 26) & 0x1F;
mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
mta |= (1 << hash_bit);
iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
}
/*
* Writes a value to a PHY register
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
*/
s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
{
int i;
u32 val;
val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
MDIO_SUP_PREAMBLE |
MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
ioread32(hw->hw_addr + REG_MDIO_CTRL);
for (i = 0; i < MDIO_WAIT_TIMES; i++) {
udelay(2);
val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
if (!(val & (MDIO_START | MDIO_BUSY)))
break;
}
if (!(val & (MDIO_START | MDIO_BUSY)))
return ATL1_SUCCESS;
return ATL1_ERR_PHY;
}
/*
* Make L001's PHY out of Power Saving State (bug)
* hw - Struct containing variables accessed by shared code
* when power on, L001's PHY always on Power saving State
* (Gigabit Link forbidden)
*/
static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
{
s32 ret;
ret = atl1_write_phy_reg(hw, 29, 0x0029);
if (ret)
return ret;
return atl1_write_phy_reg(hw, 30, 0);
}
/*
*TODO: do something or get rid of this
*/
s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
{
/* s32 ret_val;
* u16 phy_data;
*/
/*
ret_val = atl1_write_phy_reg(hw, ...);
ret_val = atl1_write_phy_reg(hw, ...);
....
*/
return ATL1_SUCCESS;
}
/*
* Resets the PHY and make all config validate
* hw - Struct containing variables accessed by shared code
*
* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
*/
static s32 atl1_phy_reset(struct atl1_hw *hw)
{
struct pci_dev *pdev = hw->back->pdev;
s32 ret_val;
u16 phy_data;
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
hw->media_type == MEDIA_TYPE_1000M_FULL)
phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
else {
switch (hw->media_type) {
case MEDIA_TYPE_100M_FULL:
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
MII_CR_RESET;
break;
case MEDIA_TYPE_100M_HALF:
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
break;
case MEDIA_TYPE_10M_FULL:
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
break;
default: /* MEDIA_TYPE_10M_HALF: */
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
break;
}
}
ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
if (ret_val) {
u32 val;
int i;
/* pcie serdes link may be down! */
dev_dbg(&pdev->dev, "pcie phy link down\n");
for (i = 0; i < 25; i++) {
msleep(1);
val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
if (!(val & (MDIO_START | MDIO_BUSY)))
break;
}
if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
return ret_val;
}
}
return ATL1_SUCCESS;
}
/*
* Configures PHY autoneg and flow control advertisement settings
* hw - Struct containing variables accessed by shared code
*/
s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
{
s32 ret_val;
s16 mii_autoneg_adv_reg;
s16 mii_1000t_ctrl_reg;
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
/* Read the MII 1000Base-T Control Register (Address 9). */
mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
/*
* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
/*
* Need to parse media_type and set up
* the appropriate PHY registers.
*/
switch (hw->media_type) {
case MEDIA_TYPE_AUTO_SENSOR:
mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
MII_AR_10T_FD_CAPS |
MII_AR_100TX_HD_CAPS |
MII_AR_100TX_FD_CAPS);
mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
break;
case MEDIA_TYPE_1000M_FULL:
mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
break;
case MEDIA_TYPE_100M_FULL:
mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
break;
case MEDIA_TYPE_100M_HALF:
mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
break;
case MEDIA_TYPE_10M_FULL:
mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
break;
default:
mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
break;
}
/* flow control fixed to enable all */
mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
if (ret_val)
return ret_val;
ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
if (ret_val)
return ret_val;
return ATL1_SUCCESS;
}
/*
* Configures link settings.
* hw - Struct containing variables accessed by shared code
* Assumes the hardware has previously been reset and the
* transmitter and receiver are not enabled.
*/
static s32 atl1_setup_link(struct atl1_hw *hw)
{
struct pci_dev *pdev = hw->back->pdev;
s32 ret_val;
/*
* Options:
* PHY will advertise value(s) parsed from
* autoneg_advertised and fc
* no matter what autoneg is , We will not wait link result.
*/
ret_val = atl1_phy_setup_autoneg_adv(hw);
if (ret_val) {
dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
return ret_val;
}
/* SW.Reset , En-Auto-Neg if needed */
ret_val = atl1_phy_reset(hw);
if (ret_val) {
dev_dbg(&pdev->dev, "error resetting phy\n");
return ret_val;
}
hw->phy_configured = true;
return ret_val;
}
static struct atl1_spi_flash_dev flash_table[] = {
/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
{"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
};
static void atl1_init_flash_opcode(struct atl1_hw *hw)
{
if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
hw->flash_vendor = 0; /* ATMEL */
/* Init OP table */
iowrite8(flash_table[hw->flash_vendor].cmd_program,
hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
hw->hw_addr + REG_SPI_FLASH_OP_RDID);
iowrite8(flash_table[hw->flash_vendor].cmd_wren,
hw->hw_addr + REG_SPI_FLASH_OP_WREN);
iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
iowrite8(flash_table[hw->flash_vendor].cmd_read,
hw->hw_addr + REG_SPI_FLASH_OP_READ);
}
/*
* Performs basic configuration of the adapter.
* hw - Struct containing variables accessed by shared code
* Assumes that the controller has previously been reset and is in a
* post-reset uninitialized state. Initializes multicast table,
* and Calls routines to setup link
* Leaves the transmit and receive units disabled and uninitialized.
*/
s32 atl1_init_hw(struct atl1_hw *hw)
{
u32 ret_val = 0;
/* Zero out the Multicast HASH table */
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
/* clear the old settings from the multicast hash table */
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
atl1_init_flash_opcode(hw);
if (!hw->phy_configured) {
/* enable GPHY LinkChange Interrrupt */
ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
if (ret_val)
return ret_val;
/* make PHY out of power-saving state */
ret_val = atl1_phy_leave_power_saving(hw);
if (ret_val)
return ret_val;
/* Call a subroutine to configure the link */
ret_val = atl1_setup_link(hw);
}
return ret_val;
}
/*
* Detects the current speed and duplex settings of the hardware.
* hw - Struct containing variables accessed by shared code
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*/
s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
{
struct pci_dev *pdev = hw->back->pdev;
s32 ret_val;
u16 phy_data;
/* ; --- Read PHY Specific Status Register (17) */
ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
if (ret_val)
return ret_val;
if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
return ATL1_ERR_PHY_RES;
switch (phy_data & MII_AT001_PSSR_SPEED) {
case MII_AT001_PSSR_1000MBS:
*speed = SPEED_1000;
break;
case MII_AT001_PSSR_100MBS:
*speed = SPEED_100;
break;
case MII_AT001_PSSR_10MBS:
*speed = SPEED_10;
break;
default:
dev_dbg(&pdev->dev, "error getting speed\n");
return ATL1_ERR_PHY_SPEED;
break;
}
if (phy_data & MII_AT001_PSSR_DPLX)
*duplex = FULL_DUPLEX;
else
*duplex = HALF_DUPLEX;
return ATL1_SUCCESS;
}
void atl1_set_mac_addr(struct atl1_hw *hw)
{
u32 value;
/*
* 00-0B-6A-F6-00-DC
* 0: 6AF600DC 1: 000B
* low dword
*/
value = (((u32) hw->mac_addr[2]) << 24) |
(((u32) hw->mac_addr[3]) << 16) |
(((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
/* high dword */
value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
}
drivers/net/atlx/atl1_hw.h 已删除 100644 → 0
浏览文件 @ 2e5071bc
此差异已折叠。
drivers/net/atlx/atl1_param.c → drivers/net/atlx/atlx.c
浏览文件 @ 305282ba
/*
/* atlx.c -- common functions for Attansic network drivers
*
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
*
* Derived from Intel e1000 driver
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
......@@ -21,10 +23,235 @@
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* Including this file like a header is a temporary hack, I promise. -- CHS */
#ifndef ATLX_C
#define ATLX_C
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/etherdevice.h>
#include <linux/if.h>
#include <linux/netdevice.h>
#include <linux/socket.h>
#include <linux/sockios.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include "atl1.h"
#include <linux/workqueue.h>
#include "atlx.h"
static struct atlx_spi_flash_dev flash_table[] = {
/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SEC_ERS CHIP_ERS */
{"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
};
static int atlx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
switch (cmd) {
case SIOCGMIIPHY:
case SIOCGMIIREG:
case SIOCSMIIREG:
return atlx_mii_ioctl(netdev, ifr, cmd);
default:
return -EOPNOTSUPP;
}
}
/*
* atlx_set_mac - Change the Ethernet Address of the NIC
* @netdev: network interface device structure
* @p: pointer to an address structure
*
* Returns 0 on success, negative on failure
*/
static int atlx_set_mac(struct net_device *netdev, void *p)
{
struct atlx_adapter *adapter = netdev_priv(netdev);
struct sockaddr *addr = p;
if (netif_running(netdev))
return -EBUSY;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
atlx_set_mac_addr(&adapter->hw);
return 0;
}
static void atlx_check_for_link(struct atlx_adapter *adapter)
{
struct net_device *netdev = adapter->netdev;
u16 phy_data = 0;
spin_lock(&adapter->lock);
adapter->phy_timer_pending = false;
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
spin_unlock(&adapter->lock);
/* notify upper layer link down ASAP */
if (!(phy_data & BMSR_LSTATUS)) {
/* Link Down */
if (netif_carrier_ok(netdev)) {
/* old link state: Up */
dev_info(&adapter->pdev->dev, "%s link is down\n",
netdev->name);
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
}
}
schedule_work(&adapter->link_chg_task);
}
/*
* atlx_set_multi - Multicast and Promiscuous mode set
* @netdev: network interface device structure
*
* The set_multi entry point is called whenever the multicast address
* list or the network interface flags are updated. This routine is
* responsible for configuring the hardware for proper multicast,
* promiscuous mode, and all-multi behavior.
*/
static void atlx_set_multi(struct net_device *netdev)
{
struct atlx_adapter *adapter = netdev_priv(netdev);
struct atlx_hw *hw = &adapter->hw;
struct dev_mc_list *mc_ptr;
u32 rctl;
u32 hash_value;
/* Check for Promiscuous and All Multicast modes */
rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
if (netdev->flags & IFF_PROMISC)
rctl |= MAC_CTRL_PROMIS_EN;
else if (netdev->flags & IFF_ALLMULTI) {
rctl |= MAC_CTRL_MC_ALL_EN;
rctl &= ~MAC_CTRL_PROMIS_EN;
} else
rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
/* clear the old settings from the multicast hash table */
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
/* compute mc addresses' hash value ,and put it into hash table */
for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
hash_value = atlx_hash_mc_addr(hw, mc_ptr->dmi_addr);
atlx_hash_set(hw, hash_value);
}
}
/*
* atlx_irq_enable - Enable default interrupt generation settings
* @adapter: board private structure
*/
static void atlx_irq_enable(struct atlx_adapter *adapter)
{
iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
ioread32(adapter->hw.hw_addr + REG_IMR);
}
/*
* atlx_irq_disable - Mask off interrupt generation on the NIC
* @adapter: board private structure
*/
static void atlx_irq_disable(struct atlx_adapter *adapter)
{
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
ioread32(adapter->hw.hw_addr + REG_IMR);
synchronize_irq(adapter->pdev->irq);
}
static void atlx_clear_phy_int(struct atlx_adapter *adapter)
{
u16 phy_data;
unsigned long flags;
spin_lock_irqsave(&adapter->lock, flags);
atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
spin_unlock_irqrestore(&adapter->lock, flags);
}
/*
* atlx_get_stats - Get System Network Statistics
* @netdev: network interface device structure
*
* Returns the address of the device statistics structure.
* The statistics are actually updated from the timer callback.
*/
static struct net_device_stats *atlx_get_stats(struct net_device *netdev)
{
struct atlx_adapter *adapter = netdev_priv(netdev);
return &adapter->net_stats;
}
/*
* atlx_tx_timeout - Respond to a Tx Hang
* @netdev: network interface device structure
*/
static void atlx_tx_timeout(struct net_device *netdev)
{
struct atlx_adapter *adapter = netdev_priv(netdev);
/* Do the reset outside of interrupt context */
schedule_work(&adapter->tx_timeout_task);
}
/*
* atlx_link_chg_task - deal with link change event Out of interrupt context
*/
static void atlx_link_chg_task(struct work_struct *work)
{
struct atlx_adapter *adapter;
unsigned long flags;
adapter = container_of(work, struct atlx_adapter, link_chg_task);
spin_lock_irqsave(&adapter->lock, flags);
atlx_check_link(adapter);
spin_unlock_irqrestore(&adapter->lock, flags);
}
static void atlx_vlan_rx_register(struct net_device *netdev,
struct vlan_group *grp)
{
struct atlx_adapter *adapter = netdev_priv(netdev);
unsigned long flags;
u32 ctrl;
spin_lock_irqsave(&adapter->lock, flags);
/* atlx_irq_disable(adapter); FIXME: confirm/remove */
adapter->vlgrp = grp;
if (grp) {
/* enable VLAN tag insert/strip */
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
ctrl |= MAC_CTRL_RMV_VLAN;
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
} else {
/* disable VLAN tag insert/strip */
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
ctrl &= ~MAC_CTRL_RMV_VLAN;
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
}
/* atlx_irq_enable(adapter); FIXME */
spin_unlock_irqrestore(&adapter->lock, flags);
}
static void atlx_restore_vlan(struct atlx_adapter *adapter)
{
atlx_vlan_rx_register(adapter->netdev, adapter->vlgrp);
}
/*
* This is the only thing that needs to be changed to adjust the
......@@ -46,8 +273,9 @@
* Default Value: 100 (200us)
*/
static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
static int num_int_mod_timer = 0;
module_param_array_named(int_mod_timer, int_mod_timer, int, &num_int_mod_timer, 0);
static int num_int_mod_timer;
module_param_array_named(int_mod_timer, int_mod_timer, int,
&num_int_mod_timer, 0);
MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
/*
......@@ -62,7 +290,7 @@ MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
* Default Value: 0
*/
static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
static int num_flash_vendor = 0;
static int num_flash_vendor;
module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
......@@ -94,7 +322,8 @@ struct atl1_option {
} arg;
};
static int __devinit atl1_validate_option(int *value, struct atl1_option *opt, struct pci_dev *pdev)
static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
struct pci_dev *pdev)
{
if (*value == OPTION_UNSET) {
*value = opt->def;
......@@ -169,8 +398,8 @@ void __devinit atl1_check_options(struct atl1_adapter *adapter)
.err = "using default of "
__MODULE_STRING(DEFAULT_INT_MOD_CNT),
.def = DEFAULT_INT_MOD_CNT,
.arg = {.r =
{.min = MIN_INT_MOD_CNT,.max = MAX_INT_MOD_CNT}}
.arg = {.r = {.min = MIN_INT_MOD_CNT,
.max = MAX_INT_MOD_CNT} }
};
int val;
if (num_int_mod_timer > bd) {
......@@ -188,9 +417,8 @@ void __devinit atl1_check_options(struct atl1_adapter *adapter)
.err = "using default of "
__MODULE_STRING(FLASH_VENDOR_DEFAULT),
.def = DEFAULT_INT_MOD_CNT,
.arg = {.r =
{.min = FLASH_VENDOR_MIN,.max =
FLASH_VENDOR_MAX}}
.arg = {.r = {.min = FLASH_VENDOR_MIN,
.max = FLASH_VENDOR_MAX} }
};
int val;
if (num_flash_vendor > bd) {
......@@ -201,3 +429,5 @@ void __devinit atl1_check_options(struct atl1_adapter *adapter)
adapter->hw.flash_vendor = (u8) (opt.def);
}
}
#endif /* ATLX_C */
drivers/net/atlx/atlx.h 0 → 100644
浏览文件 @ 305282ba
此差异已折叠。
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或