Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openanolis
cloud-kernel
提交
2f5394c3
cloud-kernel
项目概览
openanolis
/
cloud-kernel
大约 1 年 前同步成功
通知
158
Star
36
Fork
7
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
10
列表
看板
标记
里程碑
合并请求
2
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
cloud-kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
10
Issue
10
列表
看板
标记
里程碑
合并请求
2
合并请求
2
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
2f5394c3
编写于
3月 12, 2012
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau: map first page of mmio early and determine chipset earlier
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
4cbb0f8d
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
62 addition
and
63 deletion
+62
-63
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_drv.h
+2
-2
drivers/gpu/drm/nouveau/nouveau_state.c
drivers/gpu/drm/nouveau/nouveau_state.c
+60
-61
未找到文件。
drivers/gpu/drm/nouveau/nouveau_drv.h
浏览文件 @
2f5394c3
...
...
@@ -695,14 +695,14 @@ struct nv04_mode_state {
};
enum
nouveau_card_type
{
NV_04
=
0x0
0
,
NV_04
=
0x0
4
,
NV_10
=
0x10
,
NV_20
=
0x20
,
NV_30
=
0x30
,
NV_40
=
0x40
,
NV_50
=
0x50
,
NV_C0
=
0xc0
,
NV_D0
=
0xd0
NV_D0
=
0xd0
,
};
struct
drm_nouveau_private
{
...
...
drivers/gpu/drm/nouveau/nouveau_state.c
浏览文件 @
2f5394c3
...
...
@@ -993,7 +993,7 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
int
nouveau_load
(
struct
drm_device
*
dev
,
unsigned
long
flags
)
{
struct
drm_nouveau_private
*
dev_priv
;
uint32_t
reg0
,
strap
;
uint32_t
reg0
=
~
0
,
strap
;
resource_size_t
mmio_start_offs
;
int
ret
;
...
...
@@ -1012,10 +1012,65 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
NV_DEBUG
(
dev
,
"vendor: 0x%X device: 0x%X class: 0x%X
\n
"
,
dev
->
pci_vendor
,
dev
->
pci_device
,
dev
->
pdev
->
class
);
/* resource 0 is mmio regs */
/* resource 1 is linear FB */
/* resource 2 is RAMIN (mmio regs + 0x1000000) */
/* resource 6 is bios */
/* first up, map the start of mmio and determine the chipset */
dev_priv
->
mmio
=
ioremap
(
pci_resource_start
(
dev
->
pdev
,
0
),
PAGE_SIZE
);
if
(
dev_priv
->
mmio
)
{
#ifdef __BIG_ENDIAN
/* put the card into big-endian mode if it's not */
if
(
nv_rd32
(
dev
,
NV03_PMC_BOOT_1
)
!=
0x01000001
)
nv_wr32
(
dev
,
NV03_PMC_BOOT_1
,
0x01000001
);
DRM_MEMORYBARRIER
();
#endif
/* determine chipset and derive architecture from it */
reg0
=
nv_rd32
(
dev
,
NV03_PMC_BOOT_0
);
if
((
reg0
&
0x0f000000
)
>
0
)
{
dev_priv
->
chipset
=
(
reg0
&
0xff00000
)
>>
20
;
switch
(
dev_priv
->
chipset
&
0xf0
)
{
case
0x10
:
case
0x20
:
case
0x30
:
dev_priv
->
card_type
=
dev_priv
->
chipset
&
0xf0
;
break
;
case
0x40
:
case
0x60
:
dev_priv
->
card_type
=
NV_40
;
break
;
case
0x50
:
case
0x80
:
case
0x90
:
case
0xa0
:
dev_priv
->
card_type
=
NV_50
;
break
;
case
0xc0
:
dev_priv
->
card_type
=
NV_C0
;
break
;
case
0xd0
:
dev_priv
->
card_type
=
NV_D0
;
break
;
default:
break
;
}
}
else
if
((
reg0
&
0xff00fff0
)
==
0x20004000
)
{
if
(
reg0
&
0x00f00000
)
dev_priv
->
chipset
=
0x05
;
else
dev_priv
->
chipset
=
0x04
;
dev_priv
->
card_type
=
NV_04
;
}
iounmap
(
dev_priv
->
mmio
);
}
if
(
!
dev_priv
->
card_type
)
{
NV_ERROR
(
dev
,
"unsupported chipset 0x%08x
\n
"
,
reg0
);
ret
=
-
EINVAL
;
goto
err_priv
;
}
NV_INFO
(
dev
,
"Detected an NV%2x generation card (0x%08x)
\n
"
,
dev_priv
->
card_type
,
reg0
);
/* map the mmio regs */
mmio_start_offs
=
pci_resource_start
(
dev
->
pdev
,
0
);
...
...
@@ -1029,62 +1084,6 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
NV_DEBUG
(
dev
,
"regs mapped ok at 0x%llx
\n
"
,
(
unsigned
long
long
)
mmio_start_offs
);
#ifdef __BIG_ENDIAN
/* Put the card in BE mode if it's not */
if
(
nv_rd32
(
dev
,
NV03_PMC_BOOT_1
)
!=
0x01000001
)
nv_wr32
(
dev
,
NV03_PMC_BOOT_1
,
0x01000001
);
DRM_MEMORYBARRIER
();
#endif
/* Time to determine the card architecture */
reg0
=
nv_rd32
(
dev
,
NV03_PMC_BOOT_0
);
/* We're dealing with >=NV10 */
if
((
reg0
&
0x0f000000
)
>
0
)
{
/* Bit 27-20 contain the architecture in hex */
dev_priv
->
chipset
=
(
reg0
&
0xff00000
)
>>
20
;
/* NV04 or NV05 */
}
else
if
((
reg0
&
0xff00fff0
)
==
0x20004000
)
{
if
(
reg0
&
0x00f00000
)
dev_priv
->
chipset
=
0x05
;
else
dev_priv
->
chipset
=
0x04
;
}
else
dev_priv
->
chipset
=
0xff
;
switch
(
dev_priv
->
chipset
&
0xf0
)
{
case
0x00
:
case
0x10
:
case
0x20
:
case
0x30
:
dev_priv
->
card_type
=
dev_priv
->
chipset
&
0xf0
;
break
;
case
0x40
:
case
0x60
:
dev_priv
->
card_type
=
NV_40
;
break
;
case
0x50
:
case
0x80
:
case
0x90
:
case
0xa0
:
dev_priv
->
card_type
=
NV_50
;
break
;
case
0xc0
:
dev_priv
->
card_type
=
NV_C0
;
break
;
case
0xd0
:
dev_priv
->
card_type
=
NV_D0
;
break
;
default:
NV_INFO
(
dev
,
"Unsupported chipset 0x%08x
\n
"
,
reg0
);
ret
=
-
EINVAL
;
goto
err_mmio
;
}
NV_INFO
(
dev
,
"Detected an NV%2x generation card (0x%08x)
\n
"
,
dev_priv
->
card_type
,
reg0
);
/* determine frequency of timing crystal */
strap
=
nv_rd32
(
dev
,
0x101000
);
if
(
dev_priv
->
chipset
<
0x17
||
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录