提交 2e653ff0 编写于 作者: S Sergei Shtylyov 提交者: David S. Miller

sh_eth: get rid of 'sh_eth_cpu_data::shift_rd0'

After checking all  the available manuals,  I have enough information to
conclude  that the 'shift_rd0' flag is only relevant  for the Ether cores
supporting so called "intelligent checksum" (and hence having CSMR) which
is indicated  by the 'hw_crc' flag.  Since  all the relevant SoCs now have
both these flags set, we can  at last  get  rid of the former flag...
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
上级 bb1d3034
......@@ -537,7 +537,6 @@ static struct sh_eth_cpu_data r7s72100_data = {
.no_ade = 1,
.hw_crc = 1,
.tsu = 1,
.shift_rd0 = 1,
};
static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
......@@ -577,7 +576,6 @@ static struct sh_eth_cpu_data r8a7740_data = {
.hw_crc = 1,
.tsu = 1,
.select_mii = 1,
.shift_rd0 = 1,
};
/* There is CPU dependent code */
......@@ -816,7 +814,6 @@ static struct sh_eth_cpu_data sh7734_data = {
.tsu = 1,
.hw_crc = 1,
.select_mii = 1,
.shift_rd0 = 1,
};
/* SH7763 */
......@@ -1416,7 +1413,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
* the RFS bits are from bit 25 to bit 16. So, the
* driver needs right shifting by 16.
*/
if (mdp->cd->shift_rd0)
if (mdp->cd->hw_crc)
desc_status >>= 16;
skb = mdp->rx_skbuff[entry];
......
......@@ -490,7 +490,6 @@ struct sh_eth_cpu_data {
unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
unsigned hw_crc:1; /* E-DMAC have CSMR */
unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */
unsigned rmiimode:1; /* EtherC has RMIIMODE register */
unsigned rtrate:1; /* EtherC has RTRATE register */
};
......
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