arch/tile: Fix bug in support for atomic64_xx() ops.

This wasn't properly tested until the perf-event subsystem started
to get brought up under the tile architecture.

The bug caused bogus atomic64_cmpxchg() values to be returned,
among other things.
Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

arch/tile/lib/atomic_asm_32.S

@@ -89,11 +89,11 @@ STD_ENTRY_SECTION(__atomic\name, .text.atomic)
 	 lh     r22, r0
 	 .else
 	 lw     r22, r0
-	 addi   r23, r0, 4
+	 addi   r28, r0, 4
 	 .endif
 	}
 	.ifc \bitwidth,64
-	lw      r23, r23
+	lw      r23, r28
 	.endif
 	\body /* set r24, and r25 if 64-bit */
 	{
@@ -109,11 +109,10 @@ STD_ENTRY_SECTION(__atomic\name, .text.atomic)
 	 sh     r0, r24
 	 .else
 	 sw     r0, r24
-	 addi   r23, r0, 4
 	 .endif
 	}
 	.ifc \bitwidth,64
-	sw      r23, r25
+	sw      r28, r25
 	.endif
 	mf
 3:	{