提交 2d32a9ae 编写于 作者: K Kenji Kaneshige 提交者: Jesse Barnes

pciehp: Add missing memory barrier

Fix the possible race condition between pcie_isr() and pciehp_write_cmd()
because of the lack of memory barrier.
Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
上级 c6b069e9
...@@ -279,6 +279,7 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask) ...@@ -279,6 +279,7 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE); slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
ctrl->cmd_busy = 1; ctrl->cmd_busy = 1;
smp_mb();
retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
if (retval) if (retval)
err("%s: Cannot write to SLOTCTRL register\n", __func__); err("%s: Cannot write to SLOTCTRL register\n", __func__);
...@@ -759,6 +760,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) ...@@ -759,6 +760,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
/* Check Command Complete Interrupt Pending */ /* Check Command Complete Interrupt Pending */
if (intr_loc & CMD_COMPLETED) { if (intr_loc & CMD_COMPLETED) {
ctrl->cmd_busy = 0; ctrl->cmd_busy = 0;
smp_mb();
wake_up_interruptible(&ctrl->queue); wake_up_interruptible(&ctrl->queue);
} }
......
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