Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
openanolis
cloud-kernel
提交
2bb00c68
cloud-kernel
项目概览
openanolis
/
cloud-kernel
大约 1 年 前同步成功
通知
153
Star
36
Fork
7
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
10
列表
看板
标记
里程碑
合并请求
2
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
cloud-kernel
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
10
Issue
10
列表
看板
标记
里程碑
合并请求
2
合并请求
2
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
2bb00c68
编写于
12月 30, 2013
作者:
T
Tomasz Figa
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'samsung-fixes' into samsung-next-base
上级
ea72dc2c
3fd68c99
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
18 addition
and
12 deletion
+18
-12
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+2
-0
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/boot/dts/exynos5250.dtsi
+1
-1
drivers/clk/samsung/clk-exynos-audss.c
drivers/clk/samsung/clk-exynos-audss.c
+5
-5
drivers/clk/samsung/clk-exynos4.c
drivers/clk/samsung/clk-exynos4.c
+1
-1
drivers/clk/samsung/clk-exynos5250.c
drivers/clk/samsung/clk-exynos5250.c
+9
-5
未找到文件。
Documentation/devicetree/bindings/clock/exynos5250-clock.txt
浏览文件 @
2bb00c68
...
...
@@ -159,6 +159,8 @@ clock which they consume.
mixer 343
hdmi 344
g2d 345
mdma0 346
smmu_mdma0 347
[Clock Muxes]
...
...
arch/arm/boot/dts/exynos5250.dtsi
浏览文件 @
2bb00c68
...
...
@@ -559,7 +559,7 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
clocks = <&clock
271
>;
clocks = <&clock
346
>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
...
...
drivers/clk/samsung/clk-exynos-audss.c
浏览文件 @
2bb00c68
...
...
@@ -26,17 +26,17 @@ static struct clk_onecell_data clk_data;
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8
/* list of all parent clock list */
static
const
char
*
mout_audss_p
[]
=
{
"fin_pll"
,
"fout_epll"
};
static
const
char
*
mout_i2s_p
[]
=
{
"mout_audss"
,
"cdclk0"
,
"sclk_audio0"
};
#ifdef CONFIG_PM_SLEEP
static
unsigned
long
reg_save
[][
2
]
=
{
{
ASS_CLK_SRC
,
0
},
{
ASS_CLK_DIV
,
0
},
{
ASS_CLK_GATE
,
0
},
};
/* list of all parent clock list */
static
const
char
*
mout_audss_p
[]
=
{
"fin_pll"
,
"fout_epll"
};
static
const
char
*
mout_i2s_p
[]
=
{
"mout_audss"
,
"cdclk0"
,
"sclk_audio0"
};
#ifdef CONFIG_PM_SLEEP
static
int
exynos_audss_clk_suspend
(
void
)
{
int
i
;
...
...
drivers/clk/samsung/clk-exynos4.c
浏览文件 @
2bb00c68
...
...
@@ -39,7 +39,7 @@
#define SRC_TOP1 0xc214
#define SRC_CAM 0xc220
#define SRC_TV 0xc224
#define SRC_MFC 0xc
c
28
#define SRC_MFC 0xc
2
28
#define SRC_G3D 0xc22c
#define E4210_SRC_IMAGE 0xc230
#define SRC_LCD0 0xc234
...
...
drivers/clk/samsung/clk-exynos5250.c
浏览文件 @
2bb00c68
...
...
@@ -25,6 +25,7 @@
#define MPLL_LOCK 0x4000
#define MPLL_CON0 0x4100
#define SRC_CORE1 0x4204
#define GATE_IP_ACP 0x8800
#define CPLL_LOCK 0x10020
#define EPLL_LOCK 0x10030
#define VPLL_LOCK 0x10040
...
...
@@ -75,7 +76,6 @@
#define SRC_CDREX 0x20200
#define PLL_DIV2_SEL 0x20a24
#define GATE_IP_DISP1 0x10928
#define GATE_IP_ACP 0x10000
/* list of PLLs to be registered */
enum
exynos5250_plls
{
...
...
@@ -120,7 +120,8 @@ enum exynos5250_clks {
spi2
,
i2s1
,
i2s2
,
pcm1
,
pcm2
,
pwm
,
spdif
,
ac97
,
hsi2c0
,
hsi2c1
,
hsi2c2
,
hsi2c3
,
chipid
,
sysreg
,
pmu
,
cmu_top
,
cmu_core
,
cmu_mem
,
tzpc0
,
tzpc1
,
tzpc2
,
tzpc3
,
tzpc4
,
tzpc5
,
tzpc6
,
tzpc7
,
tzpc8
,
tzpc9
,
hdmi_cec
,
mct
,
wdt
,
rtc
,
tmu
,
fimd1
,
mie1
,
dsim0
,
dp
,
mixer
,
hdmi
,
g2d
,
wdt
,
rtc
,
tmu
,
fimd1
,
mie1
,
dsim0
,
dp
,
mixer
,
hdmi
,
g2d
,
mdma0
,
smmu_mdma0
,
/* mux clocks */
mout_hdmi
=
1024
,
...
...
@@ -354,8 +355,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE
(
smmu_gscl2
,
"smmu_gscl2"
,
"aclk266"
,
GATE_IP_GSCL
,
9
,
0
,
0
),
GATE
(
smmu_gscl3
,
"smmu_gscl3"
,
"aclk266"
,
GATE_IP_GSCL
,
10
,
0
,
0
),
GATE
(
mfc
,
"mfc"
,
"aclk333"
,
GATE_IP_MFC
,
0
,
0
,
0
),
GATE
(
smmu_mfcl
,
"smmu_mfcl"
,
"aclk333"
,
GATE_IP_MFC
,
1
,
0
,
0
),
GATE
(
smmu_mfcr
,
"smmu_mfcr"
,
"aclk333"
,
GATE_IP_MFC
,
2
,
0
,
0
),
GATE
(
smmu_mfcl
,
"smmu_mfcl"
,
"aclk333"
,
GATE_IP_MFC
,
2
,
0
,
0
),
GATE
(
smmu_mfcr
,
"smmu_mfcr"
,
"aclk333"
,
GATE_IP_MFC
,
1
,
0
,
0
),
GATE
(
rotator
,
"rotator"
,
"aclk266"
,
GATE_IP_GEN
,
1
,
0
,
0
),
GATE
(
jpeg
,
"jpeg"
,
"aclk166"
,
GATE_IP_GEN
,
2
,
0
,
0
),
GATE
(
mdma1
,
"mdma1"
,
"aclk266"
,
GATE_IP_GEN
,
4
,
0
,
0
),
...
...
@@ -406,7 +407,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE
(
hsi2c2
,
"hsi2c2"
,
"aclk66"
,
GATE_IP_PERIC
,
30
,
0
,
0
),
GATE
(
hsi2c3
,
"hsi2c3"
,
"aclk66"
,
GATE_IP_PERIC
,
31
,
0
,
0
),
GATE
(
chipid
,
"chipid"
,
"aclk66"
,
GATE_IP_PERIS
,
0
,
0
,
0
),
GATE
(
sysreg
,
"sysreg"
,
"aclk66"
,
GATE_IP_PERIS
,
1
,
0
,
0
),
GATE
(
sysreg
,
"sysreg"
,
"aclk66"
,
GATE_IP_PERIS
,
1
,
CLK_IGNORE_UNUSED
,
0
),
GATE
(
pmu
,
"pmu"
,
"aclk66"
,
GATE_IP_PERIS
,
2
,
CLK_IGNORE_UNUSED
,
0
),
GATE
(
tzpc0
,
"tzpc0"
,
"aclk66"
,
GATE_IP_PERIS
,
6
,
0
,
0
),
GATE
(
tzpc1
,
"tzpc1"
,
"aclk66"
,
GATE_IP_PERIS
,
7
,
0
,
0
),
...
...
@@ -492,6 +494,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE
(
mixer
,
"mixer"
,
"mout_aclk200_disp1"
,
GATE_IP_DISP1
,
5
,
0
,
0
),
GATE
(
hdmi
,
"hdmi"
,
"mout_aclk200_disp1"
,
GATE_IP_DISP1
,
6
,
0
,
0
),
GATE
(
g2d
,
"g2d"
,
"aclk200"
,
GATE_IP_ACP
,
3
,
0
,
0
),
GATE
(
mdma0
,
"mdma0"
,
"aclk266"
,
GATE_IP_ACP
,
1
,
0
,
0
),
GATE
(
smmu_mdma0
,
"smmu_mdma0"
,
"aclk266"
,
GATE_IP_ACP
,
5
,
0
,
0
),
};
static
struct
samsung_pll_rate_table
vpll_24mhz_tbl
[]
__initdata
=
{
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录