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提交 2563afa9 编写于 作者: F Florian Tobias Schandinat
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Merge branch 'viafb-pll' into viafb-next

上级 bf5ea02d e4fcaeff
展开全部 隐藏空白更改
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Showing with 479 addition and 747 deletion
drivers/video/via/dvi.c
浏览文件 @ 2563afa9
...@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp, ...@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
struct crt_mode_table *pDviTiming; struct crt_mode_table *pDviTiming;
unsigned long desirePixelClock, maxPixelClock; unsigned long desirePixelClock, maxPixelClock;
pDviTiming = mode->crtc; pDviTiming = mode->crtc;
desirePixelClock = pDviTiming->clk / 1000000; desirePixelClock = pDviTiming->refresh_rate
* pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
/ 1000000;
maxPixelClock = (unsigned long)viaparinfo-> maxPixelClock = (unsigned long)viaparinfo->
tmds_setting_info->max_pixel_clock; tmds_setting_info->max_pixel_clock;
......
drivers/video/via/hw.c
浏览文件 @ 2563afa9
...@@ -22,342 +22,272 @@ ...@@ -22,342 +22,272 @@
#include <linux/via-core.h> #include <linux/via-core.h>
#include "global.h" #include "global.h"
static struct pll_map pll_value[] = { static struct pll_config cle266_pll_config[] = {
{25175000, {19, 4, 0},
{99, 7, 3}, {26, 5, 0},
{85, 3, 4}, /* ignoring bit difference: 0x00008000 */ {28, 5, 0},
{141, 5, 4}, {31, 5, 0},
{141, 5, 4} }, {33, 5, 0},
{29581000, {55, 5, 0},
{33, 4, 2}, {102, 5, 0},
{66, 2, 4}, /* ignoring bit difference: 0x00808000 */ {53, 6, 0},
{166, 5, 4}, /* ignoring bit difference: 0x00008000 */ {92, 6, 0},
{165, 5, 4} }, {98, 6, 0},
{26880000, {112, 6, 0},
{15, 4, 1}, {41, 7, 0},
{30, 2, 3}, /* ignoring bit difference: 0x00808000 */ {60, 7, 0},
{150, 5, 4}, {99, 7, 0},
{150, 5, 4} }, {100, 7, 0},
{31500000, {83, 8, 0},
{53, 3, 3}, /* ignoring bit difference: 0x00008000 */ {86, 8, 0},
{141, 4, 4}, /* ignoring bit difference: 0x00008000 */ {108, 8, 0},
{176, 5, 4}, {87, 9, 0},
{176, 5, 4} }, {118, 9, 0},
{31728000, {95, 12, 0},
{31, 7, 1}, {115, 12, 0},
{177, 5, 4}, /* ignoring bit difference: 0x00008000 */ {108, 13, 0},
{177, 5, 4}, {83, 17, 0},
{142, 4, 4} }, {67, 20, 0},
{32688000, {86, 20, 0},
{73, 4, 3}, {98, 20, 0},
{146, 4, 4}, /* ignoring bit difference: 0x00008000 */ {121, 24, 0},
{183, 5, 4}, {99, 29, 0},
{146, 4, 4} }, {33, 3, 1},
{36000000, {15, 4, 1},
{101, 5, 3}, /* ignoring bit difference: 0x00008000 */ {23, 4, 1},
{161, 4, 4}, /* ignoring bit difference: 0x00008000 */ {37, 5, 1},
{202, 5, 4}, {83, 5, 1},
{161, 4, 4} }, {85, 5, 1},
{40000000, {94, 5, 1},
{89, 4, 3}, {103, 5, 1},
{89, 4, 3}, /* ignoring bit difference: 0x00008000 */ {109, 5, 1},
{112, 5, 3}, {113, 5, 1},
{112, 5, 3} }, {121, 5, 1},
{41291000, {82, 6, 1},
{23, 4, 1}, {31, 7, 1},
{69, 3, 3}, /* ignoring bit difference: 0x00008000 */ {55, 7, 1},
{115, 5, 3}, {84, 7, 1},
{115, 5, 3} }, {83, 8, 1},
{43163000, {76, 9, 1},
{121, 5, 3}, {127, 9, 1},
{121, 5, 3}, /* ignoring bit difference: 0x00008000 */ {33, 4, 2},
{121, 5, 3}, {75, 4, 2},
{121, 5, 3} }, {119, 4, 2},
{45250000, {121, 4, 2},
{127, 5, 3}, {91, 5, 2},
{127, 5, 3}, /* ignoring bit difference: 0x00808000 */ {118, 5, 2},
{127, 5, 3}, {83, 6, 2},
{127, 5, 3} }, {109, 6, 2},
{46000000, {90, 7, 2},
{90, 7, 2}, {93, 2, 3},
{103, 4, 3}, /* ignoring bit difference: 0x00008000 */ {53, 3, 3},
{129, 5, 3}, {73, 4, 3},
{103, 4, 3} }, {89, 4, 3},
{46996000, {105, 4, 3},
{105, 4, 3}, /* ignoring bit difference: 0x00008000 */ {117, 4, 3},
{131, 5, 3}, /* ignoring bit difference: 0x00808000 */ {101, 5, 3},
{131, 5, 3}, /* ignoring bit difference: 0x00808000 */ {121, 5, 3},
{105, 4, 3} }, {127, 5, 3},
{48000000, {99, 7, 3}
{67, 20, 0}, };
{134, 5, 3}, /* ignoring bit difference: 0x00808000 */
{134, 5, 3}, static struct pll_config k800_pll_config[] = {
{134, 5, 3} }, {22, 2, 0},
{48875000, {28, 3, 0},
{99, 29, 0}, {81, 3, 1},
{82, 3, 3}, /* ignoring bit difference: 0x00808000 */ {85, 3, 1},
{82, 3, 3}, /* ignoring bit difference: 0x00808000 */ {98, 3, 1},
{137, 5, 3} }, {112, 3, 1},
{49500000, {86, 4, 1},
{83, 6, 2}, {166, 4, 1},
{83, 3, 3}, /* ignoring bit difference: 0x00008000 */ {109, 5, 1},
{138, 5, 3}, {113, 5, 1},
{83, 3, 3} }, {121, 5, 1},
{52406000, {131, 5, 1},
{117, 4, 3}, {143, 5, 1},
{117, 4, 3}, /* ignoring bit difference: 0x00008000 */ {153, 5, 1},
{117, 4, 3}, {66, 3, 2},
{88, 3, 3} }, {68, 3, 2},
{52977000, {95, 3, 2},
{37, 5, 1}, {106, 3, 2},
{148, 5, 3}, /* ignoring bit difference: 0x00808000 */ {116, 3, 2},
{148, 5, 3}, {93, 4, 2},
{148, 5, 3} }, {119, 4, 2},
{56250000, {121, 4, 2},
{55, 7, 1}, /* ignoring bit difference: 0x00008000 */ {133, 4, 2},
{126, 4, 3}, /* ignoring bit difference: 0x00008000 */ {137, 4, 2},
{157, 5, 3}, {117, 5, 2},
{157, 5, 3} }, {118, 5, 2},
{57275000, {120, 5, 2},
{0, 0, 0}, {124, 5, 2},
{2, 2, 0}, {132, 5, 2},
{2, 2, 0}, {137, 5, 2},
{157, 5, 3} }, /* ignoring bit difference: 0x00808000 */ {141, 5, 2},
{60466000, {166, 5, 2},
{76, 9, 1}, {170, 5, 2},
{169, 5, 3}, /* ignoring bit difference: 0x00808000 */ {191, 5, 2},
{169, 5, 3}, /* FIXED: old = {72, 2, 3} */ {206, 5, 2},
{169, 5, 3} }, {208, 5, 2},
{61500000, {30, 2, 3},
{86, 20, 0}, {69, 3, 3},
{172, 5, 3}, /* ignoring bit difference: 0x00808000 */ {82, 3, 3},
{172, 5, 3}, {83, 3, 3},
{172, 5, 3} }, {109, 3, 3},
{65000000, {114, 3, 3},
{109, 6, 2}, /* ignoring bit difference: 0x00008000 */ {125, 3, 3},
{109, 3, 3}, /* ignoring bit difference: 0x00008000 */ {89, 4, 3},
{109, 3, 3}, {103, 4, 3},
{109, 3, 3} }, {117, 4, 3},
{65178000, {126, 4, 3},
{91, 5, 2}, {150, 4, 3},
{182, 5, 3}, /* ignoring bit difference: 0x00808000 */ {161, 4, 3},
{109, 3, 3}, {121, 5, 3},
{182, 5, 3} }, {127, 5, 3},
{66750000, {131, 5, 3},
{75, 4, 2}, {134, 5, 3},
{150, 4, 3}, /* ignoring bit difference: 0x00808000 */ {148, 5, 3},
{150, 4, 3}, {169, 5, 3},
{112, 3, 3} }, {172, 5, 3},
{68179000, {182, 5, 3},
{19, 4, 0}, {195, 5, 3},
{114, 3, 3}, /* ignoring bit difference: 0x00008000 */ {196, 5, 3},
{190, 5, 3}, {208, 5, 3},
{191, 5, 3} }, {66, 2, 4},
{69924000, {85, 3, 4},
{83, 17, 0}, {141, 4, 4},
{195, 5, 3}, /* ignoring bit difference: 0x00808000 */ {146, 4, 4},
{195, 5, 3}, {161, 4, 4},
{195, 5, 3} }, {177, 5, 4}
{70159000, };
{98, 20, 0},
{196, 5, 3}, /* ignoring bit difference: 0x00808000 */ static struct pll_config cx700_pll_config[] = {
{196, 5, 3}, {98, 3, 1},
{195, 5, 3} }, {86, 4, 1},
{72000000, {109, 5, 1},
{121, 24, 0}, {110, 5, 1},
{161, 4, 3}, /* ignoring bit difference: 0x00808000 */ {113, 5, 1},
{161, 4, 3}, {121, 5, 1},
{161, 4, 3} }, {131, 5, 1},
{78750000, {135, 5, 1},
{33, 3, 1}, {142, 5, 1},
{66, 3, 2}, /* ignoring bit difference: 0x00008000 */ {143, 5, 1},
{110, 5, 2}, {153, 5, 1},
{110, 5, 2} }, {187, 5, 1},
{80136000, {208, 5, 1},
{28, 5, 0}, {68, 2, 2},
{68, 3, 2}, /* ignoring bit difference: 0x00008000 */ {95, 3, 2},
{112, 5, 2}, {116, 3, 2},
{112, 5, 2} }, {93, 4, 2},
{83375000, {119, 4, 2},
{93, 2, 3}, {133, 4, 2},
{93, 4, 2}, /* ignoring bit difference: 0x00800000 */ {137, 4, 2},
{93, 4, 2}, /* ignoring bit difference: 0x00800000 */ {151, 4, 2},
{117, 5, 2} }, {166, 4, 2},
{83950000, {110, 5, 2},
{41, 7, 0}, {112, 5, 2},
{117, 5, 2}, /* ignoring bit difference: 0x00008000 */ {117, 5, 2},
{117, 5, 2}, {118, 5, 2},
{117, 5, 2} }, {120, 5, 2},
{84750000, {132, 5, 2},
{118, 5, 2}, {137, 5, 2},
{118, 5, 2}, /* ignoring bit difference: 0x00808000 */ {141, 5, 2},
{118, 5, 2}, {151, 5, 2},
{118, 5, 2} }, {166, 5, 2},
{85860000, {175, 5, 2},
{84, 7, 1}, {191, 5, 2},
{120, 5, 2}, /* ignoring bit difference: 0x00808000 */ {206, 5, 2},
{120, 5, 2}, {174, 7, 2},
{118, 5, 2} }, {82, 3, 3},
{88750000, {109, 3, 3},
{31, 5, 0}, {117, 4, 3},
{124, 5, 2}, /* ignoring bit difference: 0x00808000 */ {150, 4, 3},
{174, 7, 2}, /* ignoring bit difference: 0x00808000 */ {161, 4, 3},
{124, 5, 2} }, {112, 5, 3},
{94500000, {115, 5, 3},
{33, 5, 0}, {121, 5, 3},
{132, 5, 2}, /* ignoring bit difference: 0x00008000 */ {127, 5, 3},
{132, 5, 2}, {129, 5, 3},
{132, 5, 2} }, {131, 5, 3},
{97750000, {134, 5, 3},
{82, 6, 1}, {138, 5, 3},
{137, 5, 2}, /* ignoring bit difference: 0x00808000 */ {148, 5, 3},
{137, 5, 2}, {157, 5, 3},
{137, 5, 2} }, {169, 5, 3},
{101000000, {172, 5, 3},
{127, 9, 1}, {190, 5, 3},
{141, 5, 2}, /* ignoring bit difference: 0x00808000 */ {195, 5, 3},
{141, 5, 2}, {196, 5, 3},
{141, 5, 2} }, {208, 5, 3},
{106500000, {141, 5, 4},
{119, 4, 2}, {150, 5, 4},
{119, 4, 2}, /* ignoring bit difference: 0x00808000 */ {166, 5, 4},
{119, 4, 2}, {176, 5, 4},
{149, 5, 2} }, {177, 5, 4},
{108000000, {183, 5, 4},
{121, 4, 2}, {202, 5, 4}
{121, 4, 2}, /* ignoring bit difference: 0x00808000 */ };
{151, 5, 2},
{151, 5, 2} }, static struct pll_config vx855_pll_config[] = {
{113309000, {86, 4, 1},
{95, 12, 0}, {108, 5, 1},
{95, 3, 2}, /* ignoring bit difference: 0x00808000 */ {110, 5, 1},
{95, 3, 2}, {113, 5, 1},
{159, 5, 2} }, {121, 5, 1},
{118840000, {131, 5, 1},
{83, 5, 1}, {135, 5, 1},
{166, 5, 2}, /* ignoring bit difference: 0x00808000 */ {142, 5, 1},
{166, 5, 2}, {143, 5, 1},
{166, 5, 2} }, {153, 5, 1},
{119000000, {164, 5, 1},
{108, 13, 0}, {187, 5, 1},
{133, 4, 2}, /* ignoring bit difference: 0x00808000 */ {208, 5, 1},
{133, 4, 2}, {110, 5, 2},
{167, 5, 2} }, {112, 5, 2},
{121750000, {117, 5, 2},
{85, 5, 1}, {118, 5, 2},
{170, 5, 2}, /* ignoring bit difference: 0x00808000 */ {124, 5, 2},
{68, 2, 2}, {132, 5, 2},
{0, 0, 0} }, {137, 5, 2},
{125104000, {141, 5, 2},
{53, 6, 0}, /* ignoring bit difference: 0x00008000 */ {149, 5, 2},
{106, 3, 2}, /* ignoring bit difference: 0x00008000 */ {151, 5, 2},
{175, 5, 2}, {159, 5, 2},
{0, 0, 0} }, {166, 5, 2},
{135000000, {167, 5, 2},
{94, 5, 1}, {172, 5, 2},
{28, 3, 0}, /* ignoring bit difference: 0x00804000 */ {189, 5, 2},
{151, 4, 2}, {191, 5, 2},
{189, 5, 2} }, {194, 5, 2},
{136700000, {206, 5, 2},
{115, 12, 0}, {208, 5, 2},
{191, 5, 2}, /* ignoring bit difference: 0x00808000 */ {83, 3, 3},
{191, 5, 2}, {88, 3, 3},
{191, 5, 2} }, {109, 3, 3},
{138400000, {112, 3, 3},
{87, 9, 0}, {103, 4, 3},
{116, 3, 2}, /* ignoring bit difference: 0x00808000 */ {105, 4, 3},
{116, 3, 2}, {161, 4, 3},
{194, 5, 2} }, {112, 5, 3},
{146760000, {115, 5, 3},
{103, 5, 1}, {121, 5, 3},
{206, 5, 2}, /* ignoring bit difference: 0x00808000 */ {127, 5, 3},
{206, 5, 2}, {134, 5, 3},
{206, 5, 2} }, {137, 5, 3},
{153920000, {148, 5, 3},
{86, 8, 0}, {157, 5, 3},
{86, 4, 1}, /* ignoring bit difference: 0x00808000 */ {169, 5, 3},
{86, 4, 1}, {172, 5, 3},
{86, 4, 1} }, /* FIXED: old = {84, 2, 1} */ {182, 5, 3},
{156000000, {191, 5, 3},
{109, 5, 1}, {195, 5, 3},
{109, 5, 1}, /* ignoring bit difference: 0x00808000 */ {209, 5, 3},
{109, 5, 1}, {142, 4, 4},
{108, 5, 1} }, {146, 4, 4},
{157500000, {161, 4, 4},
{55, 5, 0}, /* ignoring bit difference: 0x00008000 */ {141, 5, 4},
{22, 2, 0}, /* ignoring bit difference: 0x00802000 */ {150, 5, 4},
{110, 5, 1}, {165, 5, 4},
{110, 5, 1} }, {176, 5, 4}
{162000000,
{113, 5, 1},
{113, 5, 1}, /* ignoring bit difference: 0x00808000 */
{113, 5, 1},
{113, 5, 1} },
{187000000,
{118, 9, 0},
{131, 5, 1}, /* ignoring bit difference: 0x00808000 */
{131, 5, 1},
{131, 5, 1} },
{193295000,
{108, 8, 0},
{81, 3, 1}, /* ignoring bit difference: 0x00808000 */
{135, 5, 1},
{135, 5, 1} },
{202500000,
{99, 7, 0},
{85, 3, 1}, /* ignoring bit difference: 0x00808000 */
{142, 5, 1},
{142, 5, 1} },
{204000000,
{100, 7, 0},
{143, 5, 1}, /* ignoring bit difference: 0x00808000 */
{143, 5, 1},
{143, 5, 1} },
{218500000,
{92, 6, 0},
{153, 5, 1}, /* ignoring bit difference: 0x00808000 */
{153, 5, 1},
{153, 5, 1} },
{234000000,
{98, 6, 0},
{98, 3, 1}, /* ignoring bit difference: 0x00008000 */
{98, 3, 1},
{164, 5, 1} },
{267250000,
{112, 6, 0},
{112, 3, 1}, /* ignoring bit difference: 0x00808000 */
{187, 5, 1},
{187, 5, 1} },
{297500000,
{102, 5, 0}, /* ignoring bit difference: 0x00008000 */
{166, 4, 1}, /* ignoring bit difference: 0x00008000 */
{208, 5, 1},
{208, 5, 1} },
{74481000,
{26, 5, 0},
{125, 3, 3}, /* ignoring bit difference: 0x00808000 */
{208, 5, 3},
{209, 5, 3} },
{172798000,
{121, 5, 1},
{121, 5, 1}, /* ignoring bit difference: 0x00808000 */
{121, 5, 1},
{121, 5, 1} },
{122614000,
{60, 7, 0},
{137, 4, 2}, /* ignoring bit difference: 0x00808000 */
{137, 4, 2},
{172, 5, 2} },
{74270000,
{83, 8, 1},
{208, 5, 3},
{208, 5, 3},
{0, 0, 0} },
{148500000,
{83, 8, 0},
{208, 5, 2},
{166, 4, 2},
{208, 5, 2} }
}; };
/* according to VIA Technologies these values are based on experiment */ /* according to VIA Technologies these values are based on experiment */
...@@ -1692,43 +1622,63 @@ static u32 vx855_encode_pll(struct pll_config pll) ...@@ -1692,43 +1622,63 @@ static u32 vx855_encode_pll(struct pll_config pll)
| pll.multiplier; | pll.multiplier;
} }
u32 viafb_get_clk_value(int clk) static inline u32 get_pll_internal_frequency(u32 ref_freq,
struct pll_config pll)
{ {
u32 value = 0; return ref_freq / pll.divisor * pll.multiplier;
int i = 0; }
while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk) static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll)
i++; {
return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift;
}
if (i == NUM_TOTAL_PLL_TABLE) { static struct pll_config get_pll_config(struct pll_config *config, int size,
printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!"); int clk)
} else { {
switch (viaparinfo->chip_info->gfx_chip_name) { struct pll_config best = config[0];
case UNICHROME_CLE266: const u32 f0 = 14318180; /* X1 frequency */
case UNICHROME_K400: int i;
value = cle266_encode_pll(pll_value[i].cle266_pll);
break;
case UNICHROME_K800: for (i = 1; i < size; i++) {
case UNICHROME_PM800: if (abs(get_pll_output_frequency(f0, config[i]) - clk)
case UNICHROME_CN700: < abs(get_pll_output_frequency(f0, best) - clk))
value = k800_encode_pll(pll_value[i].k800_pll); best = config[i];
break; }
case UNICHROME_CX700: return best;
case UNICHROME_CN750: }
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
value = k800_encode_pll(pll_value[i].cx700_pll);
break;
case UNICHROME_VX855: u32 viafb_get_clk_value(int clk)
case UNICHROME_VX900: {
value = vx855_encode_pll(pll_value[i].vx855_pll); u32 value = 0;
break;
} switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
value = cle266_encode_pll(get_pll_config(cle266_pll_config,
ARRAY_SIZE(cle266_pll_config), clk));
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
value = k800_encode_pll(get_pll_config(k800_pll_config,
ARRAY_SIZE(k800_pll_config), clk));
break;
case UNICHROME_CX700:
case UNICHROME_CN750:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
value = k800_encode_pll(get_pll_config(cx700_pll_config,
ARRAY_SIZE(cx700_pll_config), clk));
break;
case UNICHROME_VX855:
case UNICHROME_VX900:
value = vx855_encode_pll(get_pll_config(vx855_pll_config,
ARRAY_SIZE(vx855_pll_config), clk));
break;
} }
return value; return value;
...@@ -2052,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, ...@@ -2052,7 +2002,7 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
int i; int i;
int index = 0; int index = 0;
int h_addr, v_addr; int h_addr, v_addr;
u32 pll_D_N; u32 pll_D_N, clock;
for (i = 0; i < video_mode->mode_array; i++) { for (i = 0; i < video_mode->mode_array; i++) {
index = i; index = i;
...@@ -2105,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, ...@@ -2105,7 +2055,9 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
&& (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
viafb_load_FIFO_reg(set_iga, h_addr, v_addr); viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
pll_D_N = viafb_get_clk_value(crt_table[index].clk); clock = crt_reg.hor_total * crt_reg.ver_total
* crt_table[index].refresh_rate;
pll_D_N = viafb_get_clk_value(clock);
DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
viafb_set_vclock(pll_D_N, set_iga); viafb_set_vclock(pll_D_N, set_iga);
...@@ -2616,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, ...@@ -2616,35 +2568,43 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
int viafb_get_pixclock(int hres, int vres, int vmode_refresh) int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
{ {
int i; int i;
struct crt_mode_table *best;
struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { if (!vmode)
if ((hres == res_map_refresh_tbl[i].hres) return RES_640X480_60HZ_PIXCLOCK;
&& (vres == res_map_refresh_tbl[i].vres)
&& (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh)) best = &vmode->crtc[0];
return res_map_refresh_tbl[i].pixclock; for (i = 1; i < vmode->mode_array; i++) {
if (abs(vmode->crtc[i].refresh_rate - vmode_refresh)
< abs(best->refresh_rate - vmode_refresh))
best = &vmode->crtc[i];
} }
return RES_640X480_60HZ_PIXCLOCK;
return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total)
* 1000 / best->refresh_rate;
} }
int viafb_get_refresh(int hres, int vres, u32 long_refresh) int viafb_get_refresh(int hres, int vres, u32 long_refresh)
{ {
#define REFRESH_TOLERANCE 3 int i;
int i, nearest = -1, diff = REFRESH_TOLERANCE; struct crt_mode_table *best;
for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { struct VideoModeTable *vmode = viafb_get_mode(hres, vres);
if ((hres == res_map_refresh_tbl[i].hres)
&& (vres == res_map_refresh_tbl[i].vres) if (!vmode)
&& (diff > (abs(long_refresh - return 60;
res_map_refresh_tbl[i].vmode_refresh)))) {
diff = abs(long_refresh - res_map_refresh_tbl[i]. best = &vmode->crtc[0];
vmode_refresh); for (i = 1; i < vmode->mode_array; i++) {
nearest = i; if (abs(vmode->crtc[i].refresh_rate - long_refresh)
} < abs(best->refresh_rate - long_refresh))
best = &vmode->crtc[i];
} }
#undef REFRESH_TOLERANCE
if (nearest > 0) if (abs(best->refresh_rate - long_refresh) > 3)
return res_map_refresh_tbl[nearest].vmode_refresh; return 60;
return 60;
return best->refresh_rate;
} }
static void device_off(void) static void device_off(void)
......
drivers/video/via/hw.h
浏览文件 @ 2563afa9
...@@ -893,8 +893,6 @@ struct iga2_crtc_timing { ...@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
/* VT3410 chipset*/ /* VT3410 chipset*/
#define VX900_FUNCTION3 0x3410 #define VX900_FUNCTION3 0x3410
#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
struct IODATA { struct IODATA {
u8 Index; u8 Index;
u8 Mask; u8 Mask;
......
drivers/video/via/lcd.c
浏览文件 @ 2563afa9
...@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, ...@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
int set_vres = plvds_setting_info->v_active; int set_vres = plvds_setting_info->v_active;
int panel_hres = plvds_setting_info->lcd_panel_hres; int panel_hres = plvds_setting_info->lcd_panel_hres;
int panel_vres = plvds_setting_info->lcd_panel_vres; int panel_vres = plvds_setting_info->lcd_panel_vres;
u32 pll_D_N; u32 pll_D_N, clock;
struct display_timing mode_crt_reg, panel_crt_reg; struct display_timing mode_crt_reg, panel_crt_reg;
struct crt_mode_table *panel_crt_table = NULL; struct crt_mode_table *panel_crt_table = NULL;
struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
...@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, ...@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n"); DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info); viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
plvds_setting_info->vclk = panel_crt_table->clk; clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
* panel_crt_table->refresh_rate;
plvds_setting_info->vclk = clock;
if (set_iga == IGA1) { if (set_iga == IGA1) {
/* IGA1 doesn't have LCD scaling, so set it as centering. */ /* IGA1 doesn't have LCD scaling, so set it as centering. */
viafb_load_crtc_timing(lcd_centering_timging viafb_load_crtc_timing(lcd_centering_timging
...@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, ...@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
fill_lcd_format(); fill_lcd_format();
pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk); pll_D_N = viafb_get_clk_value(clock);
DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N); DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
viafb_set_vclock(pll_D_N, set_iga); viafb_set_vclock(pll_D_N, set_iga);
lcd_patch_skew(plvds_setting_info, plvds_chip_info); lcd_patch_skew(plvds_setting_info, plvds_chip_info);
......
drivers/video/via/share.h
浏览文件 @ 2563afa9
...@@ -627,77 +627,6 @@ ...@@ -627,77 +627,6 @@
#define M2048x1536_R60_HSP NEGATIVE #define M2048x1536_R60_HSP NEGATIVE
#define M2048x1536_R60_VSP POSITIVE #define M2048x1536_R60_VSP POSITIVE
/* define PLL index: */
#define CLK_25_175M 25175000
#define CLK_26_880M 26880000
#define CLK_29_581M 29581000
#define CLK_31_500M 31500000
#define CLK_31_728M 31728000
#define CLK_32_668M 32688000
#define CLK_36_000M 36000000
#define CLK_40_000M 40000000
#define CLK_41_291M 41291000
#define CLK_43_163M 43163000
#define CLK_45_250M 45250000 /* 45.46MHz */
#define CLK_46_000M 46000000
#define CLK_46_996M 46996000
#define CLK_48_000M 48000000
#define CLK_48_875M 48875000
#define CLK_49_500M 49500000
#define CLK_52_406M 52406000
#define CLK_52_977M 52977000
#define CLK_56_250M 56250000
#define CLK_57_275M 57275000
#define CLK_60_466M 60466000
#define CLK_61_500M 61500000
#define CLK_65_000M 65000000
#define CLK_65_178M 65178000
#define CLK_66_750M 66750000 /* 67.116MHz */
#define CLK_68_179M 68179000
#define CLK_69_924M 69924000
#define CLK_70_159M 70159000
#define CLK_72_000M 72000000
#define CLK_74_270M 74270000
#define CLK_78_750M 78750000
#define CLK_80_136M 80136000
#define CLK_83_375M 83375000
#define CLK_83_950M 83950000
#define CLK_84_750M 84750000 /* 84.537Mhz */
#define CLK_85_860M 85860000
#define CLK_88_750M 88750000
#define CLK_94_500M 94500000
#define CLK_97_750M 97750000
#define CLK_101_000M 101000000
#define CLK_106_500M 106500000
#define CLK_108_000M 108000000
#define CLK_113_309M 113309000
#define CLK_118_840M 118840000
#define CLK_119_000M 119000000
#define CLK_121_750M 121750000 /* 121.704MHz */
#define CLK_125_104M 125104000
#define CLK_135_000M 135000000
#define CLK_136_700M 136700000
#define CLK_138_400M 138400000
#define CLK_146_760M 146760000
#define CLK_148_500M 148500000
#define CLK_153_920M 153920000
#define CLK_156_000M 156000000
#define CLK_157_500M 157500000
#define CLK_162_000M 162000000
#define CLK_187_000M 187000000
#define CLK_193_295M 193295000
#define CLK_202_500M 202500000
#define CLK_204_000M 204000000
#define CLK_218_500M 218500000
#define CLK_234_000M 234000000
#define CLK_267_250M 267250000
#define CLK_297_500M 297500000
#define CLK_74_481M 74481000
#define CLK_172_798M 172798000
#define CLK_122_614M 122614000
/* Definition CRTC Timing Index */ /* Definition CRTC Timing Index */
#define H_TOTAL_INDEX 0 #define H_TOTAL_INDEX 0
#define H_ADDR_INDEX 1 #define H_ADDR_INDEX 1
...@@ -722,76 +651,7 @@ ...@@ -722,76 +651,7 @@
/* Definition Video Mode Pixel Clock (picoseconds) /* Definition Video Mode Pixel Clock (picoseconds)
*/ */
#define RES_480X640_60HZ_PIXCLOCK 39722
#define RES_640X480_60HZ_PIXCLOCK 39722 #define RES_640X480_60HZ_PIXCLOCK 39722
#define RES_640X480_75HZ_PIXCLOCK 31747
#define RES_640X480_85HZ_PIXCLOCK 27777
#define RES_640X480_100HZ_PIXCLOCK 23168
#define RES_640X480_120HZ_PIXCLOCK 19081
#define RES_720X480_60HZ_PIXCLOCK 37020
#define RES_720X576_60HZ_PIXCLOCK 30611
#define RES_800X600_60HZ_PIXCLOCK 25000
#define RES_800X600_75HZ_PIXCLOCK 20203
#define RES_800X600_85HZ_PIXCLOCK 17777
#define RES_800X600_100HZ_PIXCLOCK 14667
#define RES_800X600_120HZ_PIXCLOCK 11912
#define RES_800X480_60HZ_PIXCLOCK 33805
#define RES_848X480_60HZ_PIXCLOCK 31756
#define RES_856X480_60HZ_PIXCLOCK 31518
#define RES_1024X512_60HZ_PIXCLOCK 24218
#define RES_1024X600_60HZ_PIXCLOCK 20460
#define RES_1024X768_60HZ_PIXCLOCK 15385
#define RES_1024X768_75HZ_PIXCLOCK 12699
#define RES_1024X768_85HZ_PIXCLOCK 10582
#define RES_1024X768_100HZ_PIXCLOCK 8825
#define RES_1152X864_75HZ_PIXCLOCK 9259
#define RES_1280X768_60HZ_PIXCLOCK 12480
#define RES_1280X800_60HZ_PIXCLOCK 11994
#define RES_1280X960_60HZ_PIXCLOCK 9259
#define RES_1280X1024_60HZ_PIXCLOCK 9260
#define RES_1280X1024_75HZ_PIXCLOCK 7408
#define RES_1280X768_85HZ_PIXCLOCK 6349
#define RES_1440X1050_60HZ_PIXCLOCK 7993
#define RES_1600X1200_60HZ_PIXCLOCK 6172
#define RES_1600X1200_75HZ_PIXCLOCK 4938
#define RES_1280X720_60HZ_PIXCLOCK 13426
#define RES_1200X900_60HZ_PIXCLOCK 17459
#define RES_1920X1080_60HZ_PIXCLOCK 5787
#define RES_1400X1050_60HZ_PIXCLOCK 8214
#define RES_1400X1050_75HZ_PIXCLOCK 6410
#define RES_1368X768_60HZ_PIXCLOCK 11647
#define RES_960X600_60HZ_PIXCLOCK 22099
#define RES_1000X600_60HZ_PIXCLOCK 20834
#define RES_1024X576_60HZ_PIXCLOCK 21278
#define RES_1088X612_60HZ_PIXCLOCK 18877
#define RES_1152X720_60HZ_PIXCLOCK 14981
#define RES_1200X720_60HZ_PIXCLOCK 14253
#define RES_1280X600_60HZ_PIXCLOCK 16260
#define RES_1280X720_50HZ_PIXCLOCK 16538
#define RES_1280X768_50HZ_PIXCLOCK 15342
#define RES_1366X768_50HZ_PIXCLOCK 14301
#define RES_1366X768_60HZ_PIXCLOCK 11646
#define RES_1360X768_60HZ_PIXCLOCK 11799
#define RES_1440X900_60HZ_PIXCLOCK 9390
#define RES_1440X900_75HZ_PIXCLOCK 7315
#define RES_1600X900_60HZ_PIXCLOCK 8415
#define RES_1600X1024_60HZ_PIXCLOCK 7315
#define RES_1680X1050_60HZ_PIXCLOCK 6814
#define RES_1680X1050_75HZ_PIXCLOCK 5348
#define RES_1792X1344_60HZ_PIXCLOCK 4902
#define RES_1856X1392_60HZ_PIXCLOCK 4577
#define RES_1920X1200_60HZ_PIXCLOCK 5173
#define RES_1920X1440_60HZ_PIXCLOCK 4274
#define RES_1920X1440_75HZ_PIXCLOCK 3367
#define RES_2048X1536_60HZ_PIXCLOCK 3742
#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
/* LCD display method /* LCD display method
*/ */
...@@ -822,7 +682,6 @@ struct display_timing { ...@@ -822,7 +682,6 @@ struct display_timing {
struct crt_mode_table { struct crt_mode_table {
int refresh_rate; int refresh_rate;
unsigned long clk;
int h_sync_polarity; int h_sync_polarity;
int v_sync_polarity; int v_sync_polarity;
struct display_timing crtc; struct display_timing crtc;
......
drivers/video/via/viamode.c
浏览文件 @ 2563afa9
此差异已折叠。
drivers/video/via/viamode.h
浏览文件 @ 2563afa9
...@@ -41,14 +41,6 @@ struct patch_table { ...@@ -41,14 +41,6 @@ struct patch_table {
struct io_reg *io_reg_table; struct io_reg *io_reg_table;
}; };
struct res_map_refresh {
int hres;
int vres;
int pixclock;
int vmode_refresh;
};
extern int NUM_TOTAL_RES_MAP_REFRESH;
extern int NUM_TOTAL_CEA_MODES; extern int NUM_TOTAL_CEA_MODES;
extern int NUM_TOTAL_CN400_ModeXregs; extern int NUM_TOTAL_CN400_ModeXregs;
extern int NUM_TOTAL_CN700_ModeXregs; extern int NUM_TOTAL_CN700_ModeXregs;
...@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[]; ...@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
extern struct crt_mode_table CEAM1920x1080[]; extern struct crt_mode_table CEAM1920x1080[];
extern struct VideoModeTable CEA_HDMI_Modes[]; extern struct VideoModeTable CEA_HDMI_Modes[];
extern struct res_map_refresh res_map_refresh_tbl[];
extern struct io_reg CN400_ModeXregs[]; extern struct io_reg CN400_ModeXregs[];
extern struct io_reg CN700_ModeXregs[]; extern struct io_reg CN700_ModeXregs[];
extern struct io_reg KM400_ModeXregs[]; extern struct io_reg KM400_ModeXregs[];
......
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