提交 1f75ff0a 编写于 作者: W Will Deacon 提交者: Catalin Marinas

arm64: generic timer: use virtual counter instead of physical at EL0

We want to use the virtual counter at EL0, as the physical counter
may not track the current clocksource for guests running under a
hypervisor.

This patch updates the vdso and generic timer driver to use the virtual
counter. The kernel EL2 entry code is also updated to ensure that the
virtual offset is initialised to zero.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
上级 45a7905f
......@@ -70,12 +70,12 @@ static inline void __cpuinit arch_counter_enable_user_access(void)
{
u32 cntkctl;
/* Disable user access to the timers and the virtual counter. */
/* Disable user access to the timers and the physical counter. */
asm volatile("mrs %0, cntkctl_el1" : "=r" (cntkctl));
cntkctl &= ~((3 << 8) | (1 << 1));
cntkctl &= ~((3 << 8) | (1 << 0));
/* Enable user access to the physical counter and frequency. */
cntkctl |= 1;
/* Enable user access to the virtual counter and frequency. */
cntkctl |= (1 << 1);
asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl));
}
......
......@@ -158,6 +158,7 @@ ENTRY(el2_setup)
mrs x0, cnthctl_el2
orr x0, x0, #3 // Enable EL1 physical timers
msr cnthctl_el2, x0
msr cntvoff_el2, xzr // Clear virtual offset
/* Populate ID registers. */
mrs x0, midr_el1
......
......@@ -220,9 +220,9 @@ ENTRY(__do_get_tspec)
ldp w11, w12, [vdso_data, #VDSO_CS_MULT]
seqcnt_read w9
/* Read the physical counter. */
/* Read the virtual counter. */
isb
mrs x15, cntpct_el0
mrs x15, cntvct_el0
/* Calculate cycle delta and convert to ns. */
sub x10, x15, x10
......
......@@ -109,7 +109,7 @@ static void __cpuinit arch_timer_setup(struct clock_event_device *clk)
enable_percpu_irq(clk->irq, 0);
/* Ensure the physical counter is visible to userspace for the vDSO. */
/* Ensure the virtual counter is visible to userspace for the vDSO. */
arch_counter_enable_user_access();
}
......
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